CN109613323A - A kind of programmable signal amplitude detection circuit - Google Patents
A kind of programmable signal amplitude detection circuit Download PDFInfo
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- CN109613323A CN109613323A CN201811279437.8A CN201811279437A CN109613323A CN 109613323 A CN109613323 A CN 109613323A CN 201811279437 A CN201811279437 A CN 201811279437A CN 109613323 A CN109613323 A CN 109613323A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
Abstract
A kind of programmable signal amplitude detection circuit of the present invention, including amplitude detection circuit and comparator circuit, amplitude detection circuit is for detecting externally input differential signal CKPWith CKNAmplitude size, with preset threshold reference voltage VTOn the basis of, output reflects externally input differential signal CKPWith CKNAmplitude size amplitude detection voltage VATo comparator circuit, for certain threshold reference voltage VT, amplitude detection voltage VAIt is inversely proportional with externally input differential signal amplitude, and for certain externally input differential signal amplitude, amplitude detection voltage VAWith threshold reference voltage VTIt is directly proportional；Comparator circuit, for comparing amplitude detection voltage VAWith reference comparison voltages VRSize, and generate amplitude indication signal QC, whether sufficiently strong it is used to indicate voltage amplitude.The present invention can be used in the circuits such as high speed signal reception, automatic growth control realizing that high speed signal amplitude flexibly controls.
Description
Technical field
The present invention relates to a kind of programmable signal amplitude detection circuits, belong to high speed interface technical field.
Background technique
Message transmission rate is constantly promoted in the Military Electronic Equipments such as broadband connections, radar navigation and electronic countermeasure.Due to
Transmission channel broadband is limited, is more than the high-frequency clock and data-signal of 5GHz, the general amplitude by control signal for frequency
Reduce distorted signals and distortion, to realize high speed highly reliable signal transmission, while signal transmission system power consumption can be reduced；
However, signal amplitude is too small may since signal will receive the influence of the non-ideal factors such as noise, mismatch in transmission process
The problem of leading to the signal-to-noise ratio of signal reduces, and high-speed data error or high-speed clock signal quality is caused to be deteriorated.In order to realize
The optimum performance of signal transmission is particularly important the amplitude control of high-speed signal transmission.Therefore, how to realize to high speed
The detection of clock or data-signal realizes that the flexible control of high speed signal amplitude is adjusted with accurate, is that this field is urgently to be resolved
Technical problem.
Summary of the invention
Technology of the invention solves the problems, such as: overcoming the deficiencies of the prior art and provide a kind of programmable signal amplitude detection electricity
Road significantly improves precision and flexibility to high speed signal amplitude detection and control, improves the signal quality of transmission, in turn
Be conducive to promotion signal transmission rate and reliability.
Technical solution of the invention are as follows: a kind of programmable signal amplitude detection circuit, the detection circuit include amplitude
Detection circuit and comparator circuit, amplitude detection circuit is for detecting externally input differential signal CKPWith CKNAmplitude size,
With preset threshold reference voltage VTOn the basis of, output reflects externally input differential signal CKPWith CKNAmplitude size width
Degree detection voltage VATo comparator circuit, for certain threshold reference voltage VT, amplitude detection voltage VAWith externally input difference
Sub-signal amplitude is inversely proportional, and for certain externally input differential signal amplitude, amplitude detection voltage VAWith threshold reference
Voltage VTIt is directly proportional；
Comparator circuit, for comparing amplitude detection voltage VAWith reference comparison voltages VRSize, and generate amplitude instruction
Signal QC, whether enough it is used to indicate voltage amplitude.
The amplitude detection circuit, comprising: PMOS tube M1, M2 and M3, resistance R1 and R2, capacitor C1, C2 and C3；
The grid connecting resistance R1 and capacitor C1 of PMOS tube M1, source electrode are grounded GND, the drain electrode for the connection PMOS tube M2 that drains,
The drain electrode of PMOS tube M3 and capacitor C3, and as amplitude detection voltage VAOutput end；The other end of resistance R1 connects resistance R2,
And it is connected to input terminal VT, another termination clock input signal anode CK of capacitor C1P, the other end ground connection GND of capacitor C3；
The grid connecting resistance R2 and capacitor C2 of PMOS tube M2, source electrode are grounded GND；Another termination clock input signal negative terminal of capacitor C2
CKN；The grid of PMOS tube M3 meets bias voltage VBP, source electrode meets power vd D.
The programmable high-speed signal amplitude detection circuit further includes threshold program circuit, and threshold program circuit is for generating
Threshold reference voltage VTWith reference comparison voltages VR, by threshold reference voltage VTIt is sent to amplitude detection circuit, will be referred to more electric
Press VRIt is sent to comparator.
The threshold program circuit, comprising: NMOS tube M7 and M8, resistance R4, R5 and R6 and resistance serializer circuit；
The grid of the grid connection M8 of NMOS tube M7, and connect bias voltage VBN, source electrode ground connection GND, drain electrode connects programmable
Resistance string end VRn；
NMOS tube M8 source electrode is grounded GND, and drain connecting resistance R4；Another terminating resistor R5 of resistance R4, and compare as reference
Voltage VROutput end；Another termination power vd D of resistance R5；A termination power vd D of resistance R6, another terminating resistor string are first
Hold VRp, resistance string will be input to its head end VRpVoltage, and divider node is as threshold reference voltage VTOutput end.
The resistance serializer circuit is programmable resistance serializer circuit, comprising: N number of identical resistance Rs1~RsN, N number of identical
Switch S1~SN and capacitor Cf, N are more than or equal to 1；
The head end of resistance Rs1 is connected with the input terminal of switch S1, and is connected to resistance string VRnEnd；The end of resistance Rs1 with
The head end of resistance Rs2 is connected with the input terminal of switch S2；The input of the end of resistance Rs2 and the head end of resistance Rs3 and switch S3
End is connected, and so on, the end of resistance RsN-1 is connected with the input terminal of the head end of resistance RsN and switch SN；Resistance RsN's
End is connected to resistance string VRpEnd；The control signal of N number of identical switch Sn is Kn and NKn, and output termination capacitor Cf is connected, and
As threshold reference voltage VTOutput port, wherein the other end of 0 < n≤N, capacitor Cf are grounded GND.
The resistance serializer circuit further includes decoding circuit, decoding circuit, for matching confidence to the M position binary code received
Number A<M:1>is decoded, and control the signal Kn and NKn of N number of identical switch Sn is obtained, wherein 0<n≤N, N=2M。
The decoding circuit is encoded using one-hot encoding, i.e. digit N after A<M:1>decoding is equal to status number N, and
Different conditions have and only one and other differences.
The decoding circuit, comprising: M input inverter, N number of NAND gate and N number of output phase inverter, wherein N=2M；
M-th of input inverter, for carrying out logical not operation to configuration code A<m>, output controls signal NA<m>, wherein
1≤m≤M；
N-th of NAND gate, for carrying out NAND Logic operation, output switch to control signal A<1:n-1>and NA<n:M>
Signal Kn；Kn is input to n-th of output phase inverter and generates switch inverted signal NKn；Only as A<M:n>=0, A<n-1:1>=1
When, Kn=0, NKn=1, otherwise Kn=1, NKn=0.
The programmable high-speed signal amplitude detection circuit further includes biasing circuit, for generating biasing circuit for providing
Bias voltage V needed for amplitude detection circuit and threshold program circuitBPAnd VBN。
The biasing circuit, comprising: NMOS tube M4, M5, PMOS tube M6 and resistance R4；
The one end resistance R4 connects the drain electrode of NMOS tube M4, and the other end connects the grid and current source Is of NMOS tube M4, M5
Negative terminal, and as bias voltage VBNOutput end；The source electrode of NMOS tube M4 is grounded GND；The positive termination power vd D of current source Is；
The source electrode of NMOS tube M5 is grounded GND, and drain electrode connects grid and the drain electrode of PMOS tube M6, and as bias voltage VBPOutput end；
The source electrode of PMOS tube M6 meets power vd D.
The present invention has the beneficial effect that compared with prior art
(1), the programmable high-speed signal amplitude detection circuit in the present invention can real-time monitoring high speed signal amplitude, when being more than
After certain threshold value, the programming Control to the threshold value is may be implemented by input configuration signal, so that width in output amplitude indication signal
Degree detection circuit can satisfy different application demands；
It (2), will not be right except the programmable high-speed signal amplitude detection circuit in the present invention is independently of high-speed signal paths
High speed transmission of signals brings additional effect, meanwhile, it, can be independent to close programmable high-speed letter by configuring after amplitude locking
Number amplitude detection circuit reduces system power dissipation；
(3), the threshold program circuit in the present invention is led to by configuring signal realization to the programming Control of reference threshold voltage
Expansion decoder architecture and resistance string length are crossed, can improve threshold program very easily by configuration signal extension to N
Precision, and can expanded threshold value programmed range.
(4), bias circuit construction of the present invention is simple, only needs external current source biasing can be for amplitude detection circuit and threshold
The bias voltage being worth needed for programmed circuit provides, enhances the Stability and dependability of circuit.
(5), the programmable high-speed signal amplitude detection circuit in the present invention can be realized high-frequency clock and data-signal width
Degree detection, circuit structure is simple, low in energy consumption, high reliablity；
Detailed description of the invention
Fig. 1 is a kind of programmable high-speed signal amplitude detection circuit structure block diagram of the embodiment of the present invention；
Fig. 2 is the amplitude detection circuit structure chart of the embodiment of the present invention；
Fig. 3 is the structure chart of the threshold program circuit of the embodiment of the present invention；
Fig. 4 is the structure chart of the decoding circuit of the embodiment of the present invention；
Fig. 5 is the structure chart of the resistance serializer circuit of the embodiment of the present invention；
Fig. 6 is the structure chart of the biasing circuit of the embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, public to the present invention below in conjunction with attached drawing
Embodiment is described in further detail.
As shown in Figure 1, a kind of programmable high-speed signal amplitude detection circuit, comprising: amplitude detection circuit, threshold program electricity
Road, biasing circuit and comparator circuit.
Amplitude detection circuit is for detecting externally input differential signal CKPWith CKNAmplitude size, with preset threshold value
Reference voltage VTOn the basis of, output reflects externally input differential signal CKPWith CKNAmplitude size amplitude detection voltage VA
To comparator circuit, for certain threshold reference voltage VT, amplitude detection voltage VAWith externally input differential signal amplitude at
Inverse ratio, and for certain externally input differential signal amplitude, amplitude detection voltage VAWith threshold reference voltage VTIt is directly proportional；
Threshold program circuit, threshold program circuit is for generating threshold reference voltage VTWith reference comparison voltages VR, by threshold value
Reference voltage VTIt is sent to amplitude detection circuit, by reference comparison voltages VRIt is sent to comparator.
Biasing circuit, for generating biasing circuit for biasing needed for providing amplitude detection circuit and threshold program circuit
Voltage VBPAnd VBN。
Comparator circuit, for comparing amplitude detection voltage VAWith reference comparison voltages VRSize, and generate amplitude instruction
Signal QC。
The embodiment of the present invention, and realized according to configuration signal A<2:0>to threshold reference voltage VTPLC technology,
High-speed differential signal CKPWith CKNAmplitude be lower than threshold voltage when, amplitude detection voltage VAHigher than reference comparison voltages VR, at this time
Compare output amplitude indication signal QCIt is 1；As high-speed differential signal CKPWith CKNAmplitude when increasing to threshold voltage, amplitude inspection
Survey voltage VALower than reference comparison voltages VR, compare output amplitude indication signal Q at this timeCIt is 0, is achieved in high speed signal
Amplitude detection function.Meanwhile configuration signal can be with flexible configuration threshold reference voltage VT, and then realize and high speed signal amplitude is examined
The threshold value of slowdown monitoring circuit is programmed control.
As shown in Fig. 2, in a kind of programmable high-speed signal amplitude detection circuit, the amplitude detection circuit, comprising: PMOS
Pipe M1, M2 and M3, resistance R1 and R2, capacitor C1, C2 and C3；
The grid connecting resistance R1 and capacitor C1 of PMOS tube M1, source electrode are grounded GND, the drain electrode for the connection PMOS tube M2 that drains,
The drain electrode of PMOS tube M3 and capacitor C3, and as amplitude detection voltage VAOutput end；The other end of resistance R1 connects resistance R2,
And it is connected to input terminal VT, another termination clock input signal anode CK of capacitor C1P, the other end ground connection GND of capacitor C3；
The grid connecting resistance R2 and capacitor C2 of PMOS tube M2, source electrode are grounded GND；Another termination clock input signal negative terminal of capacitor C2
CKN；The grid of PMOS tube M3 meets bias voltage VBP, source electrode meets power vd D.
Capacitor C1, C2 are used for high speed signal AC coupled, and height can be isolated while obtaining high speed signal amplitude information
The common mode electrical level of fast signal, for certain threshold reference voltage VT, with the increase of high speed signal amplitude, amplitude detection voltage
VAIt gradually decreases；And for certain signal amplitude, amplitude detection voltage VAIt can be with threshold reference voltage VTIncrease and increase
Greatly；
As shown in figure 3, in a kind of programmable high-speed signal amplitude detection circuit, the threshold program circuit, comprising:
NMOS tube M7 and M8, resistance R4, R5 and R6 and resistance serializer circuit；
The grid of the grid connection M8 of NMOS tube M7, and connect bias voltage VBN, source electrode ground connection GND, drain electrode connects programmable
Resistance string end VRn；
NMOS tube M8 source electrode is grounded GND, and drain connecting resistance R4；Another terminating resistor R5 of resistance R4, and compare as reference
Voltage VROutput end；Another termination power vd D of resistance R5；A termination power vd D of resistance R6, another terminating resistor string are first
Hold VRp, resistance string will be input to its head end VRpVoltage, and divider node is as threshold reference voltage VTOutput end.
Resistance R5, R6 resistance value is equal, and R6 and programmable resistance string entirety resistance value are equal, i.e. reference comparison voltages VREqual to can
Programming resistors string VRpHold voltage；Bias voltage VBNThe size of current of resistance is flowed through in control, determines the programming of threshold reference voltage
Accuracy rating.
The resistance serializer circuit is programmable resistance serializer circuit, comprising: N number of identical resistance Rs1~RsN, N number of identical
Switch S1~SN and capacitor Cf, N are more than or equal to 1；
The head end of resistance Rs1 is connected with the input terminal of switch S1, and is connected to resistance string VRnEnd；The end of resistance Rs1 with
The head end of resistance Rs2 is connected with the input terminal of switch S2；The input of the end of resistance Rs2 and the head end of resistance Rs3 and switch S3
End is connected, and so on, the end of resistance RsN-1 is connected with the input terminal of the head end of resistance RsN and switch SN；Resistance RsN's
End is connected to resistance string VRpEnd；The control signal of N number of identical switch Sn is Kn and NKn, and output termination capacitor Cf is connected, and
As threshold reference voltage VTOutput port, wherein the other end of 0 < n≤N, capacitor Cf are grounded GND.
The resistance serializer circuit further includes decoding circuit, decoding circuit, for matching confidence to the M position binary code received
Number A<M:1>is decoded, and control the signal Kn and NKn of N number of identical switch Sn is obtained, wherein 0<n≤N, N=2M.And it configures
The digit of signal A determines the programming precision of threshold reference voltage；And the resistance value of resistance can according to different design requirements into
Row adjustment.
The decoding circuit is encoded using one-hot encoding, i.e. digit N after A<M:1>decoding is equal to status number N, and
Different conditions have and only one and other differences.
The decoding circuit, comprising: M input inverter, N number of NAND gate and N number of output phase inverter, wherein N=2M；
M-th of input inverter, for carrying out logical not operation to configuration code A<m>, output controls signal NA<m>, wherein
1≤m≤M；
N-th of NAND gate, for carrying out NAND Logic operation, output switch to control signal A<1:n-1>and NA<n:M>
Signal Kn；Kn is input to n-th of output phase inverter and generates switch inverted signal NKn；Only as A<M:n>=0, A<n-1:1>=1
When, Kn=0, NKn=1, otherwise Kn=1, NKn=0.
As shown in figure 4, configuration signal is A [2:0], and the decoding circuit is for receiving three two in the embodiment of the present invention
Ary codes configure signal A<2:0>, decode to A<2:0>, control signal Ki and NKi are obtained, wherein 0<i≤8；The decoding
Circuit, comprising: three input inverters, eight NAND gates and eight output phase inverters；
First input inverter, for carrying out logical not operation, output control signal NA1 to configuration code A<1>；
Second input inverter, for carrying out logical not operation, output control signal NA2 to configuration code A<2>；
Third input inverter, for carrying out logical not operation, output control signal NA3 to configuration code A<3>；
First NAND gate, for carrying out NAND Logic operation, output switching signal K1 to control signal NA1, NA2 and NA3；
K1 is input to the first output phase inverter and generates switch inverted signal NK1；Only as A<3:1>=000, K1=0, NK1=1；
Second NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A1 and control signal NA2, NA3
Signal K2；K2 is input to the second output phase inverter and generates switch inverted signal NK2；Only as A<3:1>=001, K2=0, NK2
=1；
Third NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A2 and control signal NA1, NA3
Signal K3；K3 is input to third output phase inverter and generates switch inverted signal NK3；Only as A<3:1>=010, K3=0, NK3
=1；
4th NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A1, A2 and control signal NA3
Signal K4；K4 is input to the 4th output phase inverter and generates switch inverted signal NK4；Only as A<3:1>=011, K4=0, NK4
=1；
5th NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A3 and control signal NA1, NA2
Signal K5；K5 is input to the 5th output phase inverter and generates switch inverted signal NK5；Only as A<3:1>=100, K5=0, NK5
=1；
6th NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A1, A3 and control signal NA2
Signal K6；K6 is input to the 6th output phase inverter and generates switch inverted signal NK6；Only as A<3:1>=101, K6=0, NK6
=1；
7th NAND gate, for carrying out NAND Logic operation, output switch to configuration signal A2, A3 and control signal NA1
Signal K7；K7 is input to the 7th output phase inverter and generates switch inverted signal NK7；Only as A<3:1>=110, K7=0, NK7
=1；
8th NAND gate, for carrying out NAND Logic operation, output switching signal K8 to configuration signal A1, A2 and A3；K8
It is input to the 8th output phase inverter and generates switch inverted signal NK8；Only as A<3:1>=111, K8=0, NK8=1；
The decoding circuit uses one-hot encoding principle, i.e. digit is equal to status number, and different conditions have and only one
With other differences.For example, corresponding decimal number is 0, then 8 bit switches are believed when configuring signal A<3:1>=000
Number Ki decoding result is 11111110, and switch inverted signal NKi is 00000001, at this time resistance string lowest order Voltage On state to threshold value
Reference voltage VTOutput end；When configuring signal A<3:1>=100, corresponding decimal number is 4, then 8 bit switch signal Ki
Decoding result is 11101111, and switch inverted signal NKi is 00010000, at this time resistance string interposition Voltage On state to threshold reference
Voltage VTOutput end；And when configuring signal A<3:1>=111, corresponding decimal number is 7, then 8 bit switch signal Ki are translated
Code result is 01111111, and switch inverted signal NKi is 10000000, at this time resistance string highest order Voltage On state to threshold reference electricity
Press VTOutput end；
As shown in figure 5, in the present embodiment, resistance serializer circuit identical is opened by eight identical resistance Rs1~Rs8, eight
Close S1~S8 and capacitor Cf composition；The head end of resistance Rs1 is connected with the input terminal of switch S1, and is connected to resistance string VRnEnd；Electricity
The end of resistance Rs1 is connected with the input terminal of the head end of resistance Rs2 and switch S2；The end of resistance Rs2 and the head end of resistance Rs3 and
The input terminal of switch S3 is connected, and so on, the end of resistance Rs7 is connected with the input terminal of the head end of resistance Rs8 and switch S8；
The end of resistance Rs8 is connected to resistance string VRpEnd；The control signal of eight identical switch Sj is Kj and NKj, output termination electricity
Hold Cf to be connected, and as VTOutput port, wherein 0 < j≤8；The other end of capacitor Cf is grounded GND.
Corresponding N configuration signal A<N:1>, resistance number are 2N, switch number is 2N.Therefore, increase configuration signal digit
Threshold program precision can be improved, but need the quantity of resistance and switch that can sharply increase.Switching circuit Sj is only being controlled
It is opened in the case where signal Kj=0 and NKj=1；Capacitor Cf stablizes output threshold reference voltage V for decoupling filteringT。
As shown in fig. 6, the biasing circuit, comprising: NMOS tube M4, M5, PMOS tube M6 and resistance R4.
The one end resistance R4 connects the drain electrode of NMOS tube M4, and the other end connects the grid and current source Is of NMOS tube M4, M5
Negative terminal, and as bias voltage VBNOutput end；The source electrode of NMOS tube M4 is grounded GND；The positive termination power vd D of current source Is；
The source electrode of NMOS tube M5 is grounded GND, and drain electrode connects grid and the drain electrode of PMOS tube M6, and as bias voltage VBPOutput end；
The source electrode of PMOS tube M6 meets power vd D.
In addition, the comparator circuit is for comparing amplitude detection voltage VAWith reference comparison voltages VRSize, and generate
Amplitude indication signal QC；Work as VA>VRWhen, output amplitude indication signal QC=1, indicate externally input differential signal CKPWith CKNWidth
Degree is not big enough, needs to be dialled further up；Otherwise output amplitude indication signal QC=0, indicate that signal amplitude is sufficiently large.
In conclusion programmable high-speed signal amplitude detection circuit of the present invention can be realized high-frequency clock and data
Signal amplitude detection, circuit structure is simple, low in energy consumption, high reliablity；And it may be implemented by input configuration signal to the threshold value
Programming Control so that amplitude detection circuit can satisfy different application demands；
Various embodiments are described in a progressive manner in this explanation, the highlights of each of the examples are with its
The difference of his embodiment, the same or similar parts between the embodiments can be referred to each other.
The above, optimal specific embodiment only of the invention, but scope of protection of the present invention is not limited thereto,
In the technical scope disclosed by the present invention, any changes or substitutions that can be easily thought of by anyone skilled in the art,
It should be covered by the protection scope of the present invention.
The content that description in the present invention is not described in detail belongs to the well-known technique of professional and technical personnel in the field.
Claims (10)
1. a kind of programmable signal amplitude detection circuit, it is characterised in that: including amplitude detection circuit and comparator circuit, amplitude
Detection circuit is for detecting externally input differential signal CKPWith CKNAmplitude size, with preset threshold reference voltage VTFor
Benchmark, output reflect externally input differential signal CKPWith CKNAmplitude size amplitude detection voltage VATo comparator circuit,
For certain threshold reference voltage VT, amplitude detection voltage VAIt is inversely proportional with externally input differential signal amplitude, and for one
Fixed externally input differential signal amplitude, amplitude detection voltage VAWith threshold reference voltage VTIt is directly proportional；
Comparator circuit, for comparing amplitude detection voltage VAWith reference comparison voltages VRSize, and generate amplitude indication signal
QC, whether enough it is used to indicate voltage amplitude.
2. a kind of programmable signal amplitude detection circuit according to claim 1, which is characterized in that the amplitude detection electricity
Road, comprising: PMOS tube M1, M2 and M3, resistance R1 and R2, capacitor C1, C2 and C3；
The grid connecting resistance R1 and capacitor C1 of PMOS tube M1, source electrode are grounded GND, the drain electrode of drain electrode connection PMOS tube M2, PMOS tube
The drain electrode of M3 and capacitor C3, and as amplitude detection voltage VAOutput end；The other end of resistance R1 connects resistance R2, and connects
To input terminal VT, another termination clock input signal anode CK of capacitor C1P, the other end ground connection GND of capacitor C3；PMOS tube M2
Grid connecting resistance R2 and capacitor C2, source electrode be grounded GND；Another termination clock input signal negative terminal CK of capacitor C2N；PMOS tube
The grid of M3 meets bias voltage VBP, source electrode meets power vd D.
3. a kind of programmable signal amplitude detection circuit according to claim 1, it is characterised in that: further include threshold program
Circuit, threshold program circuit is for generating threshold reference voltage VTWith reference comparison voltages VR, by threshold reference voltage VTIt is sent to
Amplitude detection circuit, by reference comparison voltages VRIt is sent to comparator.
4. a kind of programmable signal amplitude detection circuit according to claim 3, which is characterized in that the threshold program electricity
Road, comprising: NMOS tube M7 and M8, resistance R4, R5 and R6 and resistance serializer circuit；
The grid of the grid connection M8 of NMOS tube M7, and connect bias voltage VBN, source electrode be grounded GND, drain electrode connect programmable resistance
String end VRn；
NMOS tube M8 source electrode is grounded GND, and drain connecting resistance R4；Another terminating resistor R5 of resistance R4, and as reference comparison voltages VR
Output end；Another termination power vd D of resistance R5；Termination a power vd D, another terminating resistor string head end V of resistance R6Rp,
Resistance string will be input to its head end VRpVoltage, and divider node is as threshold reference voltage VTOutput end.
5. a kind of programmable signal amplitude detection circuit according to claim 4, which is characterized in that the resistance serializer circuit
For programmable resistance serializer circuit, comprising: N number of identical resistance Rs1~RsN, N number of identical switch S1~SN and capacitor Cf, N are big
In equal to 1；
The head end of resistance Rs1 is connected with the input terminal of switch S1, and is connected to resistance string VRnEnd；The end of resistance Rs1 and resistance
The head end of Rs2 is connected with the input terminal of switch S2；The end of resistance Rs2 and the head end of resistance Rs3 and the input terminal phase of switch S3
Even, and so on, the end of resistance RsN-1 is connected with the input terminal of the head end of resistance RsN and switch SN；The end of resistance RsN
It is connected to resistance string VRpEnd；The control signal of N number of identical switch Sn is Kn and NKn, and output termination capacitor Cf is connected, and conduct
Threshold reference voltage VTOutput port, wherein the other end of 0 < n≤N, capacitor Cf are grounded GND.
6. a kind of programmable signal amplitude detection circuit according to claim 5, which is characterized in that the resistance serializer circuit
It further include decoding circuit, decoding circuit obtains N for decoding to M position binary code configuration signal A<M:1>received
Control the signal Kn and NKn of a identical switch Sn, wherein 0 < n≤N, N=2M。
7. a kind of programmable signal amplitude detection circuit according to claim 6, which is characterized in that the decoding circuit is adopted
Encoded with one-hot encoding, i.e. A<M:1>decoding after digit N be equal to status number N, and different conditions have and only one with
Other differences.
8. a kind of programmable high-speed signal amplitude detection circuit according to claim 7, which is characterized in that the decoding electricity
Road, comprising: M input inverter, N number of NAND gate and N number of output phase inverter, wherein N=2M；
M-th of input inverter, for carrying out logical not operation, output control signal NA<m>, wherein 1≤m to configuration code A<m>
≤M；
N-th of NAND gate, for carrying out NAND Logic operation, output switching signal to control signal A<1:n-1>and NA<n:M>
Kn；Kn is input to n-th of output phase inverter and generates switch inverted signal NKn；Only as A<M:n>=0, A<n-1:1>=1, Kn
=0, NKn=1, otherwise Kn=1, NKn=0.
9. a kind of programmable signal amplitude detection circuit according to claim 4, it is characterised in that it further include biasing circuit,
For generating biasing circuit for bias voltage V needed for providing amplitude detection circuit and threshold program circuitBPAnd VBN。
10. a kind of programmable signal amplitude detection circuit according to claim 9, which is characterized in that the biasing circuit,
It include: NMOS tube M4, M5, PMOS tube M6 and resistance R4；
The one end resistance R4 connects the drain electrode of NMOS tube M4, and the other end connects the grid of NMOS tube M4, M5 and the negative terminal of current source Is,
And as bias voltage VBNOutput end；The source electrode of NMOS tube M4 is grounded GND；The positive termination power vd D of current source Is；NMOS tube
The source electrode of M5 is grounded GND, and drain electrode connects grid and the drain electrode of PMOS tube M6, and as bias voltage VBPOutput end；PMOS tube M6
Source electrode meet power vd D.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811279437.8A CN109613323B (en) | 2018-10-30 | 2018-10-30 | Programmable signal amplitude detection circuit |
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|---|---|---|---|
| CN201811279437.8A CN109613323B (en) | 2018-10-30 | 2018-10-30 | Programmable signal amplitude detection circuit |
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| CN109613323A true CN109613323A (en) | 2019-04-12 |
| CN109613323B CN109613323B (en) | 2021-04-13 |
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| CN201811279437.8A Active CN109613323B (en) | 2018-10-30 | 2018-10-30 | Programmable signal amplitude detection circuit |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111208347A (en) * | 2020-03-16 | 2020-05-29 | 成都纳能微电子有限公司 | High-speed differential signal amplitude detection circuit |
| CN112383291A (en) * | 2020-11-10 | 2021-02-19 | 北京智芯微电子科技有限公司 | Digital controllable delay chain |
| CN116859112A (en) * | 2023-09-05 | 2023-10-10 | 中国电子科技集团公司第十四研究所 | Dynamic amplitude monitoring circuit for improving precision |
| CN117650072A (en) * | 2023-11-28 | 2024-03-05 | 广州润芯信息技术有限公司 | Process detection method, system and circuit |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1671050A (en) * | 2004-09-30 | 2005-09-21 | 东南大学 | Fixed amplitude circuit for voltage controlled oscillator |
| JP2006067607A (en) * | 2005-09-16 | 2006-03-09 | Oki Electric Ind Co Ltd | Am modulation signal receiving circuit |
| CN1909360A (en) * | 2005-08-01 | 2007-02-07 | 马维尔国际贸易有限公司 | Low-noise high-stability crystal oscillator |
| CN101162910A (en) * | 2006-10-10 | 2008-04-16 | 北京六合万通微电子技术有限公司 | Local oscillator leakage automatic eliminator |
| CN101557122A (en) * | 2009-02-24 | 2009-10-14 | 深圳市民展科技开发有限公司 | Duplicate supply selection circuit |
| CN101636911A (en) * | 2007-01-31 | 2010-01-27 | 英特尔公司 | Vco amplitude control |
| US7688154B1 (en) * | 2006-06-21 | 2010-03-30 | Exar Corporation | Amplitude regulated crystal oscillator |
| US20110199154A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Automatic level control |
| CN102624346A (en) * | 2011-09-22 | 2012-08-01 | 杭州中科微电子有限公司 | Automatic gain amplification circuit with inverse exponential characteristic type digital control circuit |
| CN105450222A (en) * | 2014-08-13 | 2016-03-30 | 南京能瑞自动化设备股份有限公司 | VCO swing automatic calibration circuit and method |
-
2018
- 2018-10-30 CN CN201811279437.8A patent/CN109613323B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1671050A (en) * | 2004-09-30 | 2005-09-21 | 东南大学 | Fixed amplitude circuit for voltage controlled oscillator |
| CN1909360A (en) * | 2005-08-01 | 2007-02-07 | 马维尔国际贸易有限公司 | Low-noise high-stability crystal oscillator |
| JP2006067607A (en) * | 2005-09-16 | 2006-03-09 | Oki Electric Ind Co Ltd | Am modulation signal receiving circuit |
| US7688154B1 (en) * | 2006-06-21 | 2010-03-30 | Exar Corporation | Amplitude regulated crystal oscillator |
| CN101162910A (en) * | 2006-10-10 | 2008-04-16 | 北京六合万通微电子技术有限公司 | Local oscillator leakage automatic eliminator |
| CN101636911A (en) * | 2007-01-31 | 2010-01-27 | 英特尔公司 | Vco amplitude control |
| CN101557122A (en) * | 2009-02-24 | 2009-10-14 | 深圳市民展科技开发有限公司 | Duplicate supply selection circuit |
| US20110199154A1 (en) * | 2010-02-12 | 2011-08-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Automatic level control |
| CN102624346A (en) * | 2011-09-22 | 2012-08-01 | 杭州中科微电子有限公司 | Automatic gain amplification circuit with inverse exponential characteristic type digital control circuit |
| CN105450222A (en) * | 2014-08-13 | 2016-03-30 | 南京能瑞自动化设备股份有限公司 | VCO swing automatic calibration circuit and method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111208347A (en) * | 2020-03-16 | 2020-05-29 | 成都纳能微电子有限公司 | High-speed differential signal amplitude detection circuit |
| CN112383291A (en) * | 2020-11-10 | 2021-02-19 | 北京智芯微电子科技有限公司 | Digital controllable delay chain |
| CN116859112A (en) * | 2023-09-05 | 2023-10-10 | 中国电子科技集团公司第十四研究所 | Dynamic amplitude monitoring circuit for improving precision |
| CN116859112B (en) * | 2023-09-05 | 2023-11-21 | 中国电子科技集团公司第十四研究所 | Dynamic amplitude monitoring circuit for improving precision |
| CN117650072A (en) * | 2023-11-28 | 2024-03-05 | 广州润芯信息技术有限公司 | Process detection method, system and circuit |
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