CN117650072A - Process detection method, system and circuit - Google Patents
Process detection method, system and circuit Download PDFInfo
- Publication number
- CN117650072A CN117650072A CN202311612691.6A CN202311612691A CN117650072A CN 117650072 A CN117650072 A CN 117650072A CN 202311612691 A CN202311612691 A CN 202311612691A CN 117650072 A CN117650072 A CN 117650072A
- Authority
- CN
- China
- Prior art keywords
- mos tube
- voltage
- sample
- resistor
- detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 354
- 238000001514 detection method Methods 0.000 title claims abstract description 238
- 238000013139 quantization Methods 0.000 claims abstract description 31
- 238000012545 processing Methods 0.000 claims abstract description 15
- 230000008030 elimination Effects 0.000 claims description 7
- 238000003379 elimination reaction Methods 0.000 claims description 7
- 238000004364 calculation method Methods 0.000 claims description 6
- 239000003550 marker Substances 0.000 claims description 5
- 238000007689 inspection Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 18
- 230000003068 static effect Effects 0.000 description 6
- 238000012938 design process Methods 0.000 description 4
- 239000000203 mixture Substances 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000013480 data collection Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000009776 industrial production Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Abstract
The invention provides a process detection method, a process detection system and a process detection circuit, wherein the process detection is carried out on a first sample to obtain a process detection voltage; performing reference voltage generation processing on the first sample to obtain a process reference voltage; respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code; and determining the process angle deviation degree of the first sample to obtain a process detection result. The process detection method, the process detection system and the process detection circuit can solve the problem that in the prior art, the process detection result is low in accuracy due to the fact that the process instrument of the detection chip is complex, the process is complex and the process is easily interfered by external factors, and improve the accuracy of the detection result.
Description
Technical Field
The present invention relates to the field of integrated circuit design services, and in particular, to a process detection method, system, and circuit.
Background
In the integrated circuit manufacturing process, the device on the chip is inevitably deviated due to the uncertainty of the pattern transfer of the chip, the process fluctuation and other factors. As feature sizes of semiconductor processes continue to shrink, process variations tend to increase. This makes the constraints adopted in the integrated circuit design process more stringent, and severely limits the performance and power consumption of the integrated circuit.
At present, for the technology of chip detection, more complicated instruments and equipment are mostly used, the occupied area is large, the operation is complex, the dynamic comparison structure is adopted to detect the process deviation, and circuit detection self-adjustment cannot be realized, so that the detection result is easily influenced by external factors such as temperature, voltage and process when strict constraint conditions in other circuit design processes of the chip cannot be relieved, the performance and the power consumption of the chip under different process deviation conditions are restricted, and huge obstruction is generated for industrial production.
Disclosure of Invention
Based on the problems, the embodiment of the invention provides a process detection method, a process detection system and a process detection circuit, which solve the problems of low accuracy of a process detection result caused by complex process instruments and complicated procedures and easy interference of external factors in the process of detecting chips in the prior art.
In order to achieve the above object, an embodiment of the present invention provides a process detection method, including:
performing process detection on the first sample to obtain a process detection voltage;
performing reference voltage generation processing on the first sample to obtain a process reference voltage;
respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code;
And determining the process angle deviation degree of the first sample according to the sample process code to obtain a process detection result.
According to the process detection method provided by the embodiment of the invention, the process code is obtained by designing the detection circuit to obtain the full static voltage and quantizing, the finally obtained multi-byte quantizing result can accurately represent the deviation degree of the process instead of the simple 3 results, and the influence caused by the process deviation is accurately compensated.
Further, the process detection is performed on the first sample to obtain a process detection voltage, which specifically includes:
collecting factory process parameters of the first sample;
obtaining positive temperature coefficient current and negative temperature coefficient current through the voltage relation in the factory technological parameters of the first sample;
performing temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain zero temperature coefficient current;
converting the zero temperature coefficient current into the process detection voltage.
According to the process detection method provided by the embodiment of the invention, the detection result is not affected by temperature any more through the compensation of the temperature coefficient by the detection circuit, and is only related to a single variable, so that the accuracy of the detection result is greatly improved.
Further, the reference voltage generation processing is performed on the first sample to obtain a process reference voltage, which specifically includes:
obtaining a base reference voltage according to the voltage relation in the factory technological parameters of the first sample;
and converting the reference voltage into a reference current, and performing reference elimination mirror image processing to obtain a process reference voltage.
Further, the differential quantization is performed on the process detection voltage and the process reference voltage to obtain a sample process code, which specifically includes:
respectively carrying out differential operation on the process detection voltage and the process reference voltage to obtain a digital code of the detection differential voltage and a digital code of the reference differential voltage;
and carrying out digital-analog quantization calculation according to the detected differential voltage digital code and the reference differential voltage digital code to obtain the process code, wherein the process code consists of a judgment flag bit and a basic digital code.
Further, determining the degree of deviation of the process angle of the first sample according to the sample process code to obtain a process detection result, specifically:
determining the process angle deviation fast angle or slow angle of the first sample according to the positive and negative of the judging zone bit of the process code and the process detection type of the first sample;
When the numerical value of the basic digital code is determined to be larger, determining that the process angle deviation degree of the first sample is larger;
and obtaining a process detection result of the first sample according to the deviation angle judgment result of the judgment marker bit and the deviation degree judgment result of the basic digital code.
The embodiment of the invention also provides a process detection system, which comprises: the device comprises a detection voltage generation module, a reference voltage generation module, a differential quantization module and a process detection result output module;
the detection voltage generation module is used for carrying out process detection on the first sample to obtain a process detection voltage;
the reference voltage generation module is used for carrying out reference voltage generation processing on the first sample to obtain a process reference voltage;
the differential quantization module is used for respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code;
and the process detection result output module is used for determining the process angle deviation degree of the first sample according to the sample process code to obtain a process detection result.
According to the process detection system provided by the embodiment of the invention, the detection of the process deviation is realized through the connection of the modules, the circuit module adopts a simple circuit structure, the loss caused by detection is reduced, the process code is obtained in a mode of obtaining the full static voltage through the detection circuit and quantifying the full static voltage, the deviation result is obtained through the differential result of the process code, the circuit design is not influenced by strict constraint conditions, the process detection can be realized through the circuit, the detection result is often only related to a single variable, the influence of external conditions is avoided, and the accuracy of the detection result is improved.
Further, the detection voltage generating module is configured to perform process detection on a sample to obtain a process detection voltage, and further includes:
the device comprises a data acquisition unit, a temperature coefficient elimination unit and a detection voltage output unit;
the data acquisition unit is used for acquiring the factory technological parameters of the first sample, and obtaining positive temperature coefficient current and negative temperature coefficient current through the voltage relation in the factory technological parameters of the first sample;
the temperature coefficient eliminating unit is used for carrying out temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain zero temperature coefficient current;
the detection voltage output unit is used for converting the zero temperature coefficient current into the process detection voltage.
Further, the reference voltage generating module is configured to perform reference voltage generation processing on the first sample to obtain a process reference voltage, and further includes:
a base reference voltage generation unit and a process reference voltage generation unit;
the reference voltage generating unit is used for obtaining a reference voltage according to the voltage relation in the factory process parameters of the first sample;
the process reference voltage generating unit is used for converting the base reference voltage into base reference current and performing reference elimination mirror image processing to obtain the process reference voltage.
Further, the differential quantization module is configured to differentially quantize the process detection voltage and the process reference voltage, respectively, to obtain a sample process code, and includes:
a differential operation unit and a digital quantization unit;
the differential operation unit is used for respectively carrying out differential operation on the process detection voltage and the process reference voltage to obtain a digital code of the detection differential voltage and a digital code of the reference differential voltage;
the digital quantization unit is used for carrying out digital-to-analog quantization calculation according to the detected differential voltage digital code and the reference differential voltage digital code to obtain the process code, wherein the process code consists of a judgment flag bit and a basic digital code.
Further, the process detection result output module is configured to determine, according to the sample process code, a degree of deviation of a process angle of the first sample, to obtain a process detection result, and specifically includes:
the deviation angle judging unit, the deviation degree judging unit and the process detection result output unit;
the deflection angle judging unit is used for determining a deflection fast angle or a deflection slow angle of the first sample according to the positive and negative of the judging zone bit of the process code and the process detection type of the first sample;
The deviation degree judging unit is used for determining that the process angle deviation degree of the first sample is larger as the numerical value of the basic digital code is larger;
and the process detection result output unit is used for obtaining the process detection result of the first sample according to the deviation angle judgment result of the judgment marker bit and the deviation degree judgment result of the basic digital code.
The embodiment of the invention also provides a process detection circuit, which comprises: the device comprises a process detection circuit, a band gap reference source circuit and an analog-to-digital converter;
the process detection circuit is respectively connected with the band gap reference source circuit and the analog-to-digital converter;
the process detection circuit is used for generating a detection voltage and a corresponding reference voltage;
the band gap reference source circuit is used for generating bias voltage;
the analog-to-digital converter is used for generating a digital code;
wherein the process detection circuit further comprises: an NMOS detection circuit and a PMOS detection circuit.
The process detection circuit provided by the embodiment of the invention has the characteristics of simple circuit structure, small occupied chip area, low power consumption and capability of being turned off after detection is finished, and can repeatedly call the process angles for respectively detecting different parts of the chip, thereby relieving strict constraint conditions in the design process of other circuits of the chip, optimizing the chip power consumption under the condition of different process angles, ensuring that the process detection result is not influenced by too many interference factors, and further improving the accuracy.
Further, the bandgap reference source circuit includes:
the first amplifier, the second amplifier, the first diode, the second diode, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor;
the first input end of the first amplifier is connected with the first resistor and the third resistor respectively; the second input end of the first amplifier is respectively connected with the second resistor and the first diode; the output port of the first amplifier is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube; the second resistor is connected with the source electrode of the first MOS tube and the first diode respectively; the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube, the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube; the first diode is respectively connected with the second diode, the source electrode of the fourth MOS tube, the fifth resistor and the source electrode of the seventh MOS tube; the second diode is connected with the first resistor; the third resistor is respectively connected with the source electrode of the second MOS tube and the first input end of the second amplifier; the source electrode of the second MOS tube is connected with the first input end of the second amplifier; the drain electrode of the fourth MOS tube is respectively connected with the source electrode of the third MOS tube and the grid electrode of the fourth MOS tube; the second input end of the second amplifier is connected with the fourth resistor and the fifth resistor respectively; the output end of the second amplifier is connected with the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube respectively; and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube.
Further, the NMOS detection circuit includes:
the device comprises a first voltage input end, a second voltage input end, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixth resistor, a seventh resistor, an eighth resistor, an NMOS detection voltage output end and an NMOS reference voltage output end;
the first voltage input end and the second voltage input end are respectively connected with the band gap reference source circuit; the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the ninth MOS tube, the drain electrode of the tenth MOS tube, the drain electrode of the eleventh MOS tube, the drain electrode of the fourteenth MOS tube and the drain electrode of the fifteenth MOS tube; the source electrode of the eighth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the thirteenth MOS tube respectively; the source electrode of the ninth MOS tube is connected with the drain electrode of the twelfth MOS tube and the grid electrode of the eleventh MOS tube respectively; the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube and the grid electrode of the eleventh MOS tube respectively; the source electrode of the twelfth MOS tube is respectively connected with the source electrode of the thirteenth MOS tube, the sixth resistor, the seventh resistor and the eighth resistor; the grid electrode of the thirteenth MOS tube is respectively connected with the source electrode of the tenth MOS tube and the sixth resistor; the grid electrode of the tenth MOS tube is connected with the grid electrode of the ninth MOS tube; the source electrode of the tenth MOS tube is connected with the sixth resistor; the source electrode of the eleventh MOS tube is respectively connected with the source electrode of the fourteenth MOS tube and the seventh resistor; the source electrode of the fourteenth MOS tube is connected with the NMOS detection voltage output end; and the source electrode of the fifteenth MOS tube is connected with the NMOS reference voltage output end.
Further, the PMOS detection circuit includes:
a third voltage input end, a fourth voltage input end, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twenty-eighth MOS tube, a twenty-eleventh MOS tube, a twenty-second MOS tube, a twenty-thirteenth MOS tube, a ninth resistor, a tenth resistor, an eleventh resistor, a PMOS detection voltage output end and a PMOS reference voltage output end;
the third voltage input end and the fourth voltage input end are connected with the band gap reference source circuit; the source electrode of the sixteenth MOS tube is respectively connected with the source electrode of the seventeenth MOS tube, the source electrode of the eighteenth MOS tube, the source electrode of the nineteenth MOS tube, the source electrode of the twenty-second MOS tube and the source electrode of the twenty-third MOS tube; the drain electrode of the sixteenth MOS tube is connected with the grid electrode of the twentieth MOS tube and the source electrode of the twenty-first MOS tube respectively; the grid electrode of the seventeenth MOS tube is connected with the grid electrode of the eighteenth MOS tube and the grid electrode of the nineteenth MOS tube respectively; the drain electrode of the seventeenth MOS tube is connected with the grid electrode of the nineteenth MOS tube and the source electrode of the twentieth MOS tube respectively; the drain electrode of the twenty-first MOS tube is connected with the drain electrode of the twenty-first MOS tube, the ninth resistor, the tenth resistor and the eleventh resistor respectively; the grid electrode of the twenty-first MOS tube is connected with the drain electrodes of the ninth resistor and the eighteenth MOS tube respectively; the drain electrode of the nineteenth MOS tube is respectively connected with the tenth resistor, the drain electrode of the twenty-second MOS tube and the PMOS detection voltage output end; and the drain electrode of the twenty-third MOS tube is respectively connected with the eleventh resistor and the PMOS reference voltage output end.
Drawings
FIG. 1 is a schematic flow chart of a process detection method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a process inspection system according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a detection voltage generation module of a process detection system according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a reference voltage generating module of a process detection system according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a differential quantization module of a process detection system according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a process detection result output module of a process detection system according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a process detection circuit according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a bandgap reference source of a process detection circuit according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an NMOS process detection circuit of a process detection circuit according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a PMOS process detection circuit according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
Referring to fig. 1, fig. 1 is a schematic flow chart of a process detection method according to an embodiment of the invention. As shown in fig. 1, the present invention proposes a process detection method, which includes steps 101 to 104, each of which specifically includes:
step 101, performing process detection on the first sample to obtain a process detection voltage.
As an example of this embodiment, a factory process parameter of a first sample is collected
Wherein K is G Negative, can be expressed as:
wherein θ T For the substrate injection coefficient, V OFF Is a fixed value in the BSIM3V3 model, V TH The threshold voltage of the MOS tube is different V at different process angles TH 。
Carrying out current mirror image processing on the factory technological parameters to obtain positive temperature coefficient current IPTAT and negative temperature coefficient current I CTAT Wherein:
where k is the Boltzmann constant and T is the absolute temperature.
Performing temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain zero temperature coefficient current;
converting the zero temperature coefficient current into the process detection voltage
V PROC_MOS ＝R x ·(I CTAT +I PTAT )
And 102, carrying out reference voltage generation processing on the first sample to obtain a process reference voltage.
As an example of the embodiment, the model of TN and TP angles set by the factory is simulated to obtain temperature coefficient compensation current I 2 Obtaining a base reference voltage V according to the voltage relation in the factory technological parameters of the first sample BG Wherein, the method comprises the steps of, wherein,
wherein V is BE2 Is the transistor base-emitter voltage difference.
The reference voltage V BG Conversion to a reference current I 5 Performing reference eliminating mirror image processing to obtain process reference voltage V REF_MOS Wherein, the method comprises the steps of, wherein,
wherein X is the ratio of the channel width W to the channel length L of the MOS transistor.
And 103, respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code.
As an example of this embodiment of the present invention,
detecting the voltage V for the process PROC_MOS And the process reference voltage V REF_MOS Respectively performing differential operation to obtain a digital code of the detected differential voltage and a digital code of the reference differential voltage;
and carrying out digital-to-analog quantization calculation according to the detected differential voltage digital CODE and the reference differential voltage digital CODE to obtain the PROCESS CODE PROCESS_CODE_MOS < M:0>, wherein the PROCESS CODE consists of a judgment flag bit and a basic digital CODE. The value of Z is reasonably selected such that vproc_mos=vref_mos of a typical process angle TN. At this time, vproc_mos-vref_mos is smaller than 0 at the fast angle FN and larger than 0 at the slow angle SN. And (3) quantizing the two analog voltage differential inputs ADC to obtain a corresponding digital CODE after voltage subtraction, namely a PROCESS CODE PROCESS_CODE_MOS < M:0> of MOS. The digital code is an offset binary, with the highest bits representing the symbols.
And 104, determining the process angle deviation degree of the first sample according to the sample process code to obtain a process detection result.
As an example of this embodiment, when it is determined that the judgment flag bit of the process code is positive and the first sample is NMOS process detection, determining that the process angle of the first sample is a slow angle SN;
when the judgment flag bit of the process code is determined to be negative and the first sample is NMOS process detection, determining that the process angle of the first sample deviates from a fast angle FN;
When the judgment flag bit of the process code is positive and the first sample is PMOS process detection, determining that the process angle of the first sample deviates from a fast angle FN;
and when the judgment flag bit of the process code is determined to be negative and the first sample is PMOS process detection, determining that the process angle of the first sample deviates from the slow angle SN.
When the value of the basic digital code is larger, the process angle of the first sample is determined to deviate more, namely, the digital code of the post M-1 bit is larger, which means that the deviation from the typical process angle is more, the deviation degree can be expressed by X (R 9 /R 8 ) Setting;
and obtaining a process detection result of the first sample according to the deviation angle judgment result of the judgment marker bit and the deviation degree judgment result of the basic digital code.
According to the process detection method provided by the embodiment of the invention, the process code is obtained by designing the detection circuit to obtain the full static voltage and quantizing, the finally obtained multi-byte quantizing result can accurately represent the deviation degree of the process instead of the simple 3 results, and the influence caused by the process deviation is accurately compensated.
Example 2
Referring to fig. 2, fig. 2 is a schematic structural diagram of a process detection system according to an embodiment of the invention.
As shown in fig. 2, the present invention proposes a process detection system, comprising:
a detection voltage generation module 201, a reference voltage generation module 202, a differential quantization module 203 and a process detection result output module 204;
the detection voltage generation module 201 is configured to perform process detection on the first sample to obtain a process detection voltage;
as an example of the present embodiment, referring to fig. 3, fig. 3 is a schematic structural diagram of a detection voltage generating module of a process detection system according to an embodiment of the present invention. As shown in fig. 3, the detection voltage generation module 201 includes: a data acquisition unit 301, a temperature coefficient elimination unit 302, and a detection voltage output unit 303;
the data collection unit 301 is configured to collect a factory process parameter of a first sample, and obtain a positive temperature coefficient current I according to a voltage relationship in the factory process parameter of the first sample PTAT And negative temperature coefficient current I CTAT Wherein, the principle that PN junction voltage differences with different junction areas are in direct proportion to temperature is utilized by a base reference voltage generating circuit to obtain positive temperature coefficient current I which is irrelevant to technological parameters PTAT A baseline reference voltage independent of process parameters; v of MOS tube under different technological parameters by technological detection circuit TH Different, obtain the negative temperature coefficient current I which varies with the technological parameters CTAT ；
The temperature coefficient eliminating unit 302 is configured to perform temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain a zero temperature coefficient current;
the detection voltage output unit 303 is configured to convert the zero temperature coefficient current into the process detection voltage V PROC_MOS 。
The reference voltage generating module 202 is configured to perform a reference voltage generating process on the first sample to obtain a process reference voltage;
as an example of the present embodiment, referring to fig. 4, fig. 4 is a schematic structural diagram of a reference voltage generating module of a process detection system according to an embodiment of the present invention. As shown in fig. 4, the reference voltage generating module 202 includes: a base reference voltage generation unit 401 and a process reference voltage generation unit 402;
the reference voltage generating unit 401 is configured to obtain a reference voltage V according to a voltage relationship in the factory process parameters of the first sample BG ；
The process reference voltage generation unit 402 is configured to generate the baseline reference voltage V BG Conversion to a reference current I 5 Performing reference eliminating mirror image processing to obtain process reference voltage V REF_MOS ；
The differential quantization module 203 is configured to perform differential quantization on the process detection voltage and the process reference voltage, respectively, to obtain a sample process code;
as an example of the present embodiment, referring to fig. 5, fig. 5 is a schematic structural diagram of a differential quantization module of a process detection system according to an embodiment of the present invention. As shown in fig. 5, the differential quantization module 203 includes: a difference operation unit 501 and a digital quantization unit 502;
the differential operation unit 501 is configured to detect a voltage V for the process PROC_MOS And the process reference voltage V REF_MOS Respectively performing differential operation to obtain a digital code of the detected differential voltage and a digital code of the reference differential voltage;
the digital quantization unit 502 is configured to perform digital-to-analog quantization calculation according to the detected quantized voltage digital CODE and the reference quantized voltage digital CODE, so as to obtain the PROCESS CODE process_code_mos < M:0>, where the PROCESS CODE is composed of a judgment flag bit and a basic digital CODE.
The process detection result output module 204 is configured to determine a degree of deviation of the process angle of the first sample according to the sample process code, so as to obtain a process detection result.
As an example of the present embodiment, referring to fig. 6, fig. 6 is a schematic structural diagram of a process detection result output module of a process detection system according to an embodiment of the present invention. As shown in fig. 6, the process detection result output module 204 includes: a deviation angle discrimination unit 601, a deviation degree discrimination unit 602, and a process detection result output unit 603;
the deviation angle judging unit 601 is configured to determine a deviation fast angle or a deviation slow angle of the first sample according to the positive and negative of the judgment flag bit of the process code and the process detection type of the first sample;
when the judgment flag bit of the process code is positive and the first sample is NMOS process detection, determining the process angle deviation slow angle SN of the first sample;
when the judgment flag bit of the process code is determined to be negative and the first sample is NMOS process detection, determining that the process angle of the first sample deviates from a fast angle FN;
when the judgment flag bit of the process code is positive and the first sample is PMOS process detection, determining that the process angle of the first sample deviates from a fast angle FN;
and when the judgment flag bit of the process code is determined to be negative and the first sample is PMOS process detection, determining that the process angle of the first sample deviates from the slow angle SN.
The deviation degree judging unit 602 is configured to determine that the process angle of the first sample deviates more when the value of the basic digital code is determined to be larger;
the process detection result output unit 603 is configured to obtain a process detection result of the first sample according to the deviation angle determination result of the determination flag bit and the deviation degree determination result of the basic digital code.
According to the process detection system provided by the embodiment of the invention, the detection of the process deviation is realized through the connection of the modules, the circuit module adopts a simple circuit structure, the loss caused by detection is reduced, the process code is obtained in a mode of obtaining the full static voltage through the detection circuit and quantifying the full static voltage, the deviation result is obtained through the differential result of the process code, the circuit design is not influenced by strict constraint conditions, the process detection can be realized through the circuit, the detection result is often only related to a single variable, the influence of external conditions is avoided, and the accuracy of the detection result is improved.
Example 3
Referring to fig. 7, fig. 7 is a schematic structural diagram of a process detection circuit according to an embodiment of the invention.
As shown in fig. 7, the present invention provides a process detection circuit, comprising:
The device comprises a process detection circuit, a band gap reference source circuit and an analog-to-digital converter;
the process detection circuit is respectively connected with the band gap reference source circuit and the analog-to-digital converter;
the process detection circuit is used for generating a detection voltage and a corresponding reference voltage;
the band gap reference source circuit is used for generating bias voltage;
as an example of the present embodiment, referring to fig. 8, fig. 8 is a schematic diagram of a bandgap reference source of a process detection circuit according to an embodiment of the present invention. As shown in fig. 8, the present invention proposes a bandgap reference source circuit of a process detection circuit, comprising: first amplifier OP 1 Second amplifier OP 2 First diode Q 1 Second diode Q 2 First MOS tube M 1 Second MOS tube M 2 Third MOS tube M 3 Fourth MOS tube M 4 Fifth MOS tube M 5 Sixth MOS transistor M 6 Seventh MOS tube M 7 A first resistor R 1 A second resistor R 2 Third resistor R 3 Fourth resistor R 4 And a fifth resistor R 5 The method comprises the steps of carrying out a first treatment on the surface of the The first amplifier OP 1 Respectively with the first resistor R 1 And the third resistor R 3 Connecting; the first amplifier OP 1 Respectively with the second resistor R 2 And the first diode Q 1 Connecting; the first amplifier OP 1 Respectively with the output port of the first MOS tube M 1 Gate electrode of the second MOS transistor M 2 Gate electrode of (d) and the third MOS transistor M 3 Is connected with the grid electrode; the second resistor R 2 Respectively at the first MOS tube M 1 And the first diode Q 1 Connecting; the first MOS tube M 1 The drain electrode of the transistor is respectively connected with the second MOS tube M 2 Drain electrode of the third MOS transistor M 3 Drain electrode of the fifth MOS transistor M 5 Drain electrode of (d) and the sixth MOS transistor M 6 Is connected with the drain electrode of the transistor; the first diode Q 1 Respectively with the second diode Q 2 The fourth MOS tube M 4 Source of said fifth resistor R 5 And the seventh MOS tube M 7 Is connected with the source electrode of the transistor; the second diode Q 2 With the first resistor R 1 Connecting; the third resistor R 3 Respectively with the second MOS tube M 2 Is connected to the source of the second amplifier OP 2 Is connected with the first input end of the first power supply; the second MOS tube M 2 Is connected to the source of the second amplifier OP 2 Is connected with the first input end of the first power supply; the fourth MOS tube M 4 The drain electrode of the transistor is respectively connected with the third MOS transistor M a Source electrode of (C) and the fourth MOS transistor M 4 Is connected with the grid electrode; the second amplifier OP 2 Respectively with the second input end of the fourth resistor R 4 And the fifth resistor R 5 Connecting; the second amplifier OP 2 The output end of the fifth MOS tube M is respectively connected with 5 Gate electrode of (d) and the sixth MOS transistor M 6 Is connected with the grid electrode; the seventh MOS tube M 7 The drain electrode of the transistor is respectively connected with the sixth MOS transistor M 6 Source electrode of (c) and the seventh MOS transistor M 7 Is connected to the gate of the transistor.
The band gap reference source circuit comprises 2 parts, I PTAT And V BG Generating circuit, I REF A circuit is generated. Wherein I is PTAT And V BG Generating circuit mainly has basic band-gap reference source structure, Q 1 、Q 2 BJT, Q matched for two diode connection forms 2 Area of Q 1 N times of (2). By utilizing the principle that PN junction voltage differences with different junction areas are proportional to temperature under the condition of the same current, the PN junction voltage differences are formed on the resistor R 1 A current proportional to temperature (PTAT) is formed and flows through R 1 、R 3 Generated voltage and Q 2 Is a base emitter voltage difference V BE2 On the other hand, a voltage V independent of the temperature coefficient is obtained BG 。M 1 And M 2 Equal in size, R 2 And R is 3 Resistance values are equal to make M 1 And M 2 Is kept consistent with the drain voltage of M 1 And M 2 The two paths of current are consistent.
Wherein the transistor base-emitter voltage difference is:
where k is the Boltzmann constant and T is the absolute temperature. M is M 1 And M is as follows 2 The proportion is the same, OP 1 The input voltages are equal, so:
I 2 R 1 +V BE2 ＝V BE1
thus:
PTAT current I 2 Flow through R 1 、R 3 The voltage generated due to the voltage drop V of the transistor BE Is a negative temperature coefficient, by properly setting the parameter R 1 And R is 3 Can obtain a reference voltage V which does not change with temperature BG ：
I REF Generating circuit through OP 2 Negative feedback of (C), V BG And R is 5 The upper voltage is short, thus, flows through R 5 The current of (2) is:
due to V described above BG Has been set by parameters to a reference voltage which does not vary with temperature, I 5 That is, a current that is dependent only on the temperature coefficient of resistance can be obtained by multiplying the same type of resistance by the current flowing through the resistorAnd eliminating the temperature coefficient of resistance to obtain a new reference voltage.
M 6 And M is as follows 5 W/L ratio of X, I 5 The mirror image is obtained:
the analog-to-digital converter is used for generating a digital code;
wherein the process detection circuit further comprises: an NMOS detection circuit and a PMOS detection circuit.
As an example of the present embodiment, referring to fig. 9, fig. 9 is a schematic diagram of an NMOS process detection circuit of a process detection circuit according to an embodiment of the present invention. As shown in fig. 9, an NMOS process detection circuit of the process detection circuit according to the present invention includes: a first voltage input end, a second voltage input end and an eighth MOS tube M 8 Ninth MOS transistor M 9 Tenth MOS transistor M 10 Eleventh MOS tube M 11 Twelfth MOS transistor M 12 Thirteenth MOS tube M 13 Fourteenth MOS tube M 14 Fifteenth MOS tube M 15 Sixth resistor R 6 Seventh resistor R 7 Eighth resistor R 8 The NMOS detection voltage output end and the NMOS reference voltage output end; the first voltage input end and the second voltage input end are respectively connected with the band gap reference source circuit; the eighth MOS tube M 8 The drains of the MOS transistors are respectively connected with the ninth MOS transistor M 9 Drain electrode of (C), tenth MOS transistor M 10 Drain electrode of (d), eleventh MOS transistor M 11 Drain electrode of (d), fourteenth MOS transistor M 14 Drain electrode of (d) and fifteenth MOS transistor M 15 A drain electrode of (2); the eighth MOS tube M 8 The source electrode of (C) is respectively connected with the twelfth MOS transistor M 12 Gate of (c) and the thirteenth MOS transistor M 13 Is connected with the drain electrode of the transistor; the ninth MOS tube M 9 The source electrode of (C) is respectively connected with the twelfth MOS transistor M 12 Drain electrode of (c) and the eleventh MOS transistor M 11 Is connected with the grid electrode; the ninth MOS tube M 9 The grid electrode of the transistor is respectively connected with the tenth MOS tube M 10 Gate of (c) and the eleventh MOS transistor M 11 Is connected with the grid electrode; the twelfth MOS transistor M 12 The source electrode of the transistor is respectively connected with the thirteenth MOS transistor M 13 Source of said sixth resistor R 6 The seventh resistor R 7 And the eighth resistor R 8 Connecting; the thirteenth MOS tube M 13 The grid electrode of the transistor is respectively connected with the tenth MOS tube M 10 Source of (d) and said sixth resistor R 6 Connecting; the tenth MOS transistor M 10 Gate of (d) and the ninth MOS transistor M 9 Is connected with the grid electrode; the tenth MOS transistor M 10 Source of (d) and said sixth resistor R 6 Connecting; the eleventh MOS tube M 11 The source electrode of (C) is respectively connected with the fourteenth MOS tube M 14 Source of (c) and said seventh resistor R 7 Connecting; the fourteenth MOS tube M 14 The source electrode of the NMOS detection voltage output end is connected with the source electrode of the NMOS detection voltage output end; the fifteenth MOS tube M 15 Is connected to the NMOS reference voltage output terminal.
Wherein M is 8 、M 9 、M 10 、M 12 、M 13 And R is 6 A process detection voltage generating circuit for forming a negative temperature coefficient; m is M 11 、M 14 And R is 7 Composition process detection voltage V PROC_NMOS A generating circuit; m is M 15 And R is 8 Composition process detection voltage V REF_NMOS A circuit is generated. V (V) P1 And V P2 Corresponding nodes in the band gap reference source circuit are respectively provided with a current mirror bias for the process detection circuit to generate corresponding I REF And I PTAT 。
M 9 、M 10 、M 12 And M 13 Loop stability V GSN Voltage, M 8 Providing a smaller quiescent current guarantee M 13 Working in a subthreshold region according to V of the MOS tube in the subthreshold region GS The formula is as follows:
wherein K is G Negative, can be expressed as:
wherein θ T For the substrate injection coefficient, V OFF Is a fixed value in the BSIM3V3 model, V TH The threshold voltage of the MOS tube is different V at different process angles TH Wherein at fast angle FN, V TH Smaller, slow angle SN, V TH Larger. Thus, a negative temperature coefficient voltage parallel at different process angles can be obtained.
V GSN At the resistance R 6 Generating CTAT current with negative temperature coefficient and mirroring to obtain I CTAT If M 10 And M 11 The W/L ratio of (2) is X, and can be obtained by:
M 14 mirroring positive temperature coefficient PTAT current from bandgap reference source circuit if it is M in bandgap reference source circuit 2 The W/L ratio of (2) is Y, and can be obtained:
will I CTAT And I PTAT Additive flow-through resistor R 7 Zero temperature coefficient voltage can be obtained:
wherein the second term is negative temperature coefficient, the third term is positive temperature coefficient, and X, Y, R is reasonably selected 1 、R 6 、R 7 The second and third terms can be added to yield a zero temperature coefficient and thus a temperature independent voltage, but process corner dependent voltage, as shown in the small graph of fig. 9.
M 15 Mirror reference current from bandgap reference source circuit and flow through resistor R 7 If and M in band gap reference source circuit 5 The W/L ratio of (2) is Z, and can be obtained by:
as another example of the present embodiment, referring to fig. 10, fig. 10 is a schematic diagram of a PMOS process detection circuit of the process detection circuit according to an embodiment of the present invention. As shown in fig. 10, a PMOS process detection circuit of the present invention includes: a third voltage input end, a fourth voltage input end and a sixteenth MOS tube M 16 Seventeenth MOS tube M 17 Eighteenth MOS tube M 18 Nineteenth MOS pipe M 19 Twentieth MOS transistor M 20 Twenty-first MOS transistor M 21 Twenty-second MOS transistor M 22 Twenty-third MOS transistor M 23 Ninth resistor R 9 Tenth resistor R 10 Eleventh resistor R 11 The PMOS detection voltage output end and the PMOS reference voltage output end;
the third voltage input end and the fourth voltage input end are connected with the band gap reference source circuit; the sixteenth MOS tube M 16 The source electrode of the (B) is respectively connected with the seventeenth MOS tube M 17 Source electrode of (eighteenth) MOS transistor M 18 Source electrode of (E) and nineteenth MOS transistor M 19 Source electrode of (E) and twenty-second MOS transistor M 22 Source electrode of (C) and twenty-third MOS transistor M 23 Is connected with the source electrode of the transistor; the sixteenth MOS tube M 16 The drain electrode of the transistor is respectively connected with the twenty-second MOS transistor M 20 Gate electrode of (c) and the twenty-first MOS transistor M 21 Is connected with the source electrode of the transistor; the seventeenth MOS tube M 17 The grid electrode of the gate electrode is respectively connected with the eighteenth MOS tube M 18 Gate of (c) and the nineteenth MOS transistor M 19 Is connected with the grid electrode; the seventeenth MOS tube M 17 The drain electrode of the transistor is respectively connected with the nineteenth MOS transistor M 19 Gate of (c) and the twentieth MOS transistor M 20 Is connected with the source electrode of the transistor; the twentieth MOS tube M 20 The drain electrodes of the second MOS tube M are respectively arranged on the second eleventh MOS tube 21 The drain electrode of the ninth resistor R 9 The tenth resistor R 10 And institute(s)The eleventh resistor R 11 Connecting; the twenty-first MOS tube M 21 The grid electrode of the resistor is respectively connected with the ninth resistor R 9 And the eighteenth MOS tube M 18 Is connected with the drain electrode of the transistor; the nineteenth MOS tube M 19 Drain electrodes of (a) are respectively connected with the tenth resistor R 10 The twenty-second MOS tube M 22 The drain electrode of the PMOS detection voltage is connected with the output end of the PMOS detection voltage; the twenty-third MOS tube M 23 Drain electrodes of (a) are respectively connected with the eleventh resistor R 11 And the PMOS reference voltage output end is connected.
Wherein M is 16 、M 17 、M 18 、M 20 、M 21 And R is 9 A process detection voltage generating circuit for forming a negative temperature coefficient; m is M 19 、M 22 And R is 10 Composition process detection voltage V PROC_PMOS A generating circuit; m is M 23 And R is 11 Composition process detection voltage V REF_PMOS A circuit is generated. V (V) N1 And V N2 Corresponding nodes in the band gap reference source circuit are respectively provided with a current mirror bias for the process detection circuit to generate corresponding I REF And I PTAT 。
In contrast, M in the PMOS detection circuit operates in the subthreshold region 21 The source is connected with the power supply VDD, so that the grid voltage is VDD-V GSP 。
Wherein K is G Is negative, so the second term of the formula is a negative temperature coefficient. The voltages with negative temperature coefficients at different process angles in parallel, as shown in the small graph of FIG. 10, are VDD-V at fast angle FP GSP Higher, slow angle SP voltage VDD-V GSP Lower.
In the same way, can obtain
Will I CTAT And I PTAT Additive flow-through resistor R 10 And then is connected with a power supply VDD to obtain zero temperature coefficient voltage:
If the reference voltage also uses the current mirror image I REF Through the resistor to ground, the VDD term is retained after subtraction, thus the resistor R 11 Connected with a power supply, the method can obtain:
thus V PROC_PMOS -V REF_PMOS The VDD term may be eliminated. The value of Z is reasonably selected, so that the V of a typical process angle can be PROC_PMOS ＝V REF_PMOS . At this time, V PROC_PMOs -V REF_PMOS Greater than 0 at fast angle FP and less than 0 at slow angle SP. The two analog voltages are input into ADC in differential mode to be quantized, and the corresponding digital CODEs after voltage subtraction are obtained, namely the PROCESS CODE PROCESS_CODE_PMOS of PMOS<M：0>. The digital code is an offset binary, with the highest bits representing the symbols.
The process detection circuit provided by the embodiment of the invention has the characteristics of simple circuit structure, small occupied chip area, low power consumption and capability of being turned off after detection is finished, and can repeatedly call the process angles for respectively detecting different parts of the chip, thereby relieving strict constraint conditions in the design process of other circuits of the chip, optimizing the chip power consumption under the condition of different process angles, ensuring that the process detection result is not influenced by too many interference factors, and further improving the accuracy.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present invention, and such modifications and variations should also be regarded as being within the scope of the invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
Claims (14)
1. A process inspection method, comprising:
Performing process detection on the first sample to obtain a process detection voltage;
performing reference voltage generation processing on the first sample to obtain a process reference voltage;
respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code;
and determining the process angle deviation degree of the first sample according to the sample process code to obtain a process detection result.
2. The process detection method according to claim 1, wherein the process detection is performed on the first sample to obtain a process detection voltage, specifically:
collecting factory process parameters of the first sample;
obtaining positive temperature coefficient current and negative temperature coefficient current through the voltage relation in the factory technological parameters of the first sample;
performing temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain zero temperature coefficient current;
converting the zero temperature coefficient current into the process detection voltage.
3. The process detection method according to claim 2, wherein the reference voltage generating process is performed on the first sample to obtain a process reference voltage, which specifically includes:
Obtaining a base reference voltage according to the voltage relation in the factory technological parameters of the first sample;
and converting the reference voltage into a reference current, and performing reference elimination mirror image processing to obtain a process reference voltage.
4. A process detection method according to claim 3, wherein said process detection voltage and said process reference voltage are respectively differentially quantized to obtain sample process codes, specifically:
respectively carrying out differential operation on the process detection voltage and the process reference voltage to obtain a digital code of the detection differential voltage and a digital code of the reference differential voltage;
and carrying out digital-analog quantization calculation according to the detected differential voltage digital code and the reference differential voltage digital code to obtain the process code, wherein the process code consists of a judgment flag bit and a basic digital code.
5. The process detection method according to claim 4, wherein determining the degree of deviation of the process angle of the first sample according to the sample process code, and obtaining the process detection result, specifically comprises:
determining the process angle deviation fast angle or slow angle of the first sample according to the positive and negative of the judging zone bit of the process code and the process detection type of the first sample;
When the numerical value of the basic digital code is determined to be larger, determining that the process angle deviation degree of the first sample is larger;
and obtaining a process detection result of the first sample according to the deviation angle judgment result of the judgment marker bit and the deviation degree judgment result of the basic digital code.
6. A process inspection system, comprising:
the device comprises a detection voltage generation module, a reference voltage generation module, a differential quantization module and a process detection result output module;
the detection voltage generation module is used for carrying out process detection on the first sample to obtain a process detection voltage;
the reference voltage generation module is used for carrying out reference voltage generation processing on the first sample to obtain a process reference voltage;
the differential quantization module is used for respectively carrying out differential quantization on the process detection voltage and the process reference voltage to obtain a sample process code;
and the process detection result output module is used for determining the process angle deviation degree of the first sample according to the sample process code to obtain a process detection result.
7. The process sensing system of claim 6, wherein the sensing voltage generation module is configured to perform a process sensing on the sample to obtain a process sensing voltage, further comprising:
The device comprises a data acquisition unit, a temperature coefficient elimination unit and a detection voltage output unit;
the data acquisition unit is used for acquiring the factory technological parameters of the first sample, and obtaining positive temperature coefficient current and negative temperature coefficient current through the voltage relation in the factory technological parameters of the first sample;
the temperature coefficient eliminating unit is used for carrying out temperature coefficient setting on the positive temperature coefficient current and the negative temperature coefficient current to obtain zero temperature coefficient current;
the detection voltage output unit is used for converting the zero temperature coefficient current into the process detection voltage.
8. The process sensing system of claim 7, wherein the reference voltage generation module is configured to perform a reference voltage generation process on the first sample to obtain a process reference voltage, and further comprising:
a base reference voltage generation unit and a process reference voltage generation unit;
the reference voltage generating unit is used for obtaining a reference voltage according to the voltage relation in the factory process parameters of the first sample;
the process reference voltage generating unit is used for converting the base reference voltage into base reference current and performing reference elimination mirror image processing to obtain the process reference voltage.
9. The process sensing system of claim 8, wherein the differential quantization module is configured to differentially quantize the process sensing voltage and the process reference voltage, respectively, to obtain sample process codes, comprising:
a differential operation unit and a digital quantization unit;
the differential operation unit is used for respectively carrying out differential operation on the process detection voltage and the process reference voltage to obtain a digital code of the detection differential voltage and a digital code of the reference differential voltage;
the digital quantization unit is used for carrying out digital-to-analog quantization calculation according to the detected differential voltage digital code and the reference differential voltage digital code to obtain the process code, wherein the process code consists of a judgment flag bit and a basic digital code.
10. The process detection system according to claim 9, wherein the process detection result output module is configured to determine a degree of deviation of a process angle of the first sample according to the sample process code, to obtain a process detection result, and specifically comprises:
the deviation angle judging unit, the deviation degree judging unit and the process detection result output unit;
the deflection angle judging unit is used for determining a deflection fast angle or a deflection slow angle of the first sample according to the positive and negative of the judging zone bit of the process code and the process detection type of the first sample;
The deviation degree judging unit is used for determining that the process angle deviation degree of the first sample is larger as the numerical value of the basic digital code is larger;
and the process detection result output unit is used for obtaining the process detection result of the first sample according to the deviation angle judgment result of the judgment marker bit and the deviation degree judgment result of the basic digital code.
11. A process sensing circuit operable to perform a process sensing method as claimed in any one of claims 1 to 5, comprising:
the device comprises a process detection circuit, a band gap reference source circuit and an analog-to-digital converter;
the process detection circuit is respectively connected with the band gap reference source circuit and the analog-to-digital converter;
the process detection circuit is used for generating a detection voltage and a corresponding reference voltage;
the band gap reference source circuit is used for generating bias voltage;
the analog-to-digital converter is used for generating a digital code;
wherein the process detection circuit further comprises: an NMOS detection circuit and a PMOS detection circuit.
12. The process sensing circuit of claim 11, wherein the bandgap reference source circuit comprises:
the first amplifier, the second amplifier, the first diode, the second diode, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the first resistor, the second resistor, the third resistor, the fourth resistor and the fifth resistor;
The first input end of the first amplifier is connected with the first resistor and the third resistor respectively; the second input end of the first amplifier is respectively connected with the second resistor and the first diode; the output port of the first amplifier is respectively connected with the grid electrode of the first MOS tube, the grid electrode of the second MOS tube and the grid electrode of the third MOS tube; the second resistor is connected with the source electrode of the first MOS tube and the first diode respectively; the drain electrode of the first MOS tube is respectively connected with the drain electrode of the second MOS tube, the drain electrode of the third MOS tube, the drain electrode of the fifth MOS tube and the drain electrode of the sixth MOS tube; the first diode is respectively connected with the second diode, the source electrode of the fourth MOS tube, the fifth resistor and the source electrode of the seventh MOS tube; the second diode is connected with the first resistor; the third resistor is respectively connected with the source electrode of the second MOS tube and the first input end of the second amplifier; the source electrode of the second MOS tube is connected with the first input end of the second amplifier; the drain electrode of the fourth MOS tube is respectively connected with the source electrode of the third MOS tube and the grid electrode of the fourth MOS tube; the second input end of the second amplifier is connected with the fourth resistor and the fifth resistor respectively; the output end of the second amplifier is connected with the grid electrode of the fifth MOS tube and the grid electrode of the sixth MOS tube respectively; and the drain electrode of the seventh MOS tube is respectively connected with the source electrode of the sixth MOS tube and the grid electrode of the seventh MOS tube.
13. The process sensing circuit of claim 12, wherein the NMOS sensing circuit comprises:
the device comprises a first voltage input end, a second voltage input end, an eighth MOS tube, a ninth MOS tube, a tenth MOS tube, an eleventh MOS tube, a twelfth MOS tube, a thirteenth MOS tube, a fourteenth MOS tube, a fifteenth MOS tube, a sixth resistor, a seventh resistor, an eighth resistor, an NMOS detection voltage output end and an NMOS reference voltage output end;
the first voltage input end and the second voltage input end are respectively connected with the band gap reference source circuit; the drain electrode of the eighth MOS tube is respectively connected with the drain electrode of the ninth MOS tube, the drain electrode of the tenth MOS tube, the drain electrode of the eleventh MOS tube, the drain electrode of the fourteenth MOS tube and the drain electrode of the fifteenth MOS tube; the source electrode of the eighth MOS tube is connected with the grid electrode of the twelfth MOS tube and the drain electrode of the thirteenth MOS tube respectively; the source electrode of the ninth MOS tube is connected with the drain electrode of the twelfth MOS tube and the grid electrode of the eleventh MOS tube respectively; the grid electrode of the ninth MOS tube is connected with the grid electrode of the tenth MOS tube and the grid electrode of the eleventh MOS tube respectively; the source electrode of the twelfth MOS tube is respectively connected with the source electrode of the thirteenth MOS tube, the sixth resistor, the seventh resistor and the eighth resistor; the grid electrode of the thirteenth MOS tube is respectively connected with the source electrode of the tenth MOS tube and the sixth resistor; the grid electrode of the tenth MOS tube is connected with the grid electrode of the ninth MOS tube; the source electrode of the tenth MOS tube is connected with the sixth resistor; the source electrode of the eleventh MOS tube is respectively connected with the source electrode of the fourteenth MOS tube and the seventh resistor; the source electrode of the fourteenth MOS tube is connected with the NMOS detection voltage output end; and the source electrode of the fifteenth MOS tube is connected with the NMOS reference voltage output end.
14. The process sensing circuit of claim 12, wherein the PMOS sensing circuit comprises:
a third voltage input end, a fourth voltage input end, a sixteenth MOS tube, a seventeenth MOS tube, an eighteenth MOS tube, a nineteenth MOS tube, a twenty-eighth MOS tube, a twenty-eleventh MOS tube, a twenty-second MOS tube, a twenty-thirteenth MOS tube, a ninth resistor, a tenth resistor, an eleventh resistor, a PMOS detection voltage output end and a PMOS reference voltage output end;
the third voltage input end and the fourth voltage input end are connected with the band gap reference source circuit; the source electrode of the sixteenth MOS tube is respectively connected with the source electrode of the seventeenth MOS tube, the source electrode of the eighteenth MOS tube, the source electrode of the nineteenth MOS tube, the source electrode of the twenty-second MOS tube and the source electrode of the twenty-third MOS tube; the drain electrode of the sixteenth MOS tube is connected with the grid electrode of the twentieth MOS tube and the source electrode of the twenty-first MOS tube respectively; the grid electrode of the seventeenth MOS tube is connected with the grid electrode of the eighteenth MOS tube and the grid electrode of the nineteenth MOS tube respectively; the drain electrode of the seventeenth MOS tube is connected with the grid electrode of the nineteenth MOS tube and the source electrode of the twentieth MOS tube respectively; the drain electrode of the twenty-first MOS tube is connected with the drain electrode of the twenty-first MOS tube, the ninth resistor, the tenth resistor and the eleventh resistor respectively; the grid electrode of the twenty-first MOS tube is connected with the drain electrodes of the ninth resistor and the eighteenth MOS tube respectively; the drain electrode of the nineteenth MOS tube is respectively connected with the tenth resistor, the drain electrode of the twenty-second MOS tube and the PMOS detection voltage output end; and the drain electrode of the twenty-third MOS tube is respectively connected with the eleventh resistor and the PMOS reference voltage output end.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311612691.6A CN117650072A (en) | 2023-11-28 | 2023-11-28 | Process detection method, system and circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311612691.6A CN117650072A (en) | 2023-11-28 | 2023-11-28 | Process detection method, system and circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117650072A true CN117650072A (en) | 2024-03-05 |
Family
ID=90042788
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311612691.6A Pending CN117650072A (en) | 2023-11-28 | 2023-11-28 | Process detection method, system and circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117650072A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109613323A (en) * | 2018-10-30 | 2019-04-12 | 北京时代民芯科技有限公司 | A kind of programmable signal amplitude detection circuit |
| CN114355027A (en) * | 2022-03-17 | 2022-04-15 | 深圳市芯卓微科技有限公司 | Detection circuit and chip |
| CN114637366A (en) * | 2022-05-18 | 2022-06-17 | 成都本原聚能科技有限公司 | Detection circuit and chip independent of process and temperature and application of lumen detection |
| CN116054754A (en) * | 2023-01-18 | 2023-05-02 | 上海迦美信芯通讯技术有限公司 | Current discrete optimizing device for automatic process detection and compensation of LNA |
-
2023
- 2023-11-28 CN CN202311612691.6A patent/CN117650072A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109613323A (en) * | 2018-10-30 | 2019-04-12 | 北京时代民芯科技有限公司 | A kind of programmable signal amplitude detection circuit |
| CN114355027A (en) * | 2022-03-17 | 2022-04-15 | 深圳市芯卓微科技有限公司 | Detection circuit and chip |
| CN114637366A (en) * | 2022-05-18 | 2022-06-17 | 成都本原聚能科技有限公司 | Detection circuit and chip independent of process and temperature and application of lumen detection |
| CN116054754A (en) * | 2023-01-18 | 2023-05-02 | 上海迦美信芯通讯技术有限公司 | Current discrete optimizing device for automatic process detection and compensation of LNA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhu et al. | A 0.45 V, nano-watt 0.033% line sensitivity MOSFET-only sub-threshold voltage reference with no amplifiers | |
| Huang et al. | A sub-200nW all-in-one bandgap voltage and current reference without amplifiers | |
| Bendali et al. | A 1-V CMOS current reference with temperature and process compensation | |
| CN108007594B (en) | Temperature detection circuit and method | |
| Whig et al. | Development of economical ASIC for PCS for water quality monitoring | |
| Michejda et al. | A precision CMOS bandgap reference | |
| Krummenacher et al. | Smart temperature sensor in CMOS technology | |
| Sasaki et al. | A Temperature Sensor With an Inaccuracy of ${-}{\hbox {1}}/{+}{\hbox {0.8}}\^{\circ} $ C Using 90-nm 1-V CMOS for Online Thermal Monitoring of VLSI Circuits | |
| CN105974996B (en) | A kind of reference voltage source | |
| CN104298293B (en) | A kind of bandgap voltage reference with curvature compensation | |
| US9335223B2 (en) | Circuits and methods for determining the temperature of a transistor | |
| CN102486414A (en) | Temperature sensor circuit | |
| Lin et al. | AV/SUB be/(T) model with application to bandgap reference design | |
| CN114623944A (en) | CMOS temperature sensor | |
| CN117650072A (en) | Process detection method, system and circuit | |
| CN113467562A (en) | High-end operational amplifier-free band gap reference source | |
| Li et al. | 1.8 V-0.18-μm CMOS temperature sensor with frequency output | |
| CN112504494B (en) | Ultra-low power consumption CMOS temperature sensing circuit | |
| Aprile et al. | Performance comparison of BJT and MOS devices as temperature sensing elements | |
| CN112345103B (en) | Temperature sensor based on MOS pipe | |
| Shama | MOS only voltage reference with improved line regulation for LDO voltage regulator applications | |
| CN103226371A (en) | Reference voltage source with temperature curvature complementing function | |
| CN117650073A (en) | PVT detection method, PVT detection system and PVT detection circuit | |
| Shi et al. | A wide supply range bandgap voltage reference with curvature compensation | |
| Kölling et al. | Design of a CMOS temperature sensor with current output |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |