JPH10247842A - Mos variable delay circuit and fine delay circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a vernier delay circuit which has simple constitution and high resolution and which is universal to a temperature change by executing rough delay and minute delay, through the use of an RC circuit, switching delay and correcting delay time. SOLUTION: A delay signal is sent from a fine delay circuit 28 to a first rough delay circuit 29. The first rough delay circuit 29 delays the signal given to the circuit by different times. A multiplexer 32 gives one of four decoder outputs to a second rough delay circuit 34 in accordance with a signal from a data bus, which is decoded in a decoder 32a. The second rough delay circuit 34 delays the signal given to the circuit by five different delays. An input signal received in an input port 20 is delayed by the three separated circuits of the first minute delay circuit 28, the first rough delay circuit 29 and the second rough delay circuit 34. The arbitrary number of minute delay circuits and rough delay circuits are used by selection.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS variable delay circuit, and more particularly, to a variable CMOS (Complementary CMOS) having a switchable capacitor for changing a delay.
tal-oxide Semiconductor) relates to a vernier (fine) delay circuit.

[0002]

2. Description of the Related Art CM for low-power and inexpensive integrated circuits
OS circuit design is well known. Many popular integrated circuit products are available for CMOS implementations. Unfortunately, however, achieving low power consumption in CMOS circuits is costly. CMOS integrated circuits are also very sensitive to temperature and electrical fluctuations. Intrinsic delay in CMOS integrated circuits is substantial and varies significantly with temperature and other variations. This makes CMOS timing and delay circuits difficult to design.

[0003] Test systems require precise calibration and correction of adjustment parameters. A programmable delay circuit, also called a programmable (programmable) delay line, is ideal for providing the necessary calibration and correction when customization of the delay adjustment is allowed. After customization, a delay is applied for each test. Or
Each test may have a different delay. As the clock speed for the circuit increases, the test circuit must accurately test at a faster rate. As the clock speed of the tester increases, so must the accuracy of the delay circuit. However, a coarse delay line consisting of inverters, RC circuits and multiplexing circuits cannot achieve the required accuracy. Therefore, higher resolution (Resoutio
n) is required.

[0004] A typical fine delay is achieved using a combination of series and parallel paths of a load connected inverter. The resolution of the delay line is thereby increased.
Unfortunately, however, these circuits are large and vary significantly with changes in temperature.

Another method for achieving high resolution is to use a vernier delay circuit. A typical vernier delay component is Brooktree ™ Bt604. This component is an ECL compatible implementation of a vernier delay circuit with a digital to analog converter (DAC), a latch linear ramp generator, and a comparator. The digital signal in the form of a multi-bit signal to a digital / analog converter is converted to a plurality of analog voltages. The constant current source charges the capacitor, thereby forming a linear ramp response. An output is provided when the capacitor charge exceeds the analog voltage provided by the digital to analog converter. The analog voltage is set by changing the data bits applied to the digital / analog converter. The latch holds data on the output during a delay. If a single current is selected to charge the capacitor, the capacitor will charge linearly, and thus the delay will be accurate. The minimum and maximum delays depend on the voltage range over which the capacitor is stored, however, the linearity of the response allows a considerable degree of flexibility. By using bipolar technology, the circuit is relatively immune to temperature changes, however, the circuit consumes significant power.

Bt 406 is a very good delay adjusting component. Unfortunately, however, it requires an external current reference source for accurate delay. Further, Bt406
Are separate hardware components, which occupy board space and increase design costs. Bt4
06 circuit into a CMOS device,
Significant changes are required to redesign bipolar circuits as CMOS circuits.

[0007] US Patent No. 5,539,095 to Goto et al.
280,195 discloses one timing generator. The timing generator includes a timing vernier. The coarse delay adjustment circuit provides a plurality of separate delay paths for more efficient and desirable delay adjustment. The timing vernier fine delay adjustment circuit used in the implementation by Goto et al. Is not disclosed in detail and is prior art prior to its disclosure.

[0008] Switchable capacitors according to the prior art are known. Some examples of switchable capacitors are described in U.S. Pat. No. 5,332,9 issued to Dingwall et al.
No. 97. Dingwall discloses a capacitor in series with a switching transistor for switching the capacitor “on” or “off”. U.S. Pat. No. 5,495,199 issued to Hirano on Feb. 27, 1996, discloses a similar switching capacitor.

Hewlett Packard Jo, published October 1994 by Goto, Barnes and Owens.
urnal), Vol. 45, No. 5, pp. 51-58, "CMOS Programmable Delay Vernier (CMOS Progr.
Ammable Delay Vernir) discloses a CMOS implementation of a delay vernier. The disclosed implementation relies on a digitally controlled RC circuit according to the prior art. One example of a known digitally controlled RC circuit is a transistor in series with a capacitor, but with a variable RC
A buffer impedance naturally occurs in a CMOS logic circuit for forming a circuit. Digital-to-analog converters are used to provide bias voltages to reduce the effects of temperature, layout, and processing diversity.
Temperature variations can be compensated for by using a bias voltage provided by a digital-to-analog converter, but it is complicated and requires sufficient space on the CMOS integrated circuit.

[0010]

From the above description, it can be seen that CM
It would be beneficial to provide a vernier delay adjustment that is implemented in an OS integrated circuit, has a high resolution in a simple configuration, and is invariant to temperature changes.

In view of the foregoing, it is an object of the present invention to provide a high resolution, substantially temperature invariant CMOS delay in a simple configuration that can solve the above and other problems in the prior art. Is to provide a circuit.

It is a further object of the present invention to provide a CMOS vernier delay for efficient use of CMOS integrated circuit area.

[0013]

In order to achieve the above object, a CMOS variable vernier delay circuit provided by the present invention comprises:
(A) an input terminal, (b) an output terminal, (c) a reference voltage terminal, (d) a resistor connected in series with the input terminal and the output terminal, and (e) a source, a gate, A transistor comprising a drain and a substrate, wherein the source and the drain are electrically connected to at least one of the output terminal and the resistance means, and the substrate is electrically connected to the reference voltage terminal. When,
(F) means for supplying a binary digital signal having at least two voltage levels to the gate for selecting from a plurality of gate / channel capacitances.

The present invention also provides another CMOS variable vernier delay circuit. This CMOS variable vernier delay circuit includes (a) an input terminal, (b) an output terminal, and (c)
A first reference voltage terminal, (d) a second reference voltage terminal, (e) a resistance means connected in series to the input terminal and the output terminal, and (f) a source, a gate, A drain and a substrate, wherein the source and the drain are electrically connected to at least one of the output terminal and the resistance means, and the substrate is connected to the first terminal.
(G) each having a source, a gate, a drain, and a substrate, wherein the source and the drain are the input terminal and the output terminal. And a plurality of p-type transistors electrically connected to one of the resistance means and having the substrate electrically connected to the second reference voltage terminal; and (h) a plurality of gates. Means for supplying a binary digital signal having at least two voltage levels to each of the gates for selecting from the channel capacitance.

The present invention also provides a fine delay circuit for use in a vernier delay circuit. The fine delay circuit includes (a) an input terminal, (b) a first gate connected to the input terminal, a first source connected to the V _DD voltage terminal, and a first drain. An input buffer including at least a first transistor having a first resistor and a vinyl resistor having a first terminal connected to the first drain and a second terminal connected to the first drain;
An output terminal electrically connected to the second terminal of the vinyl resistor; (d) a first reference voltage terminal;
(E) having at least a second source, a second gate, a second drain, and a substrate, wherein the second source and the second drain are electrically connected to at least the output terminal; A second transistor having a substrate electrically connected to the first reference voltage terminal;
Means for supplying a binary digital signal to the second gate for selecting one of the gate channel capacitance of the second and the second substantially larger gate channel capacitance.

An advantage of the present invention is that it eliminates the need for complex feedback and control circuitry from CMOS vernier delays. Yet another advantage is that the present invention reduces the inherent delay of the vernier delay circuit.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Vernier delay circuits are generally known. When implementing a vernier delay circuit in general,
Coarse and fine delays are performed using RC circuits.
The delay is switchable, which results in a modification of the delay time. Delay adjustment is accomplished by calibrating the circuit to set the delay to a desired level and running the calibrated circuit until further calibration is performed. Alternatively, the delay adjustment is changed periodically.

Hereinafter, embodiments of the present invention will be described in detail with reference to FIGS.

FIG. 1 shows a prior art circuit diagram used for a fine delay adjustment circuit for vernier delay and for use in CMOS. The input buffer 1 is provided with an input signal at its input terminal. The buffered signal is sent from the output terminal of input buffer 1 to the input terminal of output buffer 2. The output of output buffer 2 forms the circuit output. Variable capacitor 4
Is connected between the ground 5 and the output terminal of the input buffer 1. The buffered signal causes the variable capacitor 4 to change. The resistance at the output side of the input buffer 1 and the resistance at the input side of the output buffer 2 combine with the capacitance of the variable capacitor 4 to form an RC circuit. Thus, a signal delay depending on the specific resistance and the capacitance occurs.

Digital / analog converter (DAC) 3
Applies a bias voltage to the input buffer 1 and the output buffer 2 to calibrate the vernier delay and correct the temperature change. The use of a digital / analog converter 3 for such purposes is well known. The biasing of the voltage is necessary to compensate for the change in resistance at the output of the input buffer 1 and at the input of the output buffer. The reason is that as a result of the change in resistance, R
This is to prevent an undesired change in the value of the C circuit.

FIG. 2 is a diagram showing a variable capacitor according to the prior art. The capacitors 8 are respectively connected in series to the transistors 9. The capacitor 8 and transistor 9 in series are in parallel with the other capacitor 8 and transistor 9 in series. Each transistor 9
A digital input signal is applied to the gate electrode of the first stage. When the signal is sufficient to turn the transistor "on" (conductive), the series capacitor 8 associated with the transistor 9 forms part of an RC circuit. When the transistor 9 is "off" (non-conducting state), the part of the RC circuit is not formed because the associated series capacitor 8 does not change. This is a brief description of the circuit of FIG. A detailed analysis of the circuit is not necessary for an understanding of the present invention.

FIG. 3 is a block diagram schematically illustrating a vernier delay circuit implemented in CMOS according to the present invention. An input signal is provided to the input port 20. This input signal is applied to the D latch 22. This D
A signal from the latch 22 is gated by a clock signal in a logic gate 24 serving as a NAND gate, and is sent to an input buffer 26.
8

A plurality of digital input signals of the D (10: 0) format are provided to a series of flip-flops 27 for holding the signals for an appropriate period of time. Once set or cleared, a plurality of digital input signals in D (5: 0) format provide a fine delay circuit 2 for controlling delay adjustment.
8 given. These signals form the data bus part. The delayed (delayed) signal is sent from the fine delay circuit 28 to the first coarse delay circuit 29. First coarse delay circuit 2
9 delays the signal given to it by different times, ie 550 ps delay, 1100 ps delay, 1650 ps
Delay by the delay. A multiplexer (MUX) 32 receives a delayed signal different from the signal supplied to the first coarse delay circuit 29 in three ways, and decodes the data bus in a decoder 32a that performs decoding from 2 bits to 4 bits. In response to the signal from D, one of the four decoder outputs is provided to the second coarse delay circuit 34. The second coarse delay circuit 34 converts the signal given thereto into n × (m × 550p
Delay by five different delays in the form of s). Here, n represents a predetermined roughness to the delay, such as 1 to 5, and m represents 4, for example. The second set of delay signals is provided to multiplexer 36 along with the signal provided to second coarse delay circuit 34. Decoded in a decoder 36a for decoding from 3 bits to 6 bits,
According to the signal from the data bus D latched by the latch 36b, one of the seven signals changes to the output port 39 of the circuit.
Given to.

The input signal received at the input port 20 is thus transmitted to the first fine delay circuit 28, the first coarse delay circuit 2
9, and a second coarse delay circuit 34. It will be apparent to one skilled in the art that this need not be the case. An arbitrary number of fine delay circuits and coarse delay circuits are used by selection. It is also known that, as the number of circuits increases or their order is rearranged, the connection between circuit elements is changed by changing the latch, thereby changing the inherent delay. And by taking into account other designs the timing can be varied.

FIGS. 4 and 5 are schematic diagrams of high-level blocks of the circuit shown in FIG. FIG. 4 is a diagram schematically showing the fine delay circuit 28. The signal applied to the fine delay circuit 28 is buffered via P1 and N6, and then buffered via P2 and N7. Vinyl insulated wire resistors (vinyl resistors) 30 and 31 provide a substantial resistance portion to the RC circuit. The use of a vinyl insulated wire resistor in series with a CMOS inverter improves the temperature invariance of the total resistor. The reason for this is that the vinyl insulated wire resistors 30, 31 are less susceptible to temperature than the intrinsic CMOS buffer output resistance, ie, an inverter without a resistor in series with it. The resistance values for the vinyl insulated wire resistors 30, 31 are selected to be reasonably greater than the intrinsic impedance of transistors P1, P2, N6, and N7.
The buffered signal B comprises four transistors P3, P3
4, N8, and N9. The buffered signal B is also supplied to the source and drain of each of the NMOS transistors N0 to N5. The transistor substrates for NMOS transistors N0-N5 are electrically connected to ground. One capacitor is formed between the date oxide and the inductive channel of each transistor. The formed capacitors are arranged in parallel. As is well known in the electronics art, capacitors arranged in parallel are considered to have their capacitance added together.

Capacitors N0-N5 are each formed from an NMOS transistor having a shorted source and drain together and a substrate connected to ground. The gate of each transistor is supplied with a data signal from a data bus represented by D (5: 0). Each of the data signals D (5: 0) is electrically connected to the gate of the transistor. Each of the NMOS transistors N0 to N5 has a different capacitance value. n, 2n, 4n, 8n, 16
A great deal of flexibility is achieved when exponentially increasing values of the form n, and 32n are selected. Here, n corresponds to the capacitance required to produce a delay with the desired resolution of the fine delay circuit.

FIG. 6 is a diagram schematically showing an NMOS transistor. Gate g is normally spaced from drain d and source s. The source s and the drain d are located in the P-type substrate and are electrically coupled. An intrinsic capacitance exists between the gate g and the source s. This capacitance is very small in relation to the distance and the surface area of the capacitive plate in the form of the source and the gate.
In FIG. 6, the gate g is shown connected to ground or another low voltage power supply. In this state, the intrinsic capacitance is substantially negligible in practical use.

FIG. 7 shows the transistor of FIG. 6 with the gate g connected to a high voltage source. The high voltage source is typically 5 volts, but can be varied within known and well understood ranges. When a voltage is applied to the gate g, a channel c is formed between the source s and the drain d. This achieves the effect of a normal transistor operating as a switch. As can be seen from FIG. 7, channel c and gate g have substantially increased capacitance. 6 because the distance between the capacitive plates is smaller and the surface area is larger than in the transistor of FIG. Here, the capacitance is approximated by C _gds = C _ox WL. WL is actually the area of the capacitive plate, especially the area of the gate g.

FIG. 8 is a graph of the capacitance of the NMOS transistor shown in FIGS. The capacitance is substantially zero until the threshold voltage value V _th is applied to the gate g.
The channel c is formed at this voltage (threshold voltage value V _th ), and the capacitance rapidly increases to a value approximated by the above equation. A more detailed analysis is provided in Appendix A.

With respect to the operation of the digitally controlled capacitor, the PMOS and NMOS transistors are not identical. FIG. 9 is a circuit diagram schematically showing the digital control capacitor. Input terminal A receives the input signal and sends it to the input buffer. The output terminal B of the input buffer is connected to a digital control capacitor. Since the voltages are relative, when the voltage V _{sd at} the output terminal B increases to exceed the voltage V _{g at the} gate g minus the threshold voltage V _th , the capacitance is substantially zero. Becomes The capacity follows the graph of FIG. In this case, V _g is V
_g - _Vsd .

Regarding the delay of the rising edge, N
MOS transistors allow the voltage at B to be similar to the rise described in FIG. The standard curve for charging the capacitor in the RC circuit is shown by the dotted line. As can be seen from the graph, when V _g -V _th is smaller than the base voltage V _B, the capacitor expired, the voltage at the output terminal B rises sharply. This is desirable as a result of a sharp rising edge.

FIG. 11 is a circuit diagram schematically showing a digitally controlled PMOS capacitor. Input terminal A receives the input signal and sends it to the input buffer. Output terminals B _o of the input buffer is connected to the digital control PMOS capacitor. Figure 12 is when a PMOS transistor is operating as a capacitor, is a graph showing the response at the output terminal B _o with respect to the rising edge. in this case,
A sharp rise occurs initially, after which a substantially standard capacitance charging curve for the RC circuit follows. It is less desirable for the initial voltage to increase quickly and for circular signals to replace square signals. Conversely, once the gate voltage V _g falls below the threshold voltage value V _th , a quick voltage drop occurs, so a PMOS is suitable for delaying the falling edge.

FIG. 13 is a diagram showing a circuit including an NMOS digital control capacitor and a PMOS digital control capacitor. FIG. 14 is a graph showing a response at the output terminal B to a rising edge. An inverted similar graph is applied to the falling edge. The use of NMOS and PMOS transistors in this manner can cause a delay on both the rising and falling edges, while maintaining their respective advantages.

The capacitance C _gd between the source or the drain and the gate of the NMOS transistor changes from 0 to a known capacitance when the gate voltage V _g rises. That is, the capacitance is programmable by the gate voltage V _g. P
The capacitance C _gd between the source or the drain and the gate of the MOS transistor changes from 0 to a known capacitance when the gate voltage V _g falls. By using this programmable capacity, the delay in the CNOS vernier can be controlled. As a result, a delay circuit that is not affected by temperature, is easy to design, and effectively reduces its inherent delay is realized. At any one time, the sum of the capacitances of each transistor exists between the output terminal B and ground. This capacitance changes the state of each transistor acting as a capacitor from “on” to “off”
D to change from “off” to “on”
It is corrected by correcting (5: 0).

The total delay of the circuit shown in FIG. 4 is the sum of the delay due to the input buffer, the delay due to the output buffer, and the delay at the output terminal (node) B itself. The buffer delay is considered an intrinsic delay. On the other hand, the delay created by the vinyl insulated wire resistance (vinyl resistor) and the digitally controlled capacitor forms a variable delay.

With respect to the single transistor described above,
Gate channel capacity is approximated by _{D (i) (C ox W} i L eff-i). Here, D (i) is 0 or 1 depending on the voltage applied to the gate of the transistor. W and L _eff are the gate dimensions, i is the transistor identifier (Iden
tifier). Referring to FIG. 4, there are six transistors N0～N5, and, when they are to be identified (identification) and from 0 to 5, the total capacitance C _b is given by the following equation.

[0037]

(Equation 1)

WL determined as described above, where W _i
By choosing an exponentially increasing value for L _eff-i = 1 / 2W _{i + 1} L _{eff + 1} , the effective gate area from one transistor to the next doubles, and Equation (1) is solved as follows.

[0039]

(Equation 2)

[0040] When all the D (i) is 0, the above equation (2) is reduced to C _L. At this time, considerable flexibility is allowed in the value of the sum. Obviously, the capacity C
_b is programmable using a sequence of binary input signals.

The minimum capacity is considered negligible, but throughout this specification it is approximated as zero capacity. However, this is not the case. In designing, it is considered that the minimum capacitance realizes the inherent delay of the fine delay circuit 28. In this regard, the number of transistors used as capacitors in the fine delay circuit 28 determines the design for balancing inherent delay and flexibility. Further, each transistor is designed to maintain a substantial capacitance difference between the "on" and "off" states.

It will be apparent to one skilled in the art that temperature changes determine the circuit delay. The delay is related to the RC circuit. C is formed from an intrinsic capacitance and a variable capacitance.
R is formed from the specific resistance and the resistance of the vinyl insulated wire. Therefore, (R _i + R _pw ) (C _i + C _v ) is related to delay. In the above design, C _i + C _v hardly changes with temperature change. R _i varies considerably with temperature. When R _pw is selected to be substantially greater than the variation of R _i over a predetermined range of temperatures, the change in delay adjustment is maintained within predetermined limits. In the above design, the R _pw is 10 times the approximately R _i. This is appropriate for this application. Other applications require larger values or lower values of R _pw with respect to R _i . Alternatively, R _pw is not required in certain temperature controlled environments.

Alternatively, a buffer circuit different from that already shown in the figures is used in the circuit. Alternatively, other temperature compensating means are used instead of vinyl insulated wire resistance. Examples of temperature correction means include temperature control such as heating or air conditioning, internal IC heating, and temperature maintenance. Alternatively, a voltage that fluctuates with temperature is used as an input signal to a digital-to-analog converter to program additional delay circuits in response to temperature fluctuations. Still further, for a different type of device or a delay circuit with a quiescent state than that disclosed above, a capacitor is connected between the output terminal B and a second level other than ground, for example. You. The capacitance between output terminal B and a voltage source in the form of VDD can also support the opposite polarity.

Still further, p-type and n-type transistors are used in a single fine delay circuit 28 to delay the rising and falling edges.

By using transistors to form digitally controlled capacitors, the number of components in fine delay circuit 28 can be reduced. In general, the lower the number of components, the lower the inherent delay and the less interference between components. This is true for the above circuit. Of course, it will be apparent to those skilled in the art that the layout (circuit design) has a significant effect on the inherent delay and interference between components, and that the layout must be designed to reduce these effects. Less interference between components often results in higher frequency response and / or better bandwidth.

The use of a capacitor in series with a transistor to provide a variable capacitor as known in the prior art increases integrated circuit area, complicates layout, and reduces path length, inherent delay, and component-to-component. Increase interference. Thus, using the digitally controlled capacitor is more beneficial.

Although FIG. 4 shows an NMOS transistor, it will be apparent to those skilled in the art that a PMOS transistor also plays a desirable role. PMOS realization and N
A mixed realization of MOS and PMOS is shown in FIGS.

FIG. 5 is a diagram schematically showing a coarse delay circuit element. Since the delay provided by the coarse delay circuitry is not variable, the delayed signal is switched using a multiplexer. However, each delay circuit is the same. Alternatively, the delay circuits are similar but not identical. Alternatively, different delays are implemented using different delay circuits. In order for the first coarse delay circuit 29 to create three different delays, a single delay path with three delay circuit elements is used. This is shown in detail in FIG. Each delay circuit element is substantially the same as the circuit shown in FIG. Alternatively, three separate delay paths are used.

Referring back to FIG. There, vinyl insulated wire resistance 40,
41 are used. The delay of this circuit is substantially 55
0 ps. As is well known in the prior art,
Transistor 43 is used as a junction capacitor.

The first coarse delay circuit 29 is composed of three serially arranged delay circuits as shown in FIG. 5, each output of which is led to the output of the first coarse delay circuit 29. Formed from

Multiplexers are well known in the art, and therefore require no further explanation and are not shown in detail. Decoders of the type from 2 bit to 4 bit decoder 32a are also well known and need not be described in detail here. Flip-flops 27 are also well known in the art.

The second coarse delay circuit 34 is formed from five delay circuits arranged in series, each output of which is led to the output of the second coarse delay circuit 34. The delay circuit comprises four delay circuits connected in series, and provides a delay substantially four times that of a single delay circuit.

FIG. 15 is a diagram schematically showing an alternative fine delay circuit 28. As shown in FIG. The fine delay circuit element shown here is suitable for delaying the falling edge. The signal provided to the fine delay circuit 28 is buffered via P1 and N6 and then buffered again via P2 and N7. Vinyl insulated wire resistors 30, 31 provide a substantial resistance portion to the RC circuit. The use of vinyl insulated wire resistors in series with CMOS inverters reduces the overall resistance because vinyl insulated wire resistors are less sensitive to temperature than the intrinsic CMOS buffer output resistance, that is, an inverter without a resistor in series with it. Temperature invariance is improved. The resistances of resistors 30, 31 are selected to be reasonably greater than the intrinsic impedance of transistors P1, P2, N6, and N7. The buffered signal B is also supplied to the source and drain of each of the PMOS transistors N0 to N5. The transistor substrates of the PMOS transistors N0 to N5 are electrically connected to _VDD . When a suitable voltage is applied to each gate, one capacitor is formed between the gate oxide of each transistor and the inductive channel. The formed capacitors are arranged in parallel. As is well known in the electronics art, capacitors arranged in parallel are considered to have their capacitance added together.

[0054] Each capacitor N0 N5 is formed from a PMOS transistor having a substrate source and drain which is electrically connected to the shorted ones and V _DD together. The gate of each transistor has a D
A data signal from the data bus indicated by (5: 0) is applied. Each of the data signals D (5: 0) is electrically connected to the gate of the transistor. Each transistor N0
To N5 have different capacitance values. The capacitance value of each transistor is associated with the gate dimensions W (width) and L (length), and therefore, by changing these areas,
The capacitance between the gate and the channel changes. n, 2n,
A greater degree of flexibility is supported when exponentially increasing values in the form of 4n, 8n, 16n, and 32n are selected. Here, n corresponds to the capacitance required to execute the delay having the desired resolution of the fine delay circuit.

FIG. 16 is a diagram schematically showing an alternative fine delay circuit 28. As shown in FIG. The fine delay circuit element shown here is suitable for delaying both rising and falling edges. The signal supplied to the fine delay circuit 28 is buffered via P1 and N6 and then buffered again via P2 and N7. Vinyl insulated wire resistors 30, 31 provide a substantial resistance portion to the RC circuit. The resistance values for the vinyl insulated wire resistors 30, 31 are selected to be reasonably greater than the intrinsic impedance of transistors P1, P2, N6, and N7.
The buffered signal B comprises four transistors P3, P3
4, N8, N9. The buffered signal B is also supplied to the source and drain of each of the PMOS transistors N0 to N2 and the source and drain of each of the NMOS transistors N3 to N5. The transistor substrates of the transistors N0 to N2
_It is electrically connected to _DD . The transistor substrates of the transistors N3 to N5 are electrically connected to the ground. When a suitable voltage is applied to each gate, one capacitor is formed between the gate oxide of each transistor and the inductive channel. The formed capacitors are arranged in parallel. As is well known in the electronics art, capacitors arranged in parallel are considered to have their capacitance added together.

The gate of each transistor has D
A data signal from the data bus indicated by (5: 0) is applied. Each of the data signals D (5: 0) is electrically connected to the gate of the transistor. Each transistor N0
ＮN5 have different gate areas and therefore have different capacitance values. n, 2n, 4n, 8n, 16n, and 32
When an exponentially increasing value in the form of n is selected, a greater degree of flexibility is ensured. Where n
Corresponds to the capacitance required to implement a delay with the desired resolution of the fine delay circuit. When delaying the rising and falling edges, it is preferable to use more components than those shown in the schematic.

Those skilled in the art will discuss the layout
Recognize what is important in design. The above design is no exception. In the design of such circuits, design assumptions are crucial to accurate simulation. Layout must be performed prior to simulation. And some layout design rules may need to be changed.

In the layout of the fine delay circuit 28, the specific capacitance is reduced, and the required layout space of the integrated circuit is greatly reduced by sharing the adjacent pads. FIG. 16 is a diagram showing a layout according to the prior art for a large number of transistors. Each transistor is provided with its own source, drain, and gate. The space occupied by the transistors in such an implementation is the sum of the transistor space and the required additional component clearance.

FIG. 18 is a diagram showing a plurality of transistors. In this case, the space between the transistors and the gap between the components are removed, and the adjacent source and drain are separated by two.
(Note that FIG. 17 is a simplified layout diagram of a fine delay circuit according to the prior art). Space savings from such designs are important. First, the gap between the components is reduced to zero. Second, the space occupied by the illustrated transistors can be as much as the required space for a single transistor multiplied by the number of transistors, to the space occupied by one source or drain multiplied by the number of transistors. It is subtracted. Thus, space savings are linearly proportional to the number of digitally controlled capacitors laid out in this manner.

FIG. 19 is a diagram showing the first transistor connected to the trace B. The transistor drain for that transistor serves as the source for the next transistor. It is also connected to trace B. In use, a capacitor is formed between the gate and the channel c or between the source and the drain. Using a structure similar to the source for the first transistor and the drain for the second transistor has little effect on capacitance, saves board space, reduces intrinsic capacitance, and reduces circuit cost. Can be realized.

[0061] Numerous other embodiments can be considered within the scope of the invention as set forth in the following claims.

[0062]

As described above, according to the present invention, it is possible to provide a CMOS delay circuit which has a high resolution with a simple structure and is substantially invariant with respect to temperature.
A CMOS vernier delay (fine delay circuit) for effectively using the MOS integrated circuit region can be provided.
It also eliminates the need for complex feedback and control circuitry from CMOS vernier delays.
Further, according to the present invention, there is obtained an advantage that the inherent delay of the vernier delay circuit is reduced.

[Brief description of the drawings]

FIG. 1 shows a conventional vernier delay circuit CMOS.
FIG. 3 is a diagram schematically showing a fine delay circuit element used in realization.

FIG. 2 is a schematic diagram of a variable capacitor according to the prior art used in the circuit of FIG. 1;

FIG. 3 is a schematic block diagram of a vernier delay circuit according to the present invention.

FIG. 4 is a schematic configuration diagram of a fine delay circuit used in the circuit of FIG. 3 according to the present invention;

FIG. 5 is a schematic configuration diagram of a delay circuit having a substantially fixed delay.

FIG. 6 is a schematic diagram of an NMOS transistor in which a low voltage is applied to a gate.

FIG. 7 is a schematic diagram of an NMOS transistor in which a high voltage is applied to a gate.

FIG. 8 is a graph showing the capacitance characteristics of the transistors in FIGS. 6 and 7.

FIG. 9 is a schematic diagram of a delay circuit including an NMOS transistor.

10 is a graph showing a voltage at an output terminal B in the delay circuit of FIG.

FIG. 11 is a schematic diagram of a delay circuit including a PMOS transistor.

12 is a graph showing a voltage at an output terminal B in the delay circuit of FIG.

FIG. 13 is a schematic configuration diagram of a delay circuit including an NMOS transistor and a PMOS transistor.

14 is a graph showing a voltage at an output terminal B in the delay circuit of FIG.

FIG. 15 is a schematic configuration diagram of a fine delay circuit using a PMOS transistor according to the present invention.

FIG. 16 shows an NMOS transistor and P according to the present invention.
FIG. 2 is a schematic configuration diagram of a fine delay circuit using a MOS transistor.

FIG. 17 is a simplified layout diagram of a fine delay circuit according to the related art.

FIG. 18 is a simplified layout diagram of a transistor in a fine delay circuit element according to the present invention.

FIG. 19 is a simplified layout diagram of a transistor in a fine delay circuit element with an inductive channel indicated by a dotted line according to the present invention.

[Explanation of symbols]

Reference Signs List 1 input buffer 2 output buffer 3 digital / analog converter (DAC) 4 variable capacitor 5 ground 8 capacitor 9 transistor 20 input port 22 D-latch 24 logic gate 26 input buffer 27 flip-flop 28 fine delay circuit 29 first coarse delay circuit 32, 36 multiplexer 32a, 36a decoder 34 second coarse delay circuit 36b latch 39 output port 30, 31, 40, 41 vinyl insulated wire resistance (vinyl resistor) 43 transistor N0 to N5, P1 to P4 transistor

Continued on the front page (72) Inventor Bruce Miller, K2S 1B6 Ontario, Stittsville, Farnban Claude, Canada 6066 (72) Inventor Claude Schwanal J9A2K8, Canada Quebec, Hull, Avignon de Jonquil 185, ♯109

Claims (18)

[Claims] (A) a first terminal; (b) a second terminal; (c) a reference voltage terminal; and (d) a series connection of the first terminal and the second terminal. Resistance means,
(E) including a source, a gate, a drain, and a substrate;
A transistor having the source and the drain electrically connected to the second terminal, and the substrate electrically connected to the reference voltage terminal; and (f) a first capacitor and a second substance. Means for supplying a binary digital signal to the gate for selecting any one of a target larger capacity. 2. The MOS variable delay circuit according to claim 1, wherein said resistance means comprises a vinyl resistor. 3. An input buffer comprising a transistor having a gate connected to an input terminal, a source connected to a reference voltage source V _DD , and a drain connected to the first terminal. The MOS variable delay circuit according to claim 1, wherein: 4. The resistance means comprises a vinyl resistor,
2. The MOS variable delay circuit according to claim 1, wherein the transistor is an NMOS transistor, and the reference voltage terminal is a ground voltage terminal. 5. The resistance means comprises a vinyl resistor,
2. The MOS variable delay circuit according to claim 1, wherein the transistor is a PMOS transistor, and the reference voltage terminal is a _VDD voltage terminal. And (g) a second source, a second gate, a second drain, and a second substrate, wherein the second source and the second drain are connected to the second terminal. (H) an electrically connected second transistor, wherein the second substrate is electrically connected to the reference voltage terminal;
Second means for providing a second binary digital signal to the second gate for selecting between a first capacitance and a second substantially larger capacitance. 2. The MOS variable delay circuit according to claim 1, wherein: 7. The MOS variable delay circuit according to claim 6, wherein said resistance means comprises a vinyl resistor. And (g) each comprising a further source, a further gate, a further drain, and a further substrate, each said further source and each said further drain being electrically connected to said second terminal. And a plurality of further transistors, each said further substrate being electrically connected to said reference voltage terminal;
(H) further means for providing a further binary digital signal to each gate of the further transistor for selecting between the first capacitance and the second substantially larger capacitance. 2. The MOS variable delay circuit according to claim 1, wherein: 9. The MOS variable delay circuit according to claim 8, wherein said resistance means comprises a vinyl resistor. 10. An input buffer comprising a transistor having a gate connected to an input terminal, a source connected to a reference voltage source _VDD , and a drain connected to the first terminal. The MOS variable delay circuit according to claim 8, wherein: 11. The resistance means comprises a vinyl resistor, the transistor is an NMOS transistor,
9. The MOS variable delay circuit according to claim 8, wherein the reference voltage terminal is a ground voltage terminal. 12. The resistance means comprises a vinyl resistor, the transistor is a PMOS transistor,
9. The MOS variable delay circuit according to claim 8, wherein said reference voltage terminal is a _VDD voltage terminal. 13. The transistor according to claim 8, wherein one of the source and the drain of the first transistor is a source or a drain of a second other transistor.
OS variable delay circuit. 14. A first terminal, (b) a second terminal, (c) a first reference voltage terminal, and (d) a second terminal.
(E) the first terminal and the second terminal
(F) each including a source, a gate, a drain, and a substrate, wherein the source and the drain are electrically connected to the second terminal. A plurality of n-type transistors each having the substrate electrically connected to the first reference voltage terminal; and (g) each including a source, a gate, a drain, and a substrate. Are electrically connected to the second terminal and the substrate is electrically connected to the second reference voltage terminal.
A type transistor; and (h) means for providing a binary digital signal to each of said gates for selecting between a first capacitance and a second substantially larger capacitance.
A MOS variable delay circuit comprising: 15. The MOS variable delay circuit according to claim 14, wherein said resistance means comprises a vinyl resistor. 16. The first reference voltage terminal is electrically connected to a ground terminal, and the second reference voltage terminal is
The MOS variable delay circuit according to claim 14, wherein the MOS variable delay circuit is electrically connected to a _DD voltage terminal. 17. The first of a type selected from n-type or p-type.
15. The MOS variable delay circuit according to claim 14, wherein one of a source and a drain of the transistor is a source or a drain of a second other transistor of the same type. 18. A circuit used in a vernier delay circuit, comprising: (a) an input terminal; (b) a first gate connected to the input terminal; and a first gate connected to a V _DD voltage terminal. An input buffer including at least a first transistor having a source and a first drain, and a vinyl resistor having a first terminal and a second terminal connected to the first drain, respectively; c) an output terminal electrically connected to the second terminal of the vinyl resistor; (d) a first reference voltage terminal; and (e).
At least a second source, a second gate, a second drain, and a substrate are provided, and the second source and the second
A second transistor having a drain electrically connected to at least the output terminal and a substrate electrically connected to the first reference voltage terminal; and (f) a first gate-channel capacitance and a second transistor. Means for providing a binary digital signal to the second gate for selecting one of the two substantially larger gate-channel capacitances.