GB9727375D0 - Delay circuits - Google Patents

Delay circuits

Info

Publication number
GB9727375D0
GB9727375D0 GBGB9727375.9A GB9727375A GB9727375D0 GB 9727375 D0 GB9727375 D0 GB 9727375D0 GB 9727375 A GB9727375 A GB 9727375A GB 9727375 D0 GB9727375 D0 GB 9727375D0
Authority
GB
United Kingdom
Prior art keywords
delay circuits
delay
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GBGB9727375.9A
Other versions
GB2321144A (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mosaid Technologies Inc
Original Assignee
Mosaid Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mosaid Technologies Inc filed Critical Mosaid Technologies Inc
Publication of GB9727375D0 publication Critical patent/GB9727375D0/en
Publication of GB2321144A publication Critical patent/GB2321144A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H03K2005/00058—Variable delay controlled by a digital setting
    • H03K2005/00071—Variable delay controlled by a digital setting by adding capacitance as a load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay
    • H03K2005/00143—Avoiding variations of delay due to temperature

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
GB9727375A 1996-12-31 1997-12-24 Temperature-insensitive adjustable CMOS fine delay circuit Withdrawn GB2321144A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3398196P 1996-12-31 1996-12-31
US81806897A 1997-03-14 1997-03-14

Publications (2)

Publication Number Publication Date
GB9727375D0 true GB9727375D0 (en) 1998-02-25
GB2321144A GB2321144A (en) 1998-07-15

Family

ID=26710404

Family Applications (1)

Application Number Title Priority Date Filing Date
GB9727375A Withdrawn GB2321144A (en) 1996-12-31 1997-12-24 Temperature-insensitive adjustable CMOS fine delay circuit

Country Status (3)

Country Link
JP (1) JPH10247842A (en)
CA (1) CA2224767A1 (en)
GB (1) GB2321144A (en)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3667196B2 (en) 2000-05-26 2005-07-06 Ｎｅｃエレクトロニクス株式会社 Timing difference division circuit
JP2002135086A (en) * 2000-10-27 2002-05-10 Asahi Kasei Microsystems Kk Oscillator
US20030231038A1 (en) * 2002-06-13 2003-12-18 Kenneth Koch Pulse shaping circuit and method
US6753708B2 (en) 2002-06-13 2004-06-22 Hewlett-Packard Development Company, L.P. Driver circuit connected to pulse shaping circuitry and method of operating same
JP4416735B2 (en) 2003-10-17 2010-02-17 富士通マイクロエレクトロニクス株式会社 Semiconductor device
JP4687951B2 (en) * 2004-12-24 2011-05-25 横河電機株式会社 Programmable delay generator
JP5204998B2 (en) * 2006-06-30 2013-06-05 株式会社半導体エネルギー研究所 Semiconductor device
US7821315B2 (en) * 2007-11-08 2010-10-26 Qualcomm Incorporated Adjustable duty cycle circuit
US8615205B2 (en) 2007-12-18 2013-12-24 Qualcomm Incorporated I-Q mismatch calibration and method
JP4842989B2 (en) 2008-03-28 2011-12-21 株式会社アドバンテスト Priority encoder, time digital converter and test device using the same
US8970272B2 (en) 2008-05-15 2015-03-03 Qualcomm Incorporated High-speed low-power latches
JP2008219946A (en) * 2008-06-02 2008-09-18 Fujitsu Ltd Semiconductor device
US8712357B2 (en) 2008-11-13 2014-04-29 Qualcomm Incorporated LO generation with deskewed input oscillator signal
US8718574B2 (en) 2008-11-25 2014-05-06 Qualcomm Incorporated Duty cycle adjustment for a local oscillator signal
US8847638B2 (en) 2009-07-02 2014-09-30 Qualcomm Incorporated High speed divide-by-two circuit
US8791740B2 (en) 2009-07-16 2014-07-29 Qualcomm Incorporated Systems and methods for reducing average current consumption in a local oscillator path
US8854098B2 (en) 2011-01-21 2014-10-07 Qualcomm Incorporated System for I-Q phase mismatch detection and correction
US9154077B2 (en) 2012-04-12 2015-10-06 Qualcomm Incorporated Compact high frequency divider

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940005004B1 (en) * 1991-03-21 1994-06-09 삼성전자 주식회사 Signal delay circuit
FR2696061B1 (en) * 1992-09-22 1994-12-02 Rainard Jean Luc Method for temporally delaying a signal and corresponding delay circuit.

Also Published As

Publication number Publication date
GB2321144A (en) 1998-07-15
CA2224767A1 (en) 1998-06-30
JPH10247842A (en) 1998-09-14

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)