JP5204998B2 - Semiconductor device - Google Patents

Description

The present invention relates to a semiconductor device capable of communicating data by wireless communication. In particular, the present invention relates to a semiconductor device including therein a clock generation circuit that generates a clock without depending on a signal in wireless communication. The present invention also relates to an electronic device including the semiconductor device.

In recent years, as described in the ubiquitous information society, an environment where an information network can be accessed in any state has been developed. In such an environment, attention has been given to an individual recognition technique in which an ID (individual identification number) is given to each individual object, thereby clarifying the history of the object and making use of it for production, management, and the like. Among these, RFID (Radio Frequency Identification) technology using a semiconductor device capable of communicating data by wireless communication such as an RFID tag (also referred to as an IC tag, an RF tag, a wireless tag, or an electronic tag) is beginning to be used.

  A general structure of a semiconductor device capable of data communication by wireless communication will be described with reference to FIG. A semiconductor device 201 capable of data communication by wireless communication includes an antenna 202 and a semiconductor integrated circuit 211. The semiconductor integrated circuit 211 includes circuit blocks such as a high-frequency circuit 203, a power supply circuit 204, a reset circuit 205, a clock generation circuit 206, a data demodulation circuit 207, a data modulation circuit 208, a control circuit 209, and a memory circuit 210. A radio signal is received by the antenna 202. The wireless signal is sent to the power supply circuit 204 via the high frequency circuit 203, and a power supply is generated. This power is supplied to a plurality of circuits constituting the semiconductor integrated circuit 211. On the other hand, the signal demodulated by the data demodulation circuit 207 via the high frequency circuit 203 and the signal passed through the reset circuit 205 via the high frequency circuit 203 are sent to the control circuit 209. The signal sent to the control circuit 209 is analyzed by the control circuit 209. Information stored in the memory circuit 210 is output in accordance with the analyzed signal. Information output from the memory circuit 210 is encoded through the control circuit 209. Further, the encoded signal passes through the data modulation circuit 208 and is transmitted on the radio signal by the antenna 202 and transmitted.

Among the circuit blocks shown in FIG. 2, the clock generation circuit 206, the control circuit 209, and the memory circuit 210 receive and input digital signals. Among them, the clock generation circuit 206 is a block for creating a reference signal for the control circuit 209 to operate correctly, and its role is important. As such a clock generation circuit 206, a PLL (Phase Locked Loop) circuit is generally used. As specific examples of the PLL circuit, various types of circuits have been developed including those described in Patent Document 1 and Patent Document 2, for example.
JP-A-7-326964 Japanese Patent Laid-Open No. 10-233768

FIG. 3 shows a basic configuration of a conventional PLL. The PLL circuit shown in the figure includes a phase comparator 301, a loop filter 302 (hereinafter referred to as LF), a voltage controlled oscillator 303 (hereinafter also referred to as VCO (Voltage Controlled Oscillator)), and a frequency divider 304. In FIG. 3, the PLL circuit uses a variable frequency signal (corresponding to INPUT in FIG. 3) input to the PLL circuit as a feedback signal, and performs phase comparison with the supplied signal. Then, the PLL circuit performs adjustment by negative feedback so that the supplied signal and the feedback signal have a constant phase. In FIG. 3, the phase comparator 301 detects the phase difference between the signal Fs input from the outside and the signal Fo / N input from the frequency divider 304. The loop filter 302 generates a signal Vin obtained by removing an AC component from the signal supplied from the phase comparator 301. The voltage controlled oscillator 303 outputs a signal Fo based on the signal Vin input from the loop filter 302. The frequency divider 304 outputs a signal Fo / N obtained by dividing the signal Fo input from the voltage controlled oscillator 303 by 1 / N.

  In this case, when receiving a signal Fs having a variable frequency from the outside, the PLL circuit performs a phase comparison with the received signal and generates a stably synchronized clock. However, when the signal Fs having a variable frequency from the outside is not received, the PLL circuit must maintain self-oscillation by the clock output from the PLL circuit itself.

On the other hand, the demodulated signal input to the clock generation circuit 206 in FIG. 2 has a voltage level corresponding to a logical value “high” (hereinafter also referred to as H level) and a voltage level corresponding to “low” (hereinafter referred to as L level). (Also referred to as the serial data) is serial data arranged in time series in accordance with the wireless communication standard. Inputting such a demodulated signal to a conventional PLL circuit means that there is a period corresponding to “when the signal Fs is not received” in the description related to FIG. 3 above.

FIG. 4 shows a period in which adjustment by negative feedback is performed and a period in which self-oscillation occurs when a conventional PLL circuit is used as the clock generation circuit 206 in FIG. A waveform 401 is a demodulated signal input to the PLL circuit, and a waveform 402 indicates a feedback signal output from a frequency divider in the PLL circuit. A period 403 is a period during which adjustment by negative feedback is performed, and a period 404 indicates a period during which self-oscillation is performed.

As shown in FIG. 4, the presence of a period during which no negative feedback is applied causes the PLL circuit to be in an unstable state, so that a constant and stable clock cannot be generated, and the frequency of the clock fluctuates, resulting in a communication failure. . As a result, the digital circuit portion constituting the semiconductor device shown in FIG. 2 may malfunction.

In addition to the above-described problems, when the variable frequency from the outside in the semiconductor device for communicating data by wireless communication is high, the duty ratio 50 for outputting a stable clock signal in the clock generation circuit inside the semiconductor device. % Reference clock may not be obtained.

  In the present invention, in view of the above situation, in a semiconductor device capable of communicating data by wireless communication, it is possible to prevent malfunction such as malfunction or non-response caused by using a clock generated based on a demodulated signal. Is an issue.

In order to solve the above-described problems, the present invention provides a ring oscillator that self-oscillates without depending on a demodulated signal in a semiconductor device that communicates data by wireless communication, and sets the output signal of the ring oscillator to a frequency in an appropriate range. A frequency divider to be adjusted is provided. Hereinafter, a specific configuration of the present invention will be described.

One of the semiconductor devices of the present invention includes an antenna circuit for receiving a radio signal, a power supply circuit that generates power by the radio signal received by the antenna circuit, and a clock generation circuit to which power is supplied, The clock generation circuit includes a ring oscillator for oscillating a signal having a constant period, and a frequency divider for dividing the signal output from the ring oscillator.

Another semiconductor device of the present invention includes an antenna circuit for receiving a radio signal, a power supply circuit that generates power from the radio signal received by the antenna circuit, and a clock generation circuit to which power is supplied. The clock generator circuit includes a ring oscillator for oscillating a signal having a fixed period, and a frequency divider for dividing the signal output from the ring oscillator. Each stage of the ring oscillator includes A capacitor element for controlling the oscillation frequency of the ring oscillator is connected.

In the present invention, the capacitive element may be an element using the gate capacitance of a MOS transistor.

In the present invention, the capacitive element may be a variable capacitive element.

In the present invention, the transistors constituting the ring oscillator and the frequency divider may be thin film transistors.

Note that in the present invention, the transistors forming the ring oscillator and the frequency divider may be transistors formed on a single crystal substrate.

Note that the term “connected” in the present invention includes a case where they are electrically connected and a case where they are directly connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, other elements (for example, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) that can be electrically connected are arranged. May be. Alternatively, they may be arranged directly connected without interposing another element therebetween. In addition, it shall be described as being connected directly when including only the case where it is connected without interposing other elements enabling electrical connection between them. Note that the description of being electrically connected includes the case of being electrically connected and the case of being directly connected.

  Note that in the present invention, various types of transistors can be used as a transistor. Thus, there is no limitation on the type of applicable transistor. Therefore, a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, a MOS transistor, a junction transistor, or a bipolar transistor Alternatively, a transistor using a compound semiconductor such as ZnO or a-InGaZnO, a transistor using an organic semiconductor or a carbon nanotube, or another transistor can be used. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. Further, the transistor can be formed using various substrates, and the type of the substrate is not limited to a specific one. Therefore, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, a stone substrate, a stainless steel substrate, a substrate having stainless steel foil, or the like can be used as the substrate. . Alternatively, a transistor may be formed using a certain substrate, and then the transistor may be moved to another substrate and placed on another substrate.

Note that the structure of the transistor can take a variety of forms. It is not limited to a specific configuration. For example, a multi-gate structure having two or more gates may be used. The multi-gate structure reduces off-current, improves the breakdown voltage of the transistor to improve reliability, and even when the drain-source voltage changes when operating in the saturation region. The current does not change so much and it can be made flat. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be employed. By adopting a structure in which the gate electrodes are arranged above and below the channel, the channel region increases, so that the current value can be increased, a depletion layer can be easily formed, and the S value can be decreased. Further, a structure in which a gate electrode is disposed above a channel, a structure in which a gate electrode is disposed below a channel, a normal staggered structure, or an inverted staggered structure may be employed. The channel region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. In addition, a source electrode or a drain electrode may overlap with the channel (or a part thereof). By adopting a structure in which the source electrode and the drain electrode do not overlap with the channel (or part thereof), it is possible to prevent electric charges from being accumulated in part of the channel and unstable operation. There may also be an LDD region. By providing an LDD region, the off-current can be reduced, the breakdown voltage of the transistor can be improved to improve reliability, and the drain-source voltage can be changed even when the drain-source voltage changes when operating in the saturation region. The current does not change so much, and it can be made flat.

Note that a transistor is an element having at least three terminals including a gate, a drain, and a source, and has a channel region between the drain region and the source region. Here, since the source and the drain vary depending on the structure and operating conditions of the transistor, it is difficult to limit which is the source or the drain. Therefore, in the present invention, a region functioning as a source and a drain may not be called a source or a drain. In that case, as an example, there are cases where they are referred to as a first terminal and a second terminal, respectively.

Note that a gate refers to the whole or part of a gate electrode and a gate wiring (also referred to as a gate line). A gate electrode refers to a conductive film which overlaps with a semiconductor that forms a channel region, an LDD (Lightly Doped Drain) region, and the like with a gate insulating film interposed therebetween.

Note that a source refers to the whole or part of a source region, a source electrode, and a source wiring (also referred to as a source line or a source signal line). The source region refers to a semiconductor region containing a large amount of P-type impurities (such as boron and gallium) and N-type impurities (such as phosphorus and arsenic). Therefore, a region containing a little P-type impurity or N-type impurity, that is, a so-called LDD (Lightly Doped Drain) region is not included in the source region. A source electrode refers to a portion of a conductive layer which is formed using a material different from that of a source region and is electrically connected to the source region. However, the source electrode may be referred to as a source electrode including the source region. The source wiring is a connection between the source electrodes of each pixel or a wiring for connecting the source electrode and another wiring.

However, there is a portion that functions as a source electrode and also functions as a source wiring. Such a region may be called a source electrode or a source wiring. That is, there is a region where the source electrode and the source wiring cannot be clearly distinguished. For example, when there is a source region that overlaps with an extended source wiring, the region functions as a source wiring, but also functions as a source electrode. Therefore, such a region may be called a source electrode or a source wiring.

A region formed of the same material as the source electrode and connected to the source electrode, or a portion connecting the source electrode and the source electrode may also be referred to as a source electrode. A portion overlapping with the source region may also be called a source electrode. Similarly, a region formed of the same material as the source wiring and connected to the source wiring may be called a source wiring. In a strict sense, such a region may not have a function of connecting to another source electrode. However, there is a region formed of the same material as the source electrode and the source wiring and connected to the source electrode and the source wiring. Therefore, such a region may also be called a source electrode or a source wiring.

Further, for example, a conductive film in a portion where the source electrode and the source wiring are connected to each other may be referred to as a source electrode or a source wiring.

Note that a source terminal refers to a part of a source region, a source electrode, or a region electrically connected to the source electrode.

The drain is the same as the source.

Note that in the present invention, a semiconductor device refers to a device having a circuit including a semiconductor element (such as a transistor or a diode). In addition, any device that can function by utilizing semiconductor characteristics may be used.

In addition, in the present invention, it is formed on a certain object, or is formed on, such that the description on “on” or “on” is directly applied to a certain object. It is not limited to touching. This includes cases where they are not in direct contact, that is, cases where another object is sandwiched between them. Therefore, for example, when the layer B is formed on the layer A (or on the layer A), the layer B is formed in direct contact with the layer A, and the layer B is formed in direct contact with the layer A. It includes the case where another layer (for example, layer C or layer D) is formed and layer B is formed in direct contact therewith. The same applies to the description of “above”, and it is not limited to being in direct contact with a certain object, and includes a case where another object is sandwiched therebetween. Therefore, for example, when the layer B is formed above the layer A, the layer B is formed in direct contact with the layer A, and another layer (for example, the layer C is formed in direct contact with the layer A). And layer D) are formed, and the layer B is formed in direct contact therewith. It should be noted that the same applies to the case of below or below, and includes the case of direct contact and the case of no contact.

According to the present invention, in a semiconductor device that performs data communication by wireless communication, a digital circuit portion can be driven with a clock signal with high frequency accuracy. Therefore, in a semiconductor device that communicates data using a radio signal, it is possible to prevent a malfunction such as malfunction or no response, and to obtain a semiconductor device that can accurately transmit information stored in a memory circuit in the semiconductor device. .

Embodiments and examples of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments and examples below.
(Embodiment 1)

  One structural example of the semiconductor device of the present invention will be described with reference to a block diagram shown in FIG. Note that in this embodiment, a case where a semiconductor device is used as an RFID chip (hereinafter simply referred to as “RFID”) capable of data communication by wireless communication will be described.

A semiconductor device 101 in FIG. 1 includes an antenna 102 and a semiconductor integrated circuit 111. In FIG. 1, a semiconductor integrated circuit 111 includes circuit blocks such as a high-frequency circuit 103, a power supply circuit 104, a reset circuit 105, a clock generation circuit 106, a data demodulation circuit 107, a data modulation circuit 108, a control circuit 109, and a memory circuit 110. Have. The clock generation circuit 106 includes a ring oscillator 112 and a frequency divider 113.

Note that the semiconductor integrated circuit 111 may be an active type RFID or a passive type RFID. In this embodiment, the description is made assuming that the RFID is a passive type RFID, but the present invention is not limited to this. In the case of an active type RFID, a configuration for providing a battery for supplying power to a power supply circuit may be employed.

As the battery, it is preferable to use a battery formed in a sheet shape having a thickness of 1 μm to several μm. For example, a lithium battery, preferably a lithium polymer battery using a gel electrolyte, a lithium ion battery, or the like, Miniaturization is possible.

Although not shown here, the antenna 102 in FIG. 1 receives a signal from the reader / writer and transmits a signal to the reader / writer. Therefore, in a wireless communication system using the semiconductor device of the present invention, a semiconductor device 101 and a reader / writer having a known configuration, an antenna connected to the reader / writer, and a control terminal for controlling the reader / writer are used. it can.

In FIG. 1, the antenna 102 can be any of a dipole antenna, a patch antenna, a loop antenna, and a Yagi antenna. In addition, a method for transmitting and receiving a radio signal in the antenna 102 may be any of an electromagnetic coupling method, an electromagnetic induction method, and a radio wave method.

Note that the communication method between the semiconductor device 101 and the antenna connected to the reader / writer is unidirectional communication or bidirectional communication, and is a space division multiplexing method, a polarization plane division multiplexing method, a frequency division multiplexing method, Any of time division multiplexing, code division multiplexing, and orthogonal frequency division multiplexing can be used.

The radio signal is a signal obtained by modulating a carrier wave. The modulation of the carrier wave is analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum.

In addition, the frequency of the carrier wave is 300 GHz to 3 THz which is a submillimeter wave, 30 GHz to 300 GHz which is a millimeter wave, 3 GHz to 30 GHz which is a microwave, 300 MHz to 3 GHz which is an ultrashort wave, 30 MHz to 300 MHz which is an ultrashort wave, and 3 MHz which is a short wave. Any frequency of ˜30 MHz, medium wave of 300 KHz to 3 MHz, long wave of 30 KHz to 300 KHz, and super long wave of 3 KHz to 30 KHz can be used.

  Next, the operation of the semiconductor device 101 illustrated in FIG. 1 will be described. A radio signal received by the antenna 102 is sent to each circuit block via the high frequency circuit 103. A power source is generated from a signal sent to the power source circuit 104 via the high frequency circuit 103. This power is supplied to a plurality of circuits constituting the semiconductor integrated circuit 111 including the clock generation circuit 106.

  Note that various types of transistors can be used as a transistor provided in the semiconductor integrated circuit 111. Thus, there is no limitation on the type of applicable transistor. Therefore, a thin film transistor (TFT) using a non-single-crystal semiconductor film typified by amorphous silicon or polycrystalline silicon, a transistor formed using a semiconductor substrate or an SOI substrate, a MOS transistor, a junction transistor, or a bipolar transistor Alternatively, a transistor using a compound semiconductor such as ZnO or a-InGaZnO, a transistor using an organic semiconductor or a carbon nanotube, or another transistor can be used. Note that the non-single-crystal semiconductor film may contain hydrogen or halogen. The semiconductor integrated circuit 111 can be formed using various substrates, and is not limited to a specific one. Therefore, for example, a single crystal substrate, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a paper substrate, a cellophane substrate, or the like can be used as the substrate. Alternatively, the semiconductor integrated circuit 111 may be formed on a certain substrate, and then the semiconductor integrated circuit 111 may be moved to another substrate and placed on another substrate.

Next, the configuration of the ring oscillator 112 of FIG. 1 in the present invention will be described. The ring oscillator 112 self-oscillates by supplying power and outputs a square wave having a constant frequency. The frequency divider 113 receives the output signal of the ring oscillator 112 and divides the frequency to generate a clock signal having an appropriate frequency.

FIG. 5 shows a specific configuration of the ring oscillator. The ring oscillator 501 includes an inverter configuration in which an N-channel transistor 502 and a P-channel transistor 503 are connected in series, and the gates of the two transistors are connected. The inverter includes a plurality of inverters as a unit. It is. The plurality of inverters have a loop structure in which a rear-stage input terminal and a front-stage output terminal are connected, and a final-stage output terminal is connected to a first-stage input terminal. Note that the number of inverters in the loop in the ring oscillator needs to be composed of an odd number of inverters in order to oscillate a signal from the oscillation circuit. In FIG. 5, the ring oscillator 501 has a five-stage configuration (5 units), but is not limited to this. The frequency of the oscillation signal obtained from the ring oscillator is determined by the characteristics of each inverter, the power supply voltage value, and the number of stages. Therefore, the number of inverter stages included in the ring oscillator is determined after comprehensively considering these factors.

FIG. 6 shows a specific configuration of the frequency divider. The frequency divider is mainly composed of a plurality of flip-flops 601. The flip-flop 601 includes an inverter circuit 602, NAND circuits 603 to 609, and inverter circuits 610 and 611. The flip-flop 601 has four input terminals (indicated as in1, in2, in3, and in4 in the drawing) and two output terminals (indicated as out1, out2 in the drawing). The flip-flop 601 includes three latches in total, and includes a NAND circuit 604 and a NAND circuit 605, a NAND circuit 606 and a NAND circuit 607, and a NAND circuit 608 and a NAND circuit 609, respectively. When the set signal is input from the input terminal in1, the data signal is input from the input terminal in2, the clock signal is input from the input terminal in3, and the reset signal is input from the input terminal in4, the data signal is output from the output terminal out1. And a data signal is output from the output terminal out2. Although the above configuration is a static flip-flop circuit, the present invention is not limited to this configuration, and for example, a quasi-static flip-flop circuit using an analog switch or the like may be used.

The frequency divider may be an asynchronous simple ripple counter or a synchronous counter. If necessary, a reset mechanism may be provided, and the frequency division ratio may be programmable. In this way, a stable clock is generated and supplied to a digital circuit unit such as the control circuit 109 in FIG. 1, so that analysis of a demodulated signal, encoding processing, and the like are normally executed.

Next, a timing chart of signals inputted to and outputted from the ring oscillator shown in FIG. 5 and the frequency divider shown in FIG. 6 will be described with reference to FIG.

A waveform 701 is a demodulated signal, and represents that logic “0” and “1” are arranged in time series in accordance with the wireless communication standard. The period 702 is a length assigned to represent 1-bit data in the demodulated signal and is constant. A waveform 703 is a square wave signal output from the ring oscillator, and indicates that it oscillates at a constant frequency regardless of the demodulated signal. A waveform 704 is a digital representation of the value of the counter constituting the frequency divider. It is reset at the falling edge of the waveform 701 of the demodulated signal, and counts up in synchronization with the waveform 703 until the next falling edge is detected. A waveform 705 is a clock signal to be output, and a toggle operation is performed according to the value of the waveform 704. In this example, the output signal of the ring oscillator divided by 4 is used as the clock signal. However, the division ratio is determined according to the required specification, and is not limited to this.

As described above, in the clock generation circuit according to the present invention, a stable clock signal can be obtained without using the demodulated signal from the reader / writer. Of course, the oscillation frequency obtained can be changed by setting the frequency division ratio.

As an example of the power supply circuit in FIG. 1, a circuit diagram is shown in FIG. The power supply circuit includes a current mirror circuit, a source grounded amplifier circuit, a diode-connected transistor, and the like, and includes transistors 801 to 811 and a resistor 812.

  A feedback loop is formed by an analog circuit included in the power supply circuit, and works to keep the output potential constant even when the current flowing from the output terminal 813 changes due to a load change. Although a typical power supply circuit is shown here, the power supply circuit used in the present invention is not limited to FIG. 8 and may be another type of circuit.

1 includes a dynamic memory (DRAM), a static memory (SRAM), a ferroelectric memory (FeRAM), a mask ROM, a volatile memory (EPROM), and a nonvolatile memory (EEPROM). Can be used. However, when a dynamic memory is used, it is necessary to add a periodic refresh function.

With the above structure, the semiconductor device capable of communicating data by wireless communication according to the present invention prevents malfunctions such as malfunction and non-response than conventional semiconductor devices, and accurately transmits information stored in the memory circuit. be able to.

Note that this embodiment mode can be freely combined with any of the other embodiments and embodiment modes in this specification.
(Embodiment 2)

In the second embodiment, a configuration of a ring oscillator different from the above embodiment will be described.

FIG. 9 shows a circuit diagram in the case where a capacitor serving as a load is added to each stage of the inverter constituting the ring oscillator in the first embodiment shown in FIG.

In FIG. 9, a ring oscillator 901 includes an N-channel transistor 902 and a P-channel transistor 903 connected in series, and an inverter configuration in which the gates of these two transistors are connected. A load configuration in which the gate terminals of the MOS transistor 904 and the P-channel type MOS transistor 905 are connected, and a combination of the inverter and the load as a unit. The plurality of inverters have a loop structure in which a rear-stage input terminal and a front-stage output terminal are connected, and a final-stage output terminal is connected to a first-stage input terminal. In order to oscillate a signal from the oscillation circuit with respect to the number of inverters in this loop, it is necessary to be composed of an odd number of inverters. In FIG. 9, the ring oscillator 901 has a five-stage configuration (5 units), but is not limited to this. The frequency of the oscillation signal obtained from the ring oscillator is determined by the characteristics of each inverter, the power supply voltage value, and the number of stages. Therefore, the number of inverter stages included in the ring oscillator is determined after comprehensively considering these factors.

The difference from the configuration of the ring oscillator of FIG. 4 shown in the first embodiment is that, in addition to the basic configuration in which inverters are connected in series in a loop shape, the source terminal and drain terminal of a MOS transistor are connected to form a gate terminal. The point is that a MOS transistor 904 and a MOS transistor 905 having a capacitance between them are added to each stage.

In FIG. 9, MOS capacitors in the MOS transistor 904 and the MOS transistor 905 added as a configuration different from that in FIG. 4 form a large capacitance between the gate terminal and the channel when the channel is formed. In this embodiment, it is used as a load for each stage of the inverter.

9, one of the MOS capacitors in the MOS transistor 904 and the MOS transistor 905 added as a configuration different from that in FIG. 1 is connected to the node of the ring oscillator, and the voltage applied to the other terminal 906 and the terminal 907 is controlled. By doing so, the load capacity can be increased or decreased. As a result, the signal propagation delay of the inverter can be increased or decreased.

In the present embodiment, not limited to the MOS capacitor, any element can be used as long as it can connect an element whose capacity changes and change the oscillation frequency of the ring oscillator. FIG. 10 is a diagram showing a configuration in which a variable capacitor is provided instead of the MOS capacitor. 10 is different from FIG. 9 in that a variable capacitance element 5001 is provided instead of the MOS transistor 904 and the MOS transistor 905 for obtaining the MOS capacitance. The variable capacitance element 5001 is an element whose capacitance is varied by a voltage input from one terminal 5002 of the variable capacitance element.

In addition, by connecting a MOS capacitor to each stage of the inverter constituting the ring oscillator as shown in FIG. 9, or by connecting a variable capacitance element to each stage of the inverter constituting the ring oscillator as shown in FIG. It is possible to increase or decrease the oscillation frequency of the ring oscillator in a plurality of stages. By adopting such a configuration, it becomes possible to control the oscillation frequency of the ring oscillator, and the influence of the characteristic variation of each element constituting the circuit can be canceled.

That is, by adopting the configuration of the ring oscillator of this embodiment, it is possible to prevent malfunctions such as malfunction and no response, which are the effects of the configuration shown in Embodiment 1, and to accurately store information stored in the memory circuit. In addition to transmission, a semiconductor device capable of controlling the oscillation frequency can be provided.

  Note that this embodiment mode can be freely combined with any of the other embodiments and embodiment modes in this specification.

In recent years, a small semiconductor device (hereinafter referred to as a wireless chip) combining an ultra-small IC chip and an antenna for wireless communication has attracted attention. The wireless chip can write and read data by transmitting and receiving a communication signal (operation magnetic field) using a wireless communication device (hereinafter referred to as a reader / writer).

As an application field of the wireless chip, for example, merchandise management in the distribution industry can be cited. At present, merchandise management using bar codes and the like is the mainstream, but since bar codes are optically read, data cannot be read if there is a shield. On the other hand, since the wireless chip reads data wirelessly, it can be read even if there is a shielding object. Accordingly, it is expected to improve the efficiency of product management and cost reduction. In addition, a wide range of applications such as boarding tickets, air passenger tickets, and automatic payment of fare are expected.

As the application field of wireless chips is expanding, the demand for higher-performance wireless chips is also increasing. For example, it is expected to prevent data leakage to a third party by encrypting transmission / reception data. For this, a method of processing the decryption / encryption process by hardware, a method of processing by software, and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit is configured by a dedicated circuit that performs decryption / encryption. In the method of processing in software, an arithmetic circuit is constituted by a CPU (Central Processing Unit) and a large-scale memory, and a decryption / encryption program is executed by the CPU. In the method using both hardware and software, the dedicated circuit, CPU, and memory constitute an arithmetic circuit, and the dedicated circuit performs a part of the decryption / encryption arithmetic processing, and the remaining arithmetic processing program is executed. Run on the CPU. In any case, it is required to mount a large-capacity memory on the wireless chip. By applying the present invention, it is possible to prevent malfunction caused by generation of a clock signal and malfunction such as no response, and to accurately transmit information stored in the memory circuit.

In this embodiment, as an example of a semiconductor device in the present invention, a wireless chip having a cryptographic processing function will be described with reference to FIGS. FIG. 22 is a block diagram of the wireless chip, and FIG. 23 is a layout diagram of the wireless chip.

First, the block configuration of the wireless chip will be described with reference to FIG. In FIG. 22, a wireless chip 1001 includes an arithmetic circuit 1006 including a CPU 1002, a ROM 1003, a RAM 1004, and a controller 1005, an antenna 1007, a resonance circuit 1008, a power supply circuit 1009, a reset circuit 1010, and a clock generation. The analog section 1015 includes a circuit 1011, a demodulation circuit 1012, a modulation circuit 1013, and a power management circuit 1014. The controller 1005 includes a CPU interface (CPUIF) 1016, a control register 1017, a code extraction circuit 1018, and an encoding circuit 1019. Note that in FIG. 22, for simplification of description, the communication signal is divided into a reception signal 1020 and a transmission signal 1021, but in reality, both are integrated signals, and the wireless chip 1001 and Data are simultaneously transmitted and received between the reader / writer. Received signal 1020 is received by antenna 1007 and resonant circuit 1008, and then demodulated by demodulation circuit 1012. The transmission signal 1021 is modulated by the modulation circuit 1013 and then transmitted from the antenna 1007.

In FIG. 22, when the wireless chip 1001 is placed in a magnetic field formed by a communication signal, an induced electromotive force is generated by the antenna 1007 and the resonance circuit 1008. The induced electromotive force is held by the electric capacity in the power supply circuit 1009, the potential is stabilized by the electric capacity, and is supplied to each circuit of the wireless chip 1001 as a power supply voltage. The reset circuit 1010 generates an initial reset signal for the entire wireless chip 1001. For example, a signal that rises after a rise in the power supply voltage is generated as a reset signal. The clock generation circuit 1011 changes the frequency and duty ratio of the clock signal in accordance with the control signal generated by the power management circuit 1014. The demodulation circuit 1012 detects the fluctuation of the amplitude of the ASK reception signal 1020 as the reception data 1022 of “0” / “1”. The demodulation circuit 1012 is a low-pass filter, for example. Further, the modulation circuit 1013 transmits the transmission data by changing the amplitude of the ASK transmission signal 1021. For example, when the transmission data 1023 is “0”, the resonance point of the resonance circuit 1008 is changed, and the amplitude of the communication signal is changed. The power management circuit 1014 monitors the power supply voltage supplied from the power supply circuit 1009 to the arithmetic circuit 1006 or the current consumption in the arithmetic circuit 1006, and the clock generation circuit 1011 controls the control signal for changing the frequency and duty ratio of the clock signal. Is generated.

The operation of the wireless chip in this embodiment will be described. First, the wireless chip 1001 receives a reception signal 1020 including ciphertext data from a reader / writer. The received signal 1020 is demodulated by the demodulation circuit 1012, decomposed into a control command, ciphertext data, and the like by the code extraction circuit 1018 and stored in the control register 1017. Here, the control command is data specifying a response of the wireless chip 1001. For example, transmission of a unique ID number, operation stop, and decryption are designated. Here, it is assumed that a decryption control command is received.

Subsequently, in the arithmetic circuit 1006, the CPU 1002 decrypts (decrypts) the ciphertext using the secret key 1024 stored in advance in the ROM 1003 in accordance with the decryption program stored in the ROM 1003. The decrypted ciphertext (decrypted text) is stored in the control register 1017. At this time, the RAM 1004 is used as a data storage area. Note that the CPU 1002 accesses the ROM 1003, the RAM 1004, and the control register 1017 via the CPU interface 1016. The CPU interface 1016 has a function of generating an access signal for any one of the ROM 1003, the RAM 1004, and the control register 1017 from an address requested by the CPU 1002.

Finally, in the encoding circuit 1019, transmission data 1023 is generated from the decoded text, modulated by the modulation circuit 1013, and the transmission signal 1021 is transmitted from the antenna 1007 to the reader / writer.

In this embodiment, as a calculation method, a method of processing by software, that is, a method of configuring a calculation circuit with a CPU and a large-scale memory and executing a program by the CPU has been described. It is also possible to select an appropriate calculation method and configure based on the method. For example, as a calculation method, other methods such as a method of processing the operation in hardware and a method of using both hardware and software are conceivable. In the method of processing in hardware, an arithmetic circuit may be configured with a dedicated circuit. In the method using both hardware and software, a dedicated circuit, a CPU, and a memory constitute an arithmetic circuit, a part of the arithmetic processing is performed by the dedicated circuit, and the remaining arithmetic processing program is executed by the CPU. .

Next, the layout configuration of the wireless chip will be described with reference to FIG. Note that, in FIG. 23, parts corresponding to those in FIG.

In FIG. 23, an FPC pad 1107 is an electrode pad group used when an FPC (Flexible Print Circuit) is attached to the wireless chip 1001, and an antenna bump 1108 is an electrode pad to which an antenna (not shown) is attached. Note that when the antenna is attached, an excessive pressure may be applied to the antenna bump 1108. Therefore, it is desirable not to dispose a component such as a transistor under the antenna bump 1108.

The FPC pad 1107 is effective when used mainly for failure analysis. In the wireless chip, since the power supply voltage is obtained from the communication signal, for example, when a failure occurs in the antenna or the power supply circuit, the arithmetic circuit does not operate at all. For this reason, failure analysis becomes extremely difficult. However, the power supply voltage is supplied from the FPC to the wireless chip 1001 via the FPC pad 1107, and the arithmetic circuit is operated by inputting an arbitrary electric signal instead of the electric signal supplied from the antenna. Is possible. Therefore, failure analysis can be performed efficiently.

Furthermore, it is more effective to arrange the FPC pad 1107 so that measurement using a prober is possible. In other words, by arranging the electrode pads on the FPC pad 1107 in accordance with the pitch of the prober needle, measurement by the prober becomes possible. By using a prober, it is possible to reduce the number of steps for attaching an FPC during failure analysis. In addition, since measurement can be performed even when a plurality of wireless chips are formed on the substrate, the number of steps to be divided into individual wireless chips can be reduced. In addition, it is possible to perform a non-defective inspection of the wireless chip immediately before the step of attaching the antenna during mass production. Accordingly, defective products can be selected at an early stage of the process, so that production costs can be reduced.

  Note that this example can be freely combined with the description of the above embodiment modes. In other words, by applying the present invention, it is possible to provide a semiconductor device capable of preventing malfunction caused by generation of a clock signal or malfunction and not responding and transmitting information stored in the memory circuit accurately. .

In this embodiment, a method for manufacturing the wireless chip described in the above embodiment will be described. Each circuit included in the wireless chip according to the present invention can be manufactured using a thin film transistor. In this embodiment, a method for manufacturing a flexible wireless chip by forming a circuit included in a wireless chip with a thin film transistor and transferring the circuit from a substrate used for manufacturing the thin film transistor to a flexible substrate will be described.

In this embodiment, as a circuit forming a wireless chip, a p-channel TFT (also referred to as “pch-TFT”) and an n-channel TFT (also referred to as “Nch-TFT”) that constitute an inverter or the like, In addition, an antenna over a thin film transistor is typically shown. Hereinafter, a method for manufacturing a wireless chip will be described with reference to cross-sectional views illustrated in FIGS.

  First, a separation layer 1303 is formed over one surface of a substrate 1301 with an insulating film 1302 interposed therebetween, and then an insulating film 1304 functioning as a base film and a semiconductor film 1305 (for example, a film containing amorphous silicon) are stacked. It is formed (see FIG. 11A). Note that the insulating film 1302, the separation layer 1303, the insulating film 1304, and the amorphous semiconductor film 1305 can be formed successively.

  The substrate 1301 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate), a ceramic substrate, a semiconductor substrate such as a Si substrate, and the like. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate. Note that in this step, the separation layer 1303 is provided over the entire surface of the substrate 1301 with the insulating film 1302 interposed therebetween. However, if necessary, the separation layer 1303 is provided over the entire surface of the substrate 1301 and then selected by a photolithography method. It may be provided.

The insulating film 1302 and the insulating film 1304 are formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x>y> 0), silicon nitride oxide (SiN _x O _y ) by a CVD method, a sputtering method, or the like. ) (X>y> 0) or the like. For example, in the case where the insulating films 1302 and 1304 have a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. The insulating film 1302 functions as a blocking layer that prevents an impurity element from being mixed into the separation layer 1303 or an element formed thereon from the substrate 1301, and the insulating film 1304 is formed over the substrate 1301 and the separation layer 1303. It functions as a blocking layer that prevents an impurity element from entering the device. In this manner, by forming the insulating films 1302 and 1304 functioning as blocking layers, an alkali metal such as Na or alkaline earth metal from the substrate 1301 and an impurity element contained in the release layer from the release layer 1303 are formed thereon. It is possible to prevent an adverse effect on an element to be formed. Note that the insulating films 1302 and 1304 may be omitted when quartz is used for the substrate 1301.

For the separation layer 1303, a metal film, a stacked structure of a metal film and a metal oxide film, or the like can be used. As the metal film, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), An element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or a film made of an alloy material or compound material containing the element as a main component, or a single layer. Form. These materials can be formed by using various CVD methods such as a sputtering method and a plasma CVD method. A stacked structure of a metal film and a metal oxide film, after forming a metal film described above, a plasma treatment under an oxygen atmosphere or an N _{2 O} atmosphere, by performing heat treatment in an oxygen atmosphere or an N _{2 O} atmosphere The oxide or oxynitride of the metal film can be provided on the surface of the metal film. For example, in the case where a tungsten film is provided as a metal film by a sputtering method, a CVD method, or the like, a metal oxide film made of tungsten oxide can be formed on the tungsten film surface by performing plasma treatment on the tungsten film. In this case, the oxide of tungsten is represented by WOx, X is 2 to 3, X is 2 (WO ₂ ), X is 2.5 (W ₂ O ₅ ), and X is In the case of 2.75 (W ₄ O ₁₁ ), X is 3 (WO ₃ ), and the like. In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. In addition, for example, after a metal film (for example, tungsten) is formed, an insulating film such as silicon oxide (SiO ₂ ) is provided on the metal film by a sputtering method, and a metal oxide (for example, for example, Tungsten oxide) may be formed over tungsten. Further, as the plasma treatment, for example, the above-described high density plasma treatment may be performed. In addition to the metal oxide film, metal nitride or metal oxynitride may be used. In this case, plasma treatment or heat treatment may be performed on the metal film in a nitrogen atmosphere or a nitrogen and oxygen atmosphere.

  The amorphous semiconductor film 1305 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method, an LPCVD method, a plasma CVD method, or the like.

  Next, crystallization is performed by irradiating the amorphous semiconductor film 1305 with laser light. Note that the amorphous semiconductor film 1305 is crystallized by a combination of laser light irradiation, a thermal crystallization method using an RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. You may go. After that, the obtained crystalline semiconductor film is etched into a desired shape to form crystalline semiconductor films 1305a to 1305f, and a gate insulating film 1306 is formed so as to cover the semiconductor films 1305a to 1305f (FIG. 11 ( B)).

The gate insulating film 1306 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x>y> 0), silicon nitride oxide (SiN _x O _y ) (x >Y> 0) or the like. For example, in the case where the gate insulating film 1306 has a two-layer structure, a silicon oxynitride film may be formed as the first insulating film and a silicon nitride oxide film may be formed as the second insulating film. Alternatively, a silicon oxide film may be formed as the first insulating film, and a silicon nitride film may be formed as the second insulating film.

  An example of a manufacturing process of the crystalline semiconductor films 1305a to 1305f will be briefly described below. First, an amorphous semiconductor film with a thickness of 50 to 60 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element that promotes crystallization, is held on the amorphous semiconductor film, the amorphous semiconductor film is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor film. After that, laser light is irradiated and crystalline semiconductor films 1305a to 1305f are formed by using a photolithography method. Note that the amorphous semiconductor film may be crystallized only by laser light irradiation without performing thermal crystallization using a metal element that promotes crystallization.

As a laser oscillator used for crystallization, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. The laser beam that can be used here is a gas laser such as Ar laser, Kr laser, or excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants Examples of the medium include lasers, glass lasers, ruby lasers, alexandrite lasers, Ti: sapphire lasers, copper vapor lasers, and gold vapor lasers that are oscillated from one or more types. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of these fundamental waves, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec. Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta as a medium, a laser, Ar ion laser, or Ti: sapphire laser with one or more added as a medium should be continuously oscillated It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or higher, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

Alternatively, the gate insulating film 1306 may be formed by performing the above-described high-density plasma treatment on the semiconductor films 1305a to 1305f and oxidizing or nitriding the surface. For example, it is formed by plasma treatment in which a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide (NO ₂ ), ammonia, nitrogen, or hydrogen are introduced. When excitation of plasma in this case is performed by introducing microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

  By such treatment using high-density plasma, an insulating film with a thickness of 1 to 20 nm, typically 5 to 10 nm, is formed over the semiconductor film. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. Such high-density plasma treatment directly oxidizes (or nitrides) a semiconductor film (crystalline silicon or polycrystalline silicon), so that the thickness of the formed insulating film ideally has extremely small variation. can do. In addition, since oxidation is not strengthened even at the crystal grain boundaries of crystalline silicon, a very favorable state is obtained. That is, the surface of the semiconductor film is solid-phase oxidized by the high-density plasma treatment shown here, thereby forming an insulating film with good uniformity and low interface state density without causing an abnormal oxidation reaction at the grain boundaries. can do.

  As the gate insulating film, only an insulating film formed by high-density plasma treatment may be used, or an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride is deposited by a CVD method using plasma or thermal reaction. , May be laminated. In any case, a transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

  Further, the semiconductor films 1305a to 1305f obtained by scanning and crystallizing in one direction while irradiating the semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or more are provided in the scanning direction of the beam. There is a characteristic that crystals grow. By arranging the transistors in accordance with the scanning direction in the channel length direction (the direction in which carriers flow when the channel formation region is formed) and combining the gate insulating film, characteristic variation is small and field effect mobility is reduced. A high thin film transistor (TFT) can be obtained.

  Next, a first conductive film and a second conductive film are stacked over the gate insulating film 1306. Here, the first conductive film is formed with a thickness of 20 to 100 nm by a CVD method, a sputtering method, or the like. The second conductive film is formed with a thickness of 100 to 400 nm. The first conductive film and the second conductive film include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like or an alloy material or a compound material containing these elements as a main component. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive film and the second conductive film include a tantalum nitride film and a tungsten film, a tungsten nitride film and a tungsten film, a molybdenum nitride film and a molybdenum film, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the first conductive film and the second conductive film are formed. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.

  Next, a resist mask is formed using a photolithography method, and an etching process for forming a gate electrode and a gate line is performed, so that a gate electrode 1307 is formed over the semiconductor films 1305a to 1305f. Here, an example in which the gate electrode 1307 has a stacked structure of a first conductive film 1307a and a second conductive film 1307b is shown.

Next, an impurity element imparting n-type conductivity is added to the semiconductor films 1305a to 1305f at a low concentration by ion doping or ion implantation using the gate electrode 1307 as a mask, and then a resist mask is formed by photolithography. An impurity element which is selectively formed and imparts p-type conductivity is added at a high concentration. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as an impurity element imparting n-type conductivity, and is selectively introduced into the semiconductor films 1305a to 1305f so as to be included at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ^3. An impurity region 1308 indicating a mold is formed. Further, boron (B) is used as an impurity element imparting p-type, and is selectively introduced into the semiconductor films 1305c and 1305e so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. An impurity region 1309 is formed (see FIG. 11C).

  Subsequently, an insulating film is formed so as to cover the gate insulating film 1306 and the gate electrode 1307. As the insulating film, a single layer or a stacked layer of a film containing an inorganic material such as silicon, a silicon oxide, or a silicon nitride, or a film containing an organic material such as an organic resin, by a plasma CVD method, a sputtering method, or the like. Form. Next, the insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that an insulating film 1310 (also referred to as a sidewall) in contact with the side surface of the gate electrode 1307 is formed. The insulating film 1310 is used as a mask for doping when forming an LDD (Lightly Doped Drain) region.

Subsequently, an impurity element imparting n-type conductivity is added to the semiconductor films 1305a, 1305b, 1305d, and 1305f at a high concentration using a resist mask formed by a photolithography method, the gate electrode 1307, and the insulating film 1310 as masks. Thus, an n-type impurity region 1311 is formed. Here, phosphorus (P) is used as an impurity element imparting n-type conductivity, and the semiconductor films 1305a, 1305b, 1305d, and 1305f are selectively used so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Then, an impurity region 1311 having an n type concentration higher than that of the impurity region 1308 is formed.

  Through the above steps, n-channel thin film transistors 1300a, 1300b, 1300d, and 1300f and p-channel thin film transistors 1300c and 1300e are formed (see FIG. 11D).

  In the n-channel thin film transistor 1300a, a channel formation region is formed in a region of the semiconductor film 1305a overlapping with the gate electrode 1307, and an impurity region 1311 forming a source region or a drain region is formed in a region not overlapping with the gate electrode 1307 and the insulating film 1310. In addition, a low-concentration impurity region (LDD region) is formed between the channel formation region and the impurity region 1311, which overlaps with the insulating film 1310. Similarly, channel formation regions, low-concentration impurity regions, and impurity regions 1311 are also formed in the n-channel thin film transistors 1300b, 1300d, and 1300f.

  In the p-channel thin film transistor 1300c, a channel formation region is formed in a region of the semiconductor film 1305c overlapping with the gate electrode 1307, and an impurity region 1309 forming a source region or a drain region is formed in a region not overlapping with the gate electrode 1307. Similarly, the channel formation region and the impurity region 1309 are formed in the p-channel thin film transistor 1300e. Note that although the LDD region is not provided in the p-channel thin film transistors 1300c and 1300e here, an LDD region may be provided in the p-channel thin film transistor, or an LDD region may not be provided in the n-channel thin film transistor. Good.

  Next, an insulating film is formed as a single layer or a stacked layer so as to cover the semiconductor films 1305a to 1305f, the gate electrode 1307, and the like, and an impurity region for forming a source region or a drain region of the thin film transistors 1300a to 1300f on the insulating film A conductive film 1313 which is electrically connected to 1309 and 1311 is formed (see FIG. 12A). Insulating film is formed by CVD, sputtering, SOG, droplet discharge, screen printing, etc., inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, etc. A single layer or a stacked layer is formed using an organic material, a siloxane material, or the like. Here, the insulating film is provided in two layers, and a silicon nitride oxide film is formed as the first insulating film 1312a, and a silicon oxynitride film is formed as the second insulating film 1312b. The conductive film 1313 can form a source electrode or a drain electrode of the thin film transistors 1300a to 1300f.

  Note that before the insulating films 1312a and 1312b are formed or after one or more thin films of the insulating films 1312a and 1312b are formed, the crystallinity of the semiconductor film is restored and the activity of the impurity element added to the semiconductor film is increased. Heat treatment for the purpose of hydrogenation of the semiconductor film is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  The conductive film 1313 is formed by a CVD method, a sputtering method, or the like by aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper ( Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. For the conductive film 1313, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film may be employed. . Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive film 1313 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

  Next, an insulating film 1314 is formed so as to cover the conductive film 1313, and conductive films that are electrically connected to the conductive film 1313 that forms source and drain electrodes of the thin film transistors 1300 a and 1300 f over the insulating film 1314, respectively. 1315a and 1315b are formed. In addition, a conductive film 1316 that is electrically connected to the conductive film 1313 that forms the source electrode or the drain electrode of the thin film transistors 1300b and 1300e is formed. Note that the conductive films 1315a and 1315b and the conductive film 1316 may be formed using the same material at the same time. The conductive films 1315a and 1315b and the conductive film 1316 can be formed using any of the materials described for the conductive film 1313.

  Next, a conductive film 1317 functioning as an antenna is formed so as to be electrically connected to the conductive film 1316 (see FIG. 12B).

The insulating film 1314 is formed by silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) by CVD or sputtering. ) (X> y) or other insulating film having oxygen or nitrogen, or a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane resin It can be provided in a single layer or laminated structure made of a siloxane material such as. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The conductive film 1317 is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when the conductive film 1317 that functions as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin is selected. Can be provided by printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins functioning as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicon resin can be given. In forming the conductive film, it is preferable to fire after extruding the conductive paste. For example, when fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) are used as a conductive paste material, the conductive film is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

  In addition, the conductive films 1315a and 1315b can function as wirings that are electrically connected to a battery included in the semiconductor device of the present invention in a later step. Further, when the conductive film 1317 functioning as an antenna is formed, a separate conductive film may be formed so as to be electrically connected to the conductive films 1315a and 1315b, and the conductive film may be used as wiring for connecting to the battery. .

Next, after an insulating film 1318 is formed so as to cover the conductive film 1317, a layer including the thin film transistors 1300 a to 1300 f, the conductive film 1317, and the like (hereinafter referred to as “element formation layer 1319”) is peeled from the substrate 1301. Here, after an opening is formed in a region avoiding the thin film transistors 1300a to 1300f by irradiating laser light (for example, UV light) (see FIG. 12C), the element is removed from the substrate 1301 using physical force. The formation layer 1319 can be peeled off. Alternatively, before the element formation layer 1319 is peeled from the substrate 1301, an etching agent may be introduced into the formed opening to selectively remove the peeling layer 1303. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the element formation layer 1319 is peeled from the substrate 1301. Note that a part of the peeling layer 1303 may be left without being removed. By doing so, it is possible to suppress the consumption of the etching agent and shorten the processing time required for removing the release layer. Further, the element formation layer 1319 can be held over the substrate 1301 even after the peeling layer 1303 is removed. In addition, cost can be reduced by reusing the substrate 1301 from which the element formation layer 1319 is peeled.

The insulating film 1318 is formed by silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x O _y ) by CVD or sputtering. ) (X> y) or other insulating film having oxygen or nitrogen, or a film containing carbon such as DLC (Diamond Like Carbon), an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, or acrylic, or a siloxane resin It can be provided in a single layer or laminated structure made of a siloxane material such as.

  In this embodiment, after an opening is formed in the element formation layer 1319 by laser light irradiation, the first sheet material 1320 is bonded to one surface of the element formation layer 1319 (the surface where the insulating film 1318 is exposed). The element formation layer 1319 is peeled from the substrate 1301 (see FIG. 13A).

  Next, the second sheet material 1321 is attached to the other surface (the surface exposed by peeling) of the element formation layer 1319, and then one or both of heat treatment and pressure treatment are performed to form the first sheet material. 1320 is attached (see FIG. 13B). As the first sheet material 1320 and the second sheet material 1321, a hot melt film or the like can be used.

  In addition, as the first sheet material 1320 and the second sheet material 1321, films provided with antistatic measures for preventing static electricity or the like (hereinafter referred to as antistatic films) can be used. Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film on which an antistatic material is attached, and the like. The film provided with an antistatic material may be a film provided with an antistatic material on one side, or a film provided with an antistatic material on both sides. Furthermore, a film provided with an antistatic material on one side may be attached to the layer so that the surface provided with the antistatic material is on the inside of the film, or on the outside of the film. It may be pasted. Note that the antistatic material may be provided on the entire surface or a part of the film. As the antistatic material here, surfactants such as metals, oxides of indium and tin (ITO), amphoteric surfactants, cationic surfactants and nonionic surfactants can be used. . In addition, as the antistatic material, a resin material containing a crosslinkable copolymer polymer having a carboxyl group and a quaternary ammonium base in the side chain can be used. An antistatic film can be obtained by sticking, kneading, or applying these materials to a film. By sealing with an antistatic film, it is possible to prevent the semiconductor element from being adversely affected by external static electricity or the like when handled as a product.

  Note that this example can be freely combined with the description of the above embodiment modes. In other words, by applying the present invention, it is possible to provide a semiconductor device capable of preventing malfunction caused by generation of a clock signal or malfunction and not responding and transmitting information stored in the memory circuit accurately. .

  In this embodiment, a method for manufacturing a wireless chip, which is different from that in the above embodiment, will be described. The transistor in the present invention can be composed of a MOS transistor formed on a single crystal substrate in addition to the thin film transistor formed on the insulating substrate described in the above embodiment.

In this embodiment, a p-channel TFT (also referred to as “Pch-TFT”) and an n-channel TFT (also referred to as “Nch-TFT”) that constitute an inverter or the like are used as circuits constituting the wireless chip. Representatively shown. Hereinafter, a method for manufacturing a wireless chip will be described with reference to cross-sectional views illustrated in FIGS.

  First, regions 2304 and 2306 (hereinafter also referred to as regions 2304 and 2306) in which elements are separated are formed in a semiconductor substrate 2300 (see FIG. 14A). The regions 2304 and 2306 provided in the semiconductor substrate 2300 are separated by an insulating film 2302 (also referred to as a field oxide film). Here, an example in which a single crystal Si substrate having n-type conductivity is used as the semiconductor substrate 2300 and a p-well 2307 is provided in a region 2306 of the semiconductor substrate 2300 is shown.

  The substrate 2300 can be used without any particular limitation as long as it is a semiconductor substrate. For example, a single crystal Si substrate having an n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by Implanted) An SOI (Silicon On Insulator) substrate or the like manufactured by an Oxygen method can be used.

  For the element isolation regions 2304 and 2306, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used as appropriate.

  The p-well formed in the region 2306 of the semiconductor substrate 2300 can be formed by selectively introducing an impurity element having p-type conductivity into the semiconductor substrate 2300. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Note that in this embodiment, since a semiconductor substrate having n-type conductivity is used as the semiconductor substrate 2300, no impurity element is introduced into the region 2304, but an impurity element exhibiting n-type is introduced. Thus, an n-well may be formed in the region 2304. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. On the other hand, when a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 2304 to form an n-well, and no impurity element is introduced into the region 2306. Good.

  Next, insulating films 2332 and 2334 are formed so as to cover the regions 2304 and 2306, respectively (see FIG. 14B).

  The insulating films 2332 and 2334 can be formed using a silicon oxide film, for example, by performing heat treatment to oxidize the surfaces of the regions 2304 and 2306 provided in the semiconductor substrate 2300. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, whereby the silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

In addition, as described above, the insulating films 2332 and 2334 may be formed by plasma treatment. For example, the surfaces of the regions 2304 and 2306 provided in the semiconductor substrate 2300 are subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, so that silicon oxide (SiO _x ) films or silicon nitride (SiN _x ) are formed as the insulating films 2332 and 2334. ) It can be formed with a film. Alternatively, the surface of the regions 2304 and 2306 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 2304 and 2306, a (silicon oxynitride film) is formed over the silicon oxide film, and the insulating films 2332 and 2334 are formed of a silicon oxide film and a silicon oxynitride film. Becomes a laminated film. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 2304 and 2306 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

In addition, the insulating films 2332 and 2334 formed in the regions 2304 and 2306 of the semiconductor substrate 2300 function as gate insulating films in transistors to be completed later.

  Next, a conductive film is formed so as to cover the insulating films 2332 and 2334 formed over the regions 2304 and 2306 (see FIG. 14C). Here, an example is shown in which a conductive film 2336 and a conductive film 2338 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 2336 and 2338 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 2336 is formed using tantalum nitride, and the conductive film 2338 is formed using tungsten in a stacked structure. In addition, a single layer or a stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used as the conductive film 2336, and a single layer or a stacked film selected from tantalum, molybdenum, or titanium is used as the conductive film 2338. Can be used.

  Next, the conductive films 2336 and 2338 provided in a stacked manner are selectively removed by etching, so that the conductive films 2336 and 2338 are left in portions above the regions 2304 and 2306, respectively. 2342 are formed (see FIG. 15A).

  Next, a resist mask 2348 is selectively formed so as to cover the region 2304, and an impurity element is formed by introducing an impurity element into the region 2306 using the resist mask 2348 and the gate electrode 2342 as masks (FIG. 15B )reference). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  In FIG. 15B, an impurity element 2352 for forming a source region or a drain region and a channel formation region 2350 are formed in the region 2306 by introducing an impurity element.

  Next, a resist mask 2366 is selectively formed so as to cover the region 2306, and an impurity element is introduced into the region 2304 using the resist mask 2366 and the gate electrode 2340 as masks (FIG. 15C )reference). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, an impurity element (eg, boron (B)) having a conductivity type different from that of the impurity element introduced into the region 2306 in FIG. 15C is introduced. As a result, an impurity region 2370 that forms a source region or a drain region and a channel formation region 2368 are formed in the region 2304.

  Next, a second insulating film 2372 is formed so as to cover the insulating films 2332 and 2334 and the gate electrodes 2340 and 2342, and impurity regions 2352 formed in regions 2304 and 2306 on the second insulating film 2372, respectively. A wiring 2374 electrically connected to 2370 is formed (see FIG. 16).

The second insulating film 2372 is formed by silicon oxide (SiO _x ), silicon nitride (SiNx), silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN _x ) by CVD or sputtering. O _y ) (x> y) or other insulating film containing oxygen or nitrogen, carbon containing film such as DLC (Diamond Like Carbon), organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or It can be provided in a single layer or a laminated structure made of a siloxane material such as a siloxane resin. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The wiring 2374 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu) by CVD or sputtering. ), Gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material or compound containing these elements as a main component The material is a single layer or a laminate. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. For the wiring 2374, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film may be employed. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are optimal materials for forming the wiring 2374 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

Note that the structure of the transistor constituting the semiconductor device of the present invention is not limited to the illustrated structure. For example, a transistor structure such as an inverted stagger structure or a fin FET structure can be employed. The fin FET structure is preferable because the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

  Note that this example can be freely combined with the description of the above embodiment modes. In other words, by applying the present invention, it is possible to provide a semiconductor device capable of preventing malfunction caused by generation of a clock signal or malfunction and not responding and transmitting information stored in the memory circuit accurately. .

  In this embodiment, a method for manufacturing a wireless chip, which is different from that in the above embodiment, will be described. The transistor in the present invention can also be constituted by a MOS transistor provided by a different manufacturing method from the MOS transistor formed on the single crystal substrate described in the above embodiment.

In this embodiment, a p-channel TFT (also referred to as “pch-TFT”) and an n-channel TFT (also referred to as “Nch-TFT”) that constitute an inverter or the like are used as circuits constituting the wireless chip. Representatively shown. Hereinafter, a method for manufacturing a wireless chip will be described with reference to cross-sectional views illustrated in FIGS.

First, an insulating film is formed over the substrate 2600. Here, single crystal Si having n-type conductivity is used as the substrate 2600, and an insulating film 2602 and an insulating film 2604 are formed over the substrate 2600 (see FIG. 17A). For example, heat treatment is performed on the substrate 2600 to form silicon oxide (SiO _x ) as the insulating film 2602, and silicon nitride (SiN _x ) is formed over the insulating film 2602 by a CVD method.

  The substrate 2600 can be used without any particular limitation as long as it is a semiconductor substrate. For example, an n-type or p-type single crystal Si substrate, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by IMplanted) An SOI (Silicon on Insulator) substrate manufactured using an OXygen method or the like can be used.

  The insulating film 2604 may be provided by nitriding the insulating film 2602 by high-density plasma treatment after the insulating film 2602 is formed. Note that the insulating film provided over the substrate 2600 may be a single layer or a stacked structure including three or more layers.

  Next, a pattern of a resist mask 2606 is selectively formed over the insulating film 2604, and selective etching is performed using the resist mask 2606 as a mask, whereby a recess 2608 is selectively formed in the substrate 2600 (FIG. 17). (See (B)). Etching of the substrate 2600 and the insulating films 2602 and 2604 can be performed by dry etching using plasma.

  Next, after the pattern of the resist mask 2606 is removed, an insulating film 2610 is formed so as to fill the recess 2608 formed in the substrate 2600 (see FIG. 17C).

The insulating film 2610 is formed using silicon oxide, silicon nitride, silicon oxynitride (SiO _x N _y ) (x>y> 0), silicon nitride oxide (SiN _x O _y ) (x>) by a CVD method, a sputtering method, or the like. It is formed using an insulating material such as y> 0). Here, as the insulating film 2610, a silicon oxide film is formed using TEOS (tetraethylorthosilicate) gas by an atmospheric pressure CVD method or a low pressure CVD method.

  Next, the surface of the substrate 2600 is exposed by performing a grinding process, a polishing process, or a CMP (Chemical Mechanical Polishing) process. Here, regions 2612 and 2613 are provided between the insulating films 2611 formed in the recesses 2608 of the substrate 2600 by exposing the surface of the substrate 2600. Note that the insulating film 2611 is obtained by removing the insulating film 2610 formed over the surface of the substrate 2600 by grinding treatment, polishing treatment, or CMP treatment. Subsequently, an impurity element having p-type conductivity is selectively introduced to form a p-well 2615 in the regions 2613 and 2614 of the substrate 2600 (see FIG. 18A).

  As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the regions 2613 and 2614 as the impurity element.

  Note that in this embodiment, since a semiconductor substrate having n-type conductivity is used as the substrate 2600, no impurity element is introduced into the region 2612; however, by introducing an impurity element exhibiting n-type conductivity An n-well may be formed in the region 2612. As the impurity element exhibiting n-type, phosphorus (P), arsenic (As), or the like can be used.

  On the other hand, in the case where a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 2612 to form an n-well, and no impurity element is introduced into the regions 2613 and 2614. It is good.

  Next, insulating films 2632 and 2634 are formed over the surfaces of the regions 2612 and 2613 of the substrate 2600, respectively (see FIG. 18B).

  For example, the insulating films 2632 and 2634 can be formed using silicon oxide films by oxidizing the surfaces of the regions 2612 and 2613 provided in the substrate 2600 by performing heat treatment. In addition, after a silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing nitriding treatment, so that a silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) are stacked. You may form with a structure.

In addition, as described above, the insulating films 2632 and 2634 may be formed by plasma treatment. For example, the surface of the regions 2612 and 2613 provided in the substrate 2600 is subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, so that a silicon oxide (SiO _x ) film or silicon nitride (SiN _x ) is formed as the insulating films 2632 and 2634. It can be formed of a film. Alternatively, after the surface of the regions 2612 and 2613 is oxidized by high-density plasma treatment, nitriding treatment may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 2612 and 2613, a (silicon oxynitride film) is formed over the silicon oxide film, and the insulating films 2632 and 2634 are formed of a silicon oxide film and a silicon oxynitride film. Becomes a laminated film. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 2612 and 2613 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  Note that the insulating films 2632 and 2634 formed in the regions 2612 and 2613 of the substrate 2600 function as gate insulating films in transistors to be completed later.

  Next, a conductive film is formed so as to cover the insulating films 2632 and 2634 formed over the regions 2612 and 2613 provided in the substrate 2600 (see FIG. 18C). Here, an example is shown in which a conductive film 2636 and a conductive film 2638 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 2636 and 2638 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as main components. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 2636 is formed using tantalum nitride, and the conductive film 2638 is formed using tungsten in a stacked structure. In addition, the conductive film 2636 is a single layer or a stacked film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride, and the conductive film 2638 is selected from tungsten, tantalum, molybdenum, or titanium. A single layer or a laminated film can be used.

  Next, the conductive films 2636 and 2638 provided in a stacked manner are selectively removed by etching, whereby the conductive films 2636 and 2638 are left in portions above the regions 2612 and 2613 of the substrate 2600, respectively. Conductive films 2640 and 2642 functioning as electrodes are formed (see FIG. 19A). Here, in the substrate 2600, the surfaces of the regions 2612 and 2613 that do not overlap with the conductive films 2640 and 2642 are exposed.

  Specifically, in the region 2612 of the substrate 2600, a portion of the insulating film 2632 formed below the conductive film 2640 that does not overlap with the conductive film 2640 is selectively removed, so that the edges of the conductive film 2640 and the insulating film 2632 are removed. The parts are formed so as to roughly match. Further, in a region 2614 of the substrate 2600, a portion of the insulating film 2634 formed below the conductive film 2642 that does not overlap with the conductive film 2642 is selectively removed, so that end portions of the conductive film 2642 and the insulating film 2634 are roughly formed. Form to match.

  In this case, an insulating film or the like which does not overlap with the formation of the conductive films 2640 and 2642 may be removed, or the resist mask remaining after the formation of the conductive films 2640 and 2642 or the conductive films 2640 and 2642 may be used as a mask. A portion of the insulating film that does not become necessary may be removed.

  Next, an impurity element is selectively introduced into the regions 2612 and 2613 of the substrate 2600 (see FIG. 19B). Here, a low-concentration impurity element imparting n-type conductivity is selectively introduced into the region 2613 using the conductive film 2642 as a mask, and a low-concentration impurity element imparting p-type conductivity is selected into the region 2612 using the conductive film 2640 as a mask. Introduced. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Next, sidewalls 2654 that are in contact with the side surfaces of the conductive films 2640 and 2642 are formed. Specifically, a film including an inorganic material such as silicon, a silicon oxide, or a silicon nitride, or a film including an organic material such as an organic resin is stacked in a single layer or stacked by a plasma CVD method, a sputtering method, or the like. Form. Then, the insulating film can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 2640 and 2642. Note that the sidewall 2654 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed. Further, here, the sidewall 2654 is formed so as to be in contact with an insulating film or a side surface of the gate electrode formed below the conductive films 2640 and 2642.

  Subsequently, an impurity element functioning as a source region or a drain region is formed by introducing an impurity element into the regions 2612 and 2613 of the substrate 2600 using the sidewalls 2654 and the conductive films 2640 and 2642 as masks (FIG. 19C )reference). Here, an impurity element imparting high concentration n-type is introduced into the region 2613 of the substrate 2600 using the sidewall 2654 and the conductive film 2642 as a mask, and a high concentration p is applied to the region 2612 using the sidewall 2654 and the conductive film 2640 as a mask. Impurity elements that impart molds are introduced.

  As a result, an impurity region 2658 that forms a source region or a drain region, a low-concentration impurity region 2660 that forms an LDD region, and a channel formation region 2656 are formed in the region 2612 of the substrate 2600. In the region 2613 of the substrate 2600, an impurity region 2664 that forms a source region or a drain region, a low-concentration impurity region 2666 that forms an LDD region, and a channel formation region 2662 are formed.

  Note that in this embodiment, the impurity element is introduced in a state where the regions 2612 and 2613 of the substrate 2600 which do not overlap with the conductive films 2640 and 2642 are exposed. Accordingly, channel formation regions 2656 and 2662 formed in the regions 2612 and 2613 of the substrate 2600 can be formed in self-alignment with the conductive films 2640 and 2642, respectively.

  Next, a second insulating film 2677 is formed so as to cover insulating films, conductive films, and the like provided over the regions 2612 and 2613 of the substrate 2600, and an opening 2678 is formed in the insulating film 2677 (FIG. A)).

The second insulating film 2677 is formed by silicon oxide (SiO _x ), silicon nitride (SiN _x ), silicon oxynitride (SiO _x N _y ) (x> y), silicon nitride oxide (SiN) by a CVD method, a sputtering method, or the like. _{x O y) (x> y} ) such as oxygen or an insulating film or a DLC (diamond like carbon) or the like film containing carbon as epoxy, polyimide, polyamide, polyvinyl phenol, benzocyclobutene, an organic material such as acrylic Alternatively, a single layer or a stacked structure including a siloxane material such as a siloxane resin can be used. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, a conductive film 2680 is formed in the opening 2678 using a CVD method, and conductive films 2682a to 2682d are selectively formed over the insulating film 2677 so as to be electrically connected to the conductive film 2680 (FIG. 20). (See (B)).

  The conductive films 2680 and 2682a to 2682d are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) by CVD or sputtering. ), Copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements as main components An alloy material or a compound material to be formed is a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive films 2680 and 2682a to 2682d include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, and a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Should be adopted. Note that the barrier film corresponds to a thin film formed of titanium, titanium nitride, molybdenum, or molybdenum nitride. Aluminum and aluminum silicon are suitable materials for forming the conductive film 2680 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made. Here, the conductive film 2680 can be formed by selectively growing tungsten (W) by a CVD method.

  Through the above steps, a semiconductor device including a p-type transistor formed in the region 2612 of the substrate 2600 and an n-type transistor formed in the region 2613 can be obtained.

Note that the structure of the transistor constituting the semiconductor device of the present invention is not limited to the illustrated structure. For example, a transistor structure such as an inverted stagger structure or a fin FET structure can be employed. The fin FET structure is preferable because the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

  Note that this example can be freely combined with the description of the above embodiment modes. In other words, by applying the present invention, it is possible to provide a semiconductor device capable of preventing malfunction caused by generation of a clock signal or malfunction and not responding and transmitting information stored in the memory circuit accurately. .

A method of using the semiconductor device 3000 functioning as the wireless chip described in the above embodiment will be described with reference to FIG.

Applications of wireless chips are wide-ranging. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, resident's card, etc., see FIG. 21A), packaging containers (wrapping paper, Bottle, etc., see FIG. 21C), recording medium (DVD software, video tape, etc., see FIG. 21B), vehicles (bicycle, etc., see FIG. 21D), personal items (bags, glasses, etc.) ), Used for goods such as foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and luggage tags (see FIGS. 21E and 21F). be able to. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like.

The semiconductor device 3000 of the present invention has the memory element of the present invention, and is fixed to an article by being mounted on a printed board, pasted on a surface, or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. Since the semiconductor device 3000 of the present invention is small, thin, and lightweight, the design itself of the article itself is not impaired even after being fixed to the article. In addition, by providing the semiconductor device 3000 of the present invention on bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and if this authentication function is utilized, forgery can be prevented. Can do. Further, by attaching the semiconductor device of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of a system such as an inspection system can be improved.

  Note that this embodiment can be freely combined with the above embodiment mode. That is, in the memory mounted on the semiconductor device, each bit line can be selectively precharged. In other words, a semiconductor device equipped with a memory with low power consumption can be provided by not precharging bit lines that are not related to reading data from the memory.

The figure explaining the structure of Embodiment 1 of this invention. The figure explaining the conventional structure. The figure explaining the structure of the conventional PLL. The figure explaining the operation | movement of the conventional PLL. The figure which shows the specific structure of a ring oscillator. 3A and 3B illustrate flip-flops included in a frequency divider. The figure explaining operation | movement of a ring oscillator and a frequency divider. The figure which shows the specific structural example of a power supply circuit. The figure shown about the structure of Embodiment 2 of this invention. The figure shown about the structure of Embodiment 2 of this invention. The figure shown about the structure of Example 2 using this invention. The figure shown about the structure of Example 2 using this invention. The figure shown about the structure of Example 2 using this invention. The figure shown about the structure of Example 3 using this invention. The figure shown about the structure of Example 3 using this invention. The figure shown about the structure of Example 3 using this invention. The figure shown about the structure of Example 4 using this invention. The figure shown about the structure of Example 4 using this invention. The figure shown about the structure of Example 4 using this invention. The figure shown about the structure of Example 4 using this invention. The figure shown about the structure of Example 5 using this invention. The figure shown about the structure of Example 1 using this invention. The figure shown about the structure of Example 1 using this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Semiconductor device 102 Antenna 103 High frequency circuit 104 Power supply circuit 105 Reset circuit 106 Clock generation circuit 107 Data demodulation circuit 108 Data modulation circuit 109 Control circuit 110 Memory circuit 111 Semiconductor integrated circuit 112 Ring oscillator 113 Frequency divider 201 Semiconductor device 202 Antenna 203 High frequency Circuit 204 Power supply circuit 205 Reset circuit 206 Clock generation circuit 207 Data demodulation circuit 208 Data modulation circuit 209 Control circuit 210 Memory circuit 211 Semiconductor integrated circuit 301 Phase comparator 302 Loop filter 303 Voltage controlled oscillator 304 Frequency divider 401 Waveform 402 Waveform 403 Period 404 Period 501 Ring oscillator 502 N-channel transistor 503 P-channel transistor 601 Flip-flop 602 Invar NAND circuit 603 NAND circuit 604 NAND circuit 605 NAND circuit 607 NAND circuit 608 NAND circuit 609 NAND circuit 610 inverter circuit 701 waveform 702 period 703 waveform 704 waveform 705 waveform 801 transistor 812 resistor 813 output terminal 901 ring oscillator 902 N channel type Transistor 903 P-channel transistor 904 MOS transistor 905 MOS transistor 906 Terminal 907 Terminal 1001 Wireless chip 1002 CPU
1003 ROM
1004 RAM
1005 Controller 1006 Arithmetic circuit 1007 Antenna 1008 Resonance circuit 1009 Power supply circuit 1010 Reset circuit 1011 Clock generation circuit 1012 Demodulation circuit 1013 Modulation circuit 1014 Power management circuit 1015 Analog unit 1016 CPU interface 1017 Control register 1018 Code extraction circuit 1019 Encoding circuit 1020 Receive signal 1021 Transmission signal 1022 Reception data 1023 Transmission data 1024 Secret key 1107 FPC pad 1108 Antenna bump 1301 Substrate 1302 Insulating film 1303 Release layer 1304 Insulating film 1305 Semiconductor film 1306 Gate insulating film 1307 Gate electrode 1308 Impurity region 1309 Impurity region 1310 Insulating film 1311 Impurity Region 1313 Conductive film 1314 Insulating film 1316 Conductive film 1317 Conductive Film 1318 Insulating film 1319 Element forming layer 1320 Sheet material 1321 Sheet material 2300 Substrate 2302 Insulating film 2304 Region 2306 Region 2307 p-well 2332 Insulating film 2336 Conductive film 2338 Conductive film 2340 Gate electrode 2342 Gate electrode 2348 Resist mask 2350 Channel formation region 2352 Impurity Region 2366 Resist mask 2368 Channel formation region 2370 Impurity region 2372 Insulating film 2374 Wiring 2600 Substrate 2602 Insulating film 2604 Insulating film 2606 Resist mask 2608 Recess 2610 Insulating film 2611 Insulating film 2612 Region 2613 Region 2614 Region 2615 P well 2632 Insulating film 2634 Insulating film 2636 conductive film 2638 conductive film 2640 conductive film 2642 conductive film 2654 sidewall 2656 channel Formation region 2658 Impurity region 2660 Low concentration impurity region 2662 Channel formation region 2664 Impurity region 2666 Low concentration impurity region 2677 Insulating film 2678 Opening 2680 Conductive film 3000 Semiconductor device 5001 Variable capacitor 5002 Terminal 1300a Thin film transistor 1300b Thin film transistor 1300c Thin film transistor 1300e Thin film transistor 1305a Semiconductor Film 1305c Semiconductor film 1307a Conductive film 1307b Conductive film 1312a Insulating film 1312b Insulating film 1315a Conductive film 2682a Conductive film

Claims (1)

An antenna circuit for receiving a radio signal;
A power supply circuit that generates power by the wireless signal received by the antenna circuit;
A clock generation circuit to which the power is supplied,
The clock generation circuit includes:
A ring oscillator for oscillating a signal with a constant period;
A frequency divider for dividing the signal output from the ring oscillator;
A control circuit to which a clock signal output from the frequency divider is supplied;
The ring oscillator can oscillate the clock signal by power supplied from the power circuit,
The ring oscillator is
An odd number of inverters, a plurality of first N-channel MOS transistors, and a plurality of first P-channel MOS transistors,
The output terminal of the final stage inverter of an odd number of stages of inverters are connected the input terminal and electrically of the first-stage inverter,
The output terminals of the inverters other than the final stage are electrically connected to the input terminal of the subsequent inverter, the gate of the first N-channel MOS transistor, and the gate of the first P-channel MOS transistor. ,
The input terminals of the inverters other than the first stage are electrically connected to the output terminal of the previous stage inverter, the gate of the first N-channel type MOS transistor, and the gate of the first P-channel type MOS transistor,
It said inverter includes a MOS transistor and a second P-channel type MOS transistor of the second N-channel type,
One of the source and the drain of the second N-channel MOS transistor is electrically connected to the first power line,
One of a source and a drain of the second P-channel MOS transistor is electrically connected to a second power supply line,
The source of the first N-channel type MOS transistor has a drain of said first N-channel type MOS transistor is connected to the first terminal and electrically,
The source of the first P-channel type MOS transistor, a semiconductor characterized by comprising: the drain of said first P-channel type MOS transistor, to be connected to the second terminal and electrically apparatus.

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