JP5346459B2 - Oscillation circuit and semiconductor device including the same - Google Patents

Description

  The present invention relates to an oscillation circuit and a semiconductor device including the oscillation circuit.

  In recent years, development of semiconductor devices in which various circuits are integrated on the same insulating surface has been promoted, and various oscillation circuits are known as clock circuits necessary for the circuits.

The oscillation circuit has been developed using CMOS, and a typical example is an oscillation circuit using a CMOS inverter (see, for example, Patent Document 1).
JP 2003-283307 A

  However, the conventional oscillation circuit has the following problems. When the power supply voltage supplied to the oscillation circuit varies, the value of the current flowing through the inverter changes, and the oscillation frequency changes. For this reason, when the output from the oscillation circuit is used as a clock signal, the clock signal fluctuates when the oscillation frequency changes, resulting in malfunction of the circuit.

  In addition, in recent years, in an RFID (Radio Frequency Identification) tag that has been attracting attention as a semiconductor device that communicates data by wireless communication, when a power supply voltage is obtained using a radio signal such as an external radio wave or electromagnetic wave, The power supply voltage easily changes depending on the distance from the signal transmission point, and the change in the power supply voltage changes the oscillation frequency.

  In addition, the oscillation frequency is weak against power supply ripple and noise caused by radio signals, and is difficult to keep constant.

  In view of the above problems, an object of the present invention is to provide an oscillation circuit that suppresses a change in oscillation frequency with respect to fluctuations in power supply voltage and the like and outputs a signal with a more stable frequency, and a semiconductor device including the oscillation circuit. .

  One aspect of the present invention is a constant current circuit that allows a constant current to flow regardless of a potential difference between power supply voltage terminals, a voltage controlled oscillation circuit that changes an oscillation frequency according to a potential difference between power supply voltage terminals, an n-channel transistor, a p-channel An oscillation circuit having a type transistor and a capacitor. The power supply voltage terminal includes a first terminal and a second terminal, and the power supply voltage is supplied from these terminals.

  In the voltage controlled oscillation circuit having the above configuration, the oscillation frequency can be changed by the voltage at the input terminal when the potential difference between the power supply voltage terminals is constant. Note that when the voltage at the input terminal increases, the oscillation frequency increases, and when the voltage at the input terminal decreases, the oscillation frequency decreases. When the voltage at the input voltage terminal is constant, the oscillation frequency changes due to the potential difference between the power supply voltage terminals. In that case, when the potential difference between the power supply voltage terminals increases, the oscillation frequency decreases, and when the potential difference between the power supply voltage terminals decreases, the oscillation frequency increases.

  The constant current circuit and the gate electrode of the p-channel transistor are connected at the second node, and the source electrode of the p-channel transistor is connected to the first terminal. Note that a current corresponding to the current value of the constant current circuit can be supplied to the p-channel transistor.

  The drain electrode of the p-channel transistor and the drain electrode of the n-channel transistor are connected, and the source electrode of the n-channel transistor is connected to the second terminal. Note that a voltage is generated in the gate electrode of the n-channel transistor due to the current flowing in the p-channel transistor.

  The voltage-controlled oscillation circuit and the gate electrode of the n-channel transistor are connected at the first node, and the oscillation frequency of the voltage-controlled oscillation circuit is determined by the voltage generated at the gate electrode of the n-channel transistor. The first node is also connected to the second terminal via a capacitor. The first node corresponds to an input terminal in the voltage controlled oscillation circuit.

  When the potential difference between the power supply voltage terminals changes, the current flowing through the constant current circuit is constant. However, the current of the p-channel transistor connected to the constant current circuit varies depending on the drain-source voltage even when the gate-source voltage is constant. When the current of the p-channel transistor changes, the gate terminal voltage of the n-channel transistor changes.

  When the potential difference between the power supply voltage terminals changes and the input terminal of the voltage controlled oscillation circuit is constant, the oscillation frequency of the voltage controlled oscillation circuit varies depending on the potential difference between the power supply voltage terminals. Since the gate terminal voltage of the transistor changes, a change in oscillation frequency due to a potential difference between the power supply voltage terminals can be suppressed.

  Note that the capacitor connected to the first node can suppress a change in voltage at the first node when the potential difference between the power supply voltage terminals suddenly changes.

  According to one aspect of the present invention, a constant current circuit electrically connected between a first terminal and a second terminal, a voltage controlled oscillation circuit in which an oscillation frequency is changed by a potential difference between power supply voltage terminals, an n-channel A p-channel transistor whose gate-source voltage is constant by a constant current circuit, and a capacitor. One of the source electrode and the drain electrode of the p-channel transistor is electrically connected to the first terminal. The other of the source and drain electrodes of the p-channel transistor is electrically connected to one of the source and drain electrodes of the n-channel transistor and the gate electrode, and the source and drain electrodes of the n-channel transistor Is electrically connected to the second terminal, and the gate electrode of the n-channel transistor is connected to the second terminal via a capacitor. An oscillation circuit that is electrically connected to the terminal. Note that the first terminal and the second terminal correspond to a power supply voltage terminal in the voltage controlled oscillation circuit. Moreover, a resistor is not necessarily required for the constant current circuit.

  Another aspect of the present invention is a constant current circuit electrically connected between the first terminal and the second terminal, a voltage controlled oscillation circuit in which the oscillation frequency changes due to a potential difference between the power supply voltage terminals, a p-channel transistor, an n-channel transistor whose gate-source voltage is constant by a constant current circuit, and a capacitor, and one of the source electrode and the drain electrode of the n-channel transistor is connected to the second terminal The other of the source electrode and the drain electrode of the n-channel transistor is electrically connected to one of the source electrode and the drain electrode of the p-channel transistor and the gate electrode, and the source electrode of the p-channel transistor and The other of the drain electrodes is electrically connected to the first terminal, and the gate electrode of the p-channel transistor is connected via a capacitor. The first terminal Te is an oscillation circuit electrically connected. Note that the first terminal and the second terminal correspond to a power supply voltage terminal in the voltage controlled oscillation circuit. Moreover, a resistor is not necessarily required for the constant current circuit.

  Another embodiment of the present invention includes a signal processing circuit and an antenna circuit that transmits and receives a signal for transmitting data stored in the signal processing circuit. The signal processing circuit includes the oscillation circuit having the above structure and the antenna circuit. And a rectifier circuit that generates a power supply voltage from the received signal. A power supply voltage is supplied to the first terminal and the second terminal of the oscillation circuit.

  One embodiment of the present invention includes a signal processing circuit and an antenna circuit that transmits and receives a signal for transmitting data stored in the signal processing circuit. The signal processing circuit receives the oscillation circuit having the above structure and the antenna circuit. The semiconductor device includes a rectifier circuit that generates a power supply voltage from the signal and a power supply circuit, and the power supply voltage is supplied to the first terminal and the second terminal of the oscillation circuit via the power supply circuit. Further, the power supply circuit may be a regulator circuit.

  Furthermore, the semiconductor device having the above structure may include a battery that stores a power supply voltage.

  In the present invention, the transistor is not particularly limited. Thin film transistors (TFTs) using non-single crystal semiconductor films typified by amorphous silicon and polycrystalline silicon, transistors formed using semiconductor substrates and SOI substrates, junction transistors, bipolar transistors, ZnO and a-InGaZnO A transistor using a compound semiconductor such as a transistor, a transistor using an organic semiconductor, or a carbon nanotube can be used. There is no particular limitation on the kind of the substrate on which the transistor is provided, and for example, a single crystal substrate, an SOI substrate, a glass substrate, a plastic substrate, or the like can be used.

  In the present invention, being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, other elements (for example, a switch, a transistor, a capacitor element) that enable electrical connection therebetween , Inductors, resistance elements, diodes, etc.) may be arranged. Needless to say, they may be arranged without interposing other elements, and being electrically connected includes the case of being directly connected.

  According to the present invention, it is possible to realize an oscillation circuit that outputs a signal having a stable frequency that is resistant to noise due to fluctuations in the power supply and that has little change in a wide voltage range. In addition, since the oscillation circuit of the present invention can generate a stable clock, a highly reliable semiconductor device capable of transmitting and receiving information wirelessly can be provided.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it is easy for those skilled in the art to make various changes in form and details without departing from the spirit and scope of the present invention. To be understood. Therefore, the present invention should not be construed as being limited to the description of the embodiment modes. Note that in the structures of the present invention described below, the same reference numerals are used in different drawings.

(Embodiment 1)
The configuration of the oscillation circuit of the present invention is shown in FIG. In FIG. 1, a terminal 208 is an input voltage terminal, and a terminal 209 is an input voltage reference voltage terminal. Note that in this specification, the input voltage terminal and the input voltage reference voltage terminal are also referred to as a first terminal and a second terminal, respectively, and are collectively referred to as a power supply voltage terminal. A gate electrode of an n-channel transistor (hereinafter referred to as “NMOS”) 206 is connected to the node N 1, and a source electrode of the NMOS 206 is connected to a terminal 209. A drain electrode of a p-channel transistor (hereinafter referred to as “PMOS”) 205 and a drain electrode of the NMOS 206 are connected, and these connection points are also connected to a node N1. The source electrode of the PMOS 205 is connected to the terminal 208, and the gate electrode of the PMOS 205 is connected to the node N2. The node N1 is connected to the terminal 209 through the capacitor 224. A current flows through the PMOS 205 due to the voltage at the node N2, and the current also flows through the NMOS 206 due to the connection between the NMOS 206 and the PMOS 205. When a current flows through the NMOS 206, a voltage corresponding to the current is generated at the node N1. Note that when the voltage at the node N2 or the voltage at the terminal 208 changes suddenly, the capacitor 224 can suppress fluctuations in voltage generated by the NMOS 206 even if the current of the PMOS 205 changes.

  A constant current circuit 10 is connected to the node N2.

  The constant current circuit 10 includes PMOSs 201 and 202, NMOSs 203 and 204, and a resistor 207 that form a current mirror circuit. The gate electrodes of the PMOSs 201 and 202 and the drain electrode of the PMOS 202 are connected to the node N 2, and the source electrodes of the PMOSs 201 and 202 are connected to the terminal 208. The drain electrode of the PMOS 201 is connected to the gate electrode of the NMOS 204 and the drain electrode of the NMOS 203. The drain electrode of the NMOS 204 is connected to the node N2. The source electrode of the NMOS 204 is connected to the gate electrode of the NMOS 203 and is connected to the terminal 209 via the resistor 207. The source electrode of the NMOS 203 is connected to the terminal 209.

  The constant current circuit 10 can pass a constant current flowing through the resistor 207 to the NMOSs 203 and 204 and the PMOSs 201 and 202. Note that the constant current flowing through the resistor 207 can be changed by the resistance value of the resistor 207. In this way, a voltage corresponding to the constant current flowing through the resistor 207 is generated at the node N2.

  On the other hand, the voltage controlled oscillation circuit 11 is connected to the node N1.

  The voltage controlled oscillation circuit 11 includes PMOS 210, 212, 213, 216, 217, 220, 221 and NMOS 211, 214, 215, 218, 219, 222, 223. Gate electrodes of NMOSs 211, 215, 219, and 223 are connected to the node N1. The source electrodes of the NMOSs 211, 215, 219, and 223 are connected to the terminal 209, and the source electrodes of the PMOSs 210, 212, 216, and 220 are connected to the terminal 208. The drain electrode of the NMOS 211 is connected to the gate electrode and drain electrode of the PMOS 210 and the gate electrodes of the PMOSs 212, 216, and 220. The drain electrode of the PMOS 212 is connected to the source electrode of the PMOS 213, the drain electrode of the PMOS 216 is connected to the source electrode of the PMOS 217, and the drain electrode of the PMOS 220 is connected to the source electrode of the PMOS 221. The drain electrode of the NMOS 215 is connected to the source electrode of the NMOS 214, the drain electrode of the NMOS 219 is connected to the source electrode of the NMOS 218, and the drain electrode of the NMOS 223 is connected to the source electrode of the NMOS 222. The drain electrode of the PMOS 213 is connected to the drain electrode of the NMOS 214, the gate electrode of the PMOS 217, and the gate electrode of the NMOS 218. The drain electrode of the PMOS 217 is connected to the drain electrode of the NMOS 218, the gate electrode of the PMOS 221 and the gate electrode of the NMOS 222. The drain electrode of the PMOS 221 is connected to the drain electrode of the NMOS 222, the gate electrode of the PMOS 213, the gate of the NMOS 214 electrode, and the output terminal 230.

  The current flowing through the NMOSs 211, 215, 219, and 223 is determined by the voltage generated at the node N1. Also, the same current as that of the NMOS 211 flows through the PMOS 210. Therefore, a voltage corresponding to the current flowing through the PMOS 210 is generated at the gate electrode of the PMOS 210. The current flowing through the PMOSs 212, 216, and 220 is determined by the voltage generated at the gate electrode of the PMOS 210.

  Note that the PMOS 213 and the NMOS 214 have an inverter configuration in which the gate electrodes of the PMOS 213 and NMOS 214 serve as input terminals and the drain electrode serves as an output terminal. Similarly, the PMOS 217 and the NMOS 218, and the PMOS 221 and the NMOS 222 have an inverter configuration. An input terminal constituting each inverter is connected to an output terminal constituting another inverter, thereby constituting a feedback circuit in which the output signal becomes an input signal. This is called a ring oscillator, and can output a signal having a frequency from the output terminal 230. In addition, since the current corresponding to the voltage of the node N1 flows through the PMOS and NMOS constituting each inverter, the oscillation frequency varies depending on the flowing current. That is, the oscillation frequency can be changed by the voltage of the node N1.

  Next, the operation of the oscillation circuit described above will be described. When a voltage is applied between the terminal 208 and the terminal 209, a current flows from the constant current circuit 10 to the PMOS 205 by the voltage generated at the node N2. Further, a current similar to that of the PMOS 205 flows through the NMOS 206, and a voltage corresponding to the current is generated at the node N1. In this way, the voltage controlled oscillation circuit 11 connected to the node N1 where the voltage is generated outputs a signal having a frequency corresponding to the voltage generated at the node N1.

  Note that even if the voltage between the terminal 208 and the terminal 209 is increased, the constant current circuit 10 allows a constant current to flow, and thus the gate-source voltage of the PMOS 205 does not change. The current flowing through the PMOS 205 varies depending on the drain-source voltage of the PMOS 205 even when the gate-source voltage of the PMOS 205 is constant. Thus, when the current of the PMOS 205 changes, the current flowing through the NMOS 206 changes, and thus the voltage generated at the node N1 changes.

  Note that when the voltage between the terminal 208 and the terminal 209 is constant, the voltage controlled oscillation circuit 11 outputs a signal having a frequency corresponding to the voltage at the node N1. When the voltage of the node N1 changes from V1 to V2 larger than V1 (V1 <V2), if the frequency corresponding to V1 is F1, and the frequency corresponding to V2 is F2, F2 is larger than F1. (F1 <F2). On the other hand, when the voltage of the node N1 is constant, the voltage controlled oscillation circuit 11 outputs a signal having a frequency corresponding to the voltage between the terminal 208 and the terminal 209. When the voltage between the terminal 208 and the terminal 209 is changed from V3 to V4 larger than V3 (V3 <V4), assuming that the frequency corresponding to V3 is F3 and the frequency corresponding to V4 is F4, F4 from F3 Becomes smaller (F3> F4).

  For example, even when the voltage between the terminal 208 and the terminal 209 increases, the voltage at the node N1 also increases at the same time, so that the oscillation frequency of the voltage controlled oscillation circuit 11 can be kept constant. On the other hand, when the voltage between the terminal 208 and the terminal 209 decreases, the voltage at the node N1 also decreases at the same time, so that the oscillation frequency of the voltage controlled oscillation circuit 11 can be kept constant.

  As described above, even when the voltage between the terminal 208 and the terminal 209 changes, the oscillation circuit of the present invention can suppress a change in the oscillation frequency and output a signal having a more stable frequency. .

  The constant current circuit 10 is not limited to the above-described form, and may be configured to flow a constant current, as long as the gate-source voltage of the PMOS 205 is constant.

  The voltage controlled oscillation circuit 11 is not limited to the above form, and may be any circuit that generates a signal having a frequency according to the voltage of the node N1.

(Embodiment 2)
In this embodiment mode, FIG. 2 shows one configuration of the oscillation circuit of the present invention which is different from that in Embodiment Mode 1. In FIG. 2, a terminal 1708 is an input voltage terminal, and a terminal 1709 is an input voltage reference voltage terminal. The gate electrode of the PMOS 1705 is connected to the node N 11, and the source electrode of the PMOS 1705 is connected to the terminal 1708. The drain electrode of the PMOS 1705 and the drain electrode of the NMOS 1706 are connected, and these connection points are also connected to the node N11. The source electrode of the NMOS 1706 is connected to the terminal 1709, and the gate electrode of the NMOS 1706 is connected to the node N12. The node N11 is connected to the terminal 1708 via the capacitor 1724. Due to the voltage at the node N12, a current flows through the NMOS 1706. Since the PMOS 1705 and the NMOS 1706 are connected, a current also flows through the PMOS 1705. When a current flows through the PMOS 1705, a voltage corresponding to the current is generated at the node N11. Note that the capacitor 1724 can suppress a change in voltage generated by the PMOS 1705 even if the current of the NMOS 1706 changes when the voltage of the node N12 or the voltage of the terminal 1708 changes suddenly.

  A constant current circuit 110 is connected to the node N12.

  The constant current circuit 110 includes PMOSs 1701 and 1702, NMOSs 1703 and 1704, and a resistor 1707 that form a current mirror circuit. The gate electrodes of the NMOSs 1703 and 1704 and the drain electrode of the NMOS 1704 are connected to the node N12. The source electrodes of the NMOSs 1703 and 1704 are connected to the terminal 1709. The drain electrode of the NMOS 1703 is connected to the gate electrode of the PMOS 1702 and the drain electrode of the PMOS 1701. The drain electrode of the PMOS 1702 is connected to the node N12. The source electrode of the PMOS 1702 is connected to the gate electrode of the PMOS 1701 and is connected to the terminal 1708 via the resistor 1707. The source electrode of the PMOS 1701 is connected to the terminal 1708.

  The constant current circuit 110 can pass a constant current flowing through the resistor 1707 to the PMOSs 1701 and 1702 and the NMOSs 1703 and 1704. Note that the constant current flowing through the resistor 1707 can be changed by the resistance value of the resistor 1707. In this way, a voltage corresponding to the constant current flowing through the resistor 1707 is generated at the node N12.

  On the other hand, the voltage controlled oscillation circuit 111 is connected to the node N11.

  The voltage controlled oscillation circuit 111 includes PMOSs 1710, 1712, 1713, 1716, 1717, 1720, 1721 and NMOSs 1711, 1714, 1715, 1718, 1719, 1722, 1723. The gate electrodes of the PMOSs 1710, 1712, 1716, and 1720 are connected to the node N11. The source electrodes of the PMOSs 1710, 1712, 1716 and 1720 are connected to the terminal 1708, and the source electrodes of the NMOSs 1711, 1715, 1719 and 1723 are connected to the terminal 1709. The drain electrode of the PMOS 1710 is connected to the gate electrode and the drain electrode of the NMOS 1711 and the gate electrodes of the NMOSs 1715, 1719, and 1723. The drain electrode of the PMOS 1712 is connected to the source electrode of the PMOS 1713, the drain electrode of the PMOS 1716 is connected to the source electrode of the PMOS 1717, and the drain electrode of the PMOS 1720 is connected to the source electrode of the PMOS 1721. The drain electrode of the NMOS 1715 is connected to the source electrode of the NMOS 1714, the drain electrode of the NMOS 1719 is connected to the source electrode of the NMOS 1718, and the drain electrode of the NMOS 1723 is connected to the source electrode of the NMOS 1722. The drain electrode of the PMOS 1713 is connected to the drain electrode of the NMOS 1714, the gate electrode of the PMOS 1717 and the gate electrode of the NMOS 1718. The drain electrode of the PMOS 1717 is connected to the drain electrode of the NMOS 1718, the gate electrode of the PMOS 1721, and the gate electrode of the NMOS 1722. The drain electrode of the PMOS 1721 is connected to the drain electrode of the NMOS 1722, the gate electrode of the PMOS 1713, the gate electrode of the NMOS 1714, and the output terminal 1730.

  The current flowing through the PMOSs 1710, 1712, 1716, and 1720 is determined by the voltage generated at the node N11. In addition, a current similar to that of the PMOS 1710 flows through the NMOS 1711. Therefore, a voltage corresponding to the current flowing through the NMOS 1711 is generated at the gate electrode of the NMOS 1711. The current flowing through the NMOSs 1715, 1719 and 1723 is determined by the voltage generated at the gate electrode of the NMOS 1711.

  Note that the PMOS 1713 and NMOS 1714 have an inverter configuration in which the gate electrodes of the PMOS 1713 and NMOS 1714 serve as input terminals and the drain electrode serves as an output terminal. Similarly, the PMOS 1717 and the NMOS 1718, and the PMOS 1721 and the NMOS 1722 have an inverter configuration. An input terminal constituting each inverter is connected to an output terminal constituting another inverter, thereby constituting a feedback circuit in which the output signal becomes an input signal. This is called a ring oscillator and can output a signal having a frequency from an output terminal 1730. In addition, since the current corresponding to the voltage of the node N11 flows through the PMOS and NMOS constituting each inverter, the oscillation frequency varies depending on the flowing current. That is, a signal having a frequency can be changed by the voltage of the node N11.

  Next, the operation of the oscillation circuit described above will be described. When a voltage is applied between the terminal 1708 and the terminal 1709, a current flows from the constant current circuit 110 to the NMOS 1706 due to the voltage generated at the node N12. Further, a current similar to that of the NMOS 1706 flows through the PMOS 1705, and a voltage corresponding to the current is generated at the node N11. In this way, the voltage controlled oscillation circuit 111 connected to the node N11 where the voltage is generated outputs a signal having a frequency corresponding to the voltage generated at the node N11.

  Note that even if the voltage between the terminal 1708 and the terminal 1709 is increased, the constant current circuit 110 causes a constant current to flow, and thus the gate-source voltage of the NMOS 1706 does not change. The current flowing through the NMOS 1706 varies depending on the drain-source voltage of the NMOS 1706 even when the gate-source voltage of the NMOS 1706 is constant. Thus, when the current of the NMOS 1706 changes, the current flowing through the PMOS 1705 changes, and the voltage generated at the node N11 changes.

  Note that when the voltage between the terminal 1708 and the terminal 1709 is constant, the voltage controlled oscillation circuit 111 outputs a signal having a frequency corresponding to the voltage between the terminal 1708 and the node N11. When the voltage between the terminal 1708 and the node N11 fluctuates from V5 to V6 larger than V5 (V5 <V6), assuming that the frequency corresponding to V5 is F5 and the frequency corresponding to V6 is F6, F5 to F6 Becomes larger (F5 <F6). On the other hand, when the voltage between the terminal 1708 and the node N11 is constant, the voltage controlled oscillation circuit 111 outputs a signal having a frequency corresponding to the voltage between the terminal 1708 and the terminal 1709. When the voltage between the terminal 1708 and the terminal 1709 is changed from V7 to V8 larger than V7 (V7 <V8), assuming that the frequency corresponding to V7 is F7 and the frequency corresponding to V8 is F8, F8 from F7 Becomes smaller (F7> F8).

  For example, even when the voltage between the terminal 1708 and the terminal 1709 increases, the voltage between the terminal 1708 and the node N11 also increases at the same time, so that the oscillation frequency of the voltage controlled oscillation circuit 111 can be kept constant. it can. On the other hand, when the voltage between the terminals 1708 and 1709 decreases, the voltage at the node N11 also decreases at the same time, so that the oscillation frequency of the voltage controlled oscillation circuit 111 can be kept constant.

  As described above, even when the voltage between the terminal 1708 and the terminal 1709 changes, the oscillation circuit of the present invention can suppress a change in the oscillation frequency and output a signal having a more stable frequency. .

  The constant current circuit 110 is not limited to the above-described form, and may have a configuration that allows a constant current to flow.

  The voltage controlled oscillation circuit 111 is not limited to the above form, and any circuit that generates a signal having a frequency by the voltage between the terminal 1708 and the node N11 may be used.

(Embodiment 3)
In this embodiment, a semiconductor device including the oscillation circuit described in the above embodiment and capable of transmitting and receiving information wirelessly will be described with reference to drawings.

  In recent years, a semiconductor device such as an RFID tag combining an ultra-small IC chip and an antenna for wireless communication has attracted attention. An RFID tag can write and read data by transmitting and receiving a communication signal using a wireless communication device (also referred to as a reader / writer). Note that an RFID tag (hereinafter simply referred to as an RFID) is also referred to as an IC (Integrated Circuit) tag, an IC chip, an RF tag, a wireless tag, or an electronic tag.

  As an application field of semiconductor devices capable of transmitting and receiving information wirelessly such as RFID, for example, merchandise management in the distribution industry can be cited. At present, merchandise management using bar codes and the like is the mainstream, but since bar codes are optically read, data cannot be read if there is a shield. On the other hand, since RFID reads data wirelessly, it can be read even if there is a shield. Accordingly, it is expected to improve the efficiency of product management and cost reduction. In addition, a wide range of applications such as boarding tickets, air passenger tickets, and automatic payment of fare are expected.

  One mode of a semiconductor device using the present invention as such an RFID will be described with reference to a block diagram shown in FIG.

  An RFID 300 in FIG. 3 includes an antenna circuit 301 and a signal processing circuit 302. The signal processing circuit 302 includes a rectifier circuit 303, a power supply circuit 304, a demodulation circuit 305, an oscillation circuit 306, a logic circuit 307, a memory control circuit 308, a memory circuit 309, a logic circuit 310, an amplifier 311, and a modulation circuit 312. ing.

  In the RFID 300, a communication signal received by the antenna circuit 301 is input to the demodulation circuit 305 in the signal processing circuit 302. There are 125 kHz, 13.56 MHz, 915 MHz, 2.45 GHz, and the like for the frequency of the received communication signal, that is, the signal transmitted / received between the antenna circuit 301 and the reader / writer, and each is set according to the ISO standard or the like. Of course, the frequency of the signal transmitted and received between the antenna circuit 301 and the reader / writer is not limited to this. For example, 300 GHz to 3 THz as a submillimeter wave, 30 GHz to 300 GHz as a millimeter wave, 3 GHz to 30 GHz as a microwave, pole Any frequency of 300 MHz to 3 GHz which is an ultrashort wave, 30 MHz to 300 MHz which is an ultrashort wave, 3 MHz to 30 MHz which is a short wave, 300 kHz to 3 MHz which is a medium wave, 30 kHz to 300 kHz which is a long wave, and 3 kHz to 30 kHz which is an ultrahigh wave is used. be able to. A signal transmitted and received between the antenna circuit 301 and the reader / writer is a signal obtained by modulating a carrier wave. The modulation method of the carrier wave may be analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum. Preferably, amplitude modulation or frequency modulation is used.

  In this embodiment, a case where a carrier wave as a communication signal is 915 MHz will be described. Note that a reference clock signal is necessary to process a signal in the RFID. Here, the clock signal is generated using the oscillation circuit 306 described in Embodiment 1 or 2. The oscillation signal output from the oscillation circuit 306 is supplied to the logic circuit 307 as a clock signal. The modulated carrier wave is demodulated by the demodulation circuit 305. The demodulated signal is also sent to the logic circuit 307 and analyzed. The signal analyzed by the logic circuit 307 is sent to the memory control circuit 308. Based on the signal, the memory control circuit 308 controls the memory circuit 309, takes out the data stored in the memory circuit 309, and sends it to the logic circuit 310. . The signal sent to the logic circuit 310 is encoded by the logic circuit 310 and then amplified by the amplifier 311. The modulation circuit 312 modulates the carrier wave by the signal. The reader / writer recognizes a signal from the RFID by the modulated carrier wave. On the other hand, the carrier wave entering the rectifier circuit 303 is rectified and then input to the power supply circuit 304. The power supply voltage thus obtained is supplied from the power supply circuit 304 to the demodulation circuit 305, the oscillation circuit 306, the logic circuit 307, the memory control circuit 308, the memory circuit 309, the logic circuit 310, the amplifier 311, the modulation circuit 312 and the like. To do. Note that the power supply circuit 304 is not necessarily required, but here has a function of stepping down, boosting, and inverting the input voltage. The RFID 300 operates as described above.

  Note that there is no particular limitation on the shape of the antenna in the antenna circuit 301. For example, as shown in FIG. 4A, a structure in which one antenna 351 is arranged around the signal processing circuit 352 on the substrate may be employed. Further, as shown in FIG. 4B, a structure in which a thin antenna 351 is arranged around the signal processing circuit 352 around the signal processing circuit 352 on the substrate may be employed. Further, as shown in FIG. 4C, the shape of an antenna 351 for receiving high-frequency electromagnetic waves may be taken with respect to the signal processing circuit 352 on the substrate. Further, as shown in FIG. 4D, the shape of an antenna 351 that is 180 degrees omnidirectional (same reception is possible from any direction) with respect to the signal processing circuit 352 on the substrate may be employed. In addition, as shown in FIG. 4E, the antenna 351 elongated in a rod shape may be formed with respect to the signal processing circuit 352 on the substrate. Further, the connection between the signal processing circuit and the antenna circuit in the antenna is not particularly limited. For example, the antenna 351 and the signal processing circuit 352 may be connected using wire bonding connection or bump connection, or may be attached to the antenna 351 using one surface of the chip signal processing circuit 352 as an electrode. Further, an ACF (anisotropy conductive film) can be used for attaching the signal processing circuit 352 and the antenna 351. The length required for the antenna differs depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, it may be about 60 mm (1/2 wavelength) if a half-wave dipole antenna is provided, and about 30 mm (¼ wavelength) if a monopole antenna is provided.

  Note that the antenna 351 may be provided by being stacked over the same substrate together with the signal processing circuit 352, or may be a configuration using an external antenna. Needless to say, the signal processing circuit 352 may have a configuration in which the antenna 351 is provided at the top or bottom.

  When the shape of FIG. 4B is employed for the antenna circuit 301 in FIG. 3, the antenna circuit 301 can be configured by an antenna 401 and a resonance capacitor 402 as shown in FIG. In such a case, the antenna 401 and the resonance capacitor 402 are collectively referred to as an antenna circuit 403.

  The rectifier circuit 303 only needs to be a circuit that the antenna circuit 301 converts an AC signal induced by a received carrier wave into a DC signal. For example, as shown in FIG. 5B, a rectifier circuit 407 may be configured by a diode 404, a diode 405, and a smoothing capacitor 406.

  Although the power supply voltage value obtained by RFID is easily changed depending on the distance to the reader / writer, etc., even when the power supply voltage value changes by using the oscillation circuit of the present invention, it is caused by the power supply voltage value. It is possible to suppress a change in the clock signal to be generated and generate a stable clock. Thus, a highly reliable semiconductor device capable of transmitting and receiving information wirelessly can be obtained.

  Note that the RFID in the present invention may have a battery 361 as shown in FIG. 6 in addition to the structure shown in FIG. When the power supply voltage output from the rectifier circuit 303 is not sufficient to operate the signal processing circuit 302, each circuit constituting the signal processing circuit 302 from the battery 361, for example, the demodulation circuit 305, the oscillation circuit 306, and the logic circuit 307 The power supply voltage can be supplied to the memory control circuit 308, the memory circuit 309, the logic circuit 310, the amplifier 311, the modulation circuit 312 and the like. Even when the power supply voltage is supplied from the battery 361 to the oscillation circuit 306, a constant power supply voltage is not necessarily generated due to noise generated by other analog circuits or pulse noise generated by the digital circuit. It cannot be supplied to 306. Therefore, also in the RFID 360 shown in FIG. 6, it is effective to use the oscillation circuit of the present invention, and the reliability as the RFID can be improved. For example, when the power supply voltage output from the rectifier circuit 303 is sufficiently larger than the power supply voltage necessary for operating the signal processing circuit 302, the surplus of the power supply voltage output from the rectifier circuit 303 is used as the battery. 361 may be charged to obtain stored energy. In addition to the antenna circuit 301 and the rectifier circuit 303, the antenna may be further provided with an antenna circuit and a rectifier circuit to obtain energy stored in the battery 361 from randomly generated radio waves or the like.

  In addition, a battery means the battery which can recover | restore continuous use time by charging. As the battery, a battery formed in a sheet shape is preferably used. For example, a lithium polymer battery using a gel electrolyte, a lithium ion battery, a lithium secondary battery, or the like can be used to reduce the size. Of course, any rechargeable battery may be used, such as a nickel metal hydride battery or a nickel cadmium battery, or a large-capacity capacitor.

  Further, a stable power supply voltage may be supplied to the power supply circuit 304 using a regulator circuit. Even in this case, as described above, a constant power supply voltage cannot always be supplied to the oscillation circuit 306 due to the influence of noise generated by other analog circuits and pulse noise generated by the digital circuit. Therefore, it is effective to use the oscillation circuit of the present invention, and the reliability as RFID can be further improved. Needless to say, a regulator circuit can be used for the power supply circuit of the RFID in FIG.

  This embodiment can be combined with any of the other embodiments in this specification as appropriate.

(Embodiment 4)
In this embodiment, an example of a method for manufacturing a semiconductor device such as an RFID described in the above embodiment will be described with reference to partial cross-sectional views.

  First, as shown in FIG. 7A, a separation layer 503 is formed on one surface of a substrate 501 with an insulating film 502 interposed therebetween, and then an insulating film 504 functioning as a base film and a semiconductor film 505 (for example, an amorphous film) A film containing crystalline silicon). Note that the insulating film 502, the separation layer 503, the insulating film 504, and the semiconductor film 505 can be formed successively.

  The substrate 501 is selected from a glass substrate, a quartz substrate, a metal substrate (for example, a stainless steel substrate), a semiconductor substrate such as a ceramic substrate, and a Si substrate. In addition, a substrate such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or acrylic can be selected as the plastic substrate. Note that in this step, the separation layer 503 is provided over the entire surface of the substrate 501 with the insulating film 502 interposed therebetween. However, if necessary, a separation layer is provided over the entire surface of the substrate 501 and then selectively removed by photolithography. May be provided.

  The insulating films 502 and 504 are formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide by a CVD method, a sputtering method, or the like. For example, in the case where the insulating film 502 and the insulating film 504 have a two-layer structure, a silicon nitride oxide film may be formed as the first insulating film and a silicon oxynitride film may be formed as the second insulating film. Alternatively, a silicon nitride film may be formed as the first insulating film, and a silicon oxide film may be formed as the second insulating film. The insulating film 502 functions as a blocking layer that prevents an impurity element from entering the separation layer 503 or an element formed thereon from the substrate 501. The insulating film 504 functions as a blocking layer that prevents an impurity element from entering a substrate 501 and a separation layer 503 from which elements are formed. In this manner, by forming the insulating film 502 and the insulating film 504 functioning as a blocking layer, an alkali metal such as Na or an alkaline earth metal is included in the release layer from the release layer 503 from the substrate 501. An impurity element can be prevented from adversely affecting an element formed thereon. Note that in the case where quartz is used for the substrate 501, the insulating films 502 and 504 may be omitted.

For the separation layer 503, a metal film, a stacked structure of a metal film and a metal oxide film, or the like can be used. As the metal film, tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), niobium (Nb), nickel (Ni), cobalt (Co), zirconium (Zr), zinc (Zn), A single layer of a film made of an element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), or an alloy material or compound material containing the element as a main component Alternatively, they are stacked. Further, these materials can be formed by using various CVD methods such as a sputtering method and a plasma CVD method. A stacked structure of a metal film and a metal oxide film, after forming a metal film described above, the plasma treatment in or under N _{2 O} atmosphere an oxygen atmosphere, by performing heat treatment in or under N _{2 O} atmosphere an oxygen atmosphere The oxide or oxynitride of the metal film can be provided on the surface of the metal film. For example, when a tungsten film is provided as a metal film by a sputtering method, a CVD method, or the like, a metal oxide film made of tungsten oxide can be formed on the tungsten film surface by performing plasma treatment on the tungsten film. In this case, the tungsten oxide is represented by WOx. The value of X is 2 to 3, and when X is 2 (WO ₂ ), X is 2.5 (W ₂ O ₅ ), X is 2.75 (W ₄ O ₁₁ ), X is In the case of 3 (WO ₃ ) and the like. In forming the tungsten oxide, there is no particular limitation on the value of X mentioned above, and it is preferable to determine which oxide is formed based on the etching rate or the like. In addition, for example, after forming a metal film (for example, tungsten), an insulating film such as silicon oxide (SiO ₂ ) is provided on the metal film by sputtering, and a metal oxide (for example, for example, Tungsten oxide) may be formed over tungsten. Further, as the plasma processing, for example, high-density plasma processing may be performed. In addition to the metal oxide film, metal nitride or metal oxynitride may be used. In this case, plasma treatment or heat treatment may be performed on the metal film in a nitrogen atmosphere or a nitrogen and oxygen atmosphere.

  The semiconductor film 505 is formed with a thickness of 25 to 200 nm (preferably 30 to 150 nm) by a sputtering method, an LPCVD method, a plasma CVD method, or the like.

  Next, as illustrated in FIG. 7B, the semiconductor film 505 is irradiated with laser light to be crystallized. Note that the semiconductor film 505 may be crystallized by a combination of laser light irradiation, a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Good. After that, the obtained semiconductor film is etched into a desired shape to form crystallized semiconductor films 505a to 505f, and a gate insulating film 506 is formed so as to cover the semiconductor films 505a to 505f.

  The gate insulating film 506 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide by a CVD method, a sputtering method, or the like. For example, in the case where the gate insulating film 506 has a two-layer structure, a silicon oxynitride film may be formed as the first insulating film and a silicon nitride oxide film may be formed as the second insulating film. Alternatively, a silicon oxide film may be formed as the first insulating film, and a silicon nitride film may be formed as the second insulating film.

  An example of a manufacturing process of the semiconductor films 505a to 505f will be briefly described below. First, an amorphous semiconductor film with a thickness of 50 to 60 nm is formed using a plasma CVD method. Next, after a solution containing nickel, which is a metal element that promotes crystallization, is held on the amorphous semiconductor film, the amorphous semiconductor film is subjected to dehydrogenation treatment (500 ° C., 1 hour), heat Crystallization treatment (550 ° C., 4 hours) is performed to form a crystalline semiconductor film. After that, crystallized semiconductor films 505a to 505f are formed by irradiating laser light and using a photolithography method. Note that the amorphous semiconductor film may be crystallized only by laser light irradiation without performing thermal crystallization using a metal element that promotes crystallization.

As a laser oscillator used for crystallization, there are a continuous wave laser beam (CW laser beam) and a pulsed laser beam (pulse laser beam). Examples of the laser beam that can be used here include gas lasers such as Ar laser, Kr laser, and excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline. (Ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants May be oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of these fundamental waves, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. In this case, a laser power density is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec. Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta as a medium, a laser, Ar ion laser, or Ti: sapphire laser with one or more added as a medium should be continuously oscillated It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or higher, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

The gate insulating film 506 may be formed by performing high-density plasma treatment on the semiconductor films 505a to 505f and oxidizing or nitriding the surface. For example, it is formed by plasma treatment in which a rare gas such as He, Ar, Kr, or Xe and a mixed gas such as oxygen, nitrogen oxide (NO ₂ ), ammonia, nitrogen, or hydrogen are introduced. In this case, when plasma is excited by introduction of microwaves, high-density plasma can be generated at a low electron temperature. The surface of the semiconductor film can be oxidized or nitrided by oxygen radicals (which may include OH radicals) or nitrogen radicals (which may include NH radicals) generated by this high-density plasma.

  By such treatment using high-density plasma, an insulating film with a thickness of 1 to 20 nm, typically 5 to 10 nm, is formed over the semiconductor film. Since the reaction in this case is a solid-phase reaction, the interface state density between the insulating film and the semiconductor film can be extremely low. Such high-density plasma treatment directly oxidizes (or nitrides) a semiconductor film (crystalline silicon or polycrystalline silicon), so that the thickness of the formed insulating film ideally varies greatly. Can be small. In addition, since the oxidation is not strengthened even at the crystal grain boundary of crystalline silicon, a very preferable state is obtained. That is, by performing solid-phase oxidation on the surface of the semiconductor film by the high-density plasma treatment shown here, an insulating film with good uniformity and low interface state density can be obtained without causing an abnormal oxidation reaction at the crystal grain boundary. Can be formed.

  As the gate insulating film 506, only an insulating film formed by high-density plasma treatment may be used, or an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride is deposited by a CVD method using plasma or thermal reaction. And may be laminated. In any case, the transistor formed by including an insulating film formed by high-density plasma in part or all of the gate insulating film can reduce variation in characteristics.

  In addition, the semiconductor films 505a to 505f obtained by scanning and crystallizing in one direction while irradiating the semiconductor film with a continuous wave laser or a laser beam oscillating at a frequency of 10 MHz or higher are in the scanning direction of the beam. There is a characteristic that crystals grow. By arranging the transistors in accordance with the scanning direction in the channel length direction (the direction in which carriers flow when a channel formation region is formed) and combining the gate insulating layer, characteristic variation is small and field effect mobility is reduced. A high thin film transistor (TFT: Thin Film Transistor) can be obtained.

  Next, a first conductive film and a second conductive film are stacked over the gate insulating film 506. Here, the first conductive film is formed with a thickness of 20 to 100 nm by a CVD method, a sputtering method, or the like. The second conductive film is formed with a thickness of 100 to 400 nm. The first conductive film and the second conductive film include tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium ( Nb) or the like, or an alloy material or a compound material containing these elements as main components. Alternatively, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus is used. Examples of the combination of the first conductive film and the second conductive film include a tantalum nitride film and a tungsten film, a tungsten nitride film and a tungsten film, a molybdenum nitride film and a molybdenum film, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the first conductive film and the second conductive film are formed. In the case of a three-layer structure instead of a two-layer structure, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.

  Next, a mask made of a resist is formed by photolithography, and an etching process for forming a gate electrode and a gate line is performed, so that the gate electrode 507 is formed above the semiconductor films 505a to 505f. Here, an example in which the gate electrode 507 is provided with a stacked structure of a first conductive film 507a and a second conductive film 507b is shown.

Next, as illustrated in FIG. 7C, an impurity element imparting n-type conductivity is added at a low concentration to the semiconductor films 505a to 505f by an ion doping method or an ion implantation method using the gate electrode 507 as a mask. Thereafter, a resist mask is selectively formed by photolithography, and an impurity element imparting p-type conductivity is added at a high concentration. As the impurity element exhibiting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as an impurity element imparting n-type conductivity, and is selectively introduced into the semiconductor films 505a to 505f so as to be included at a concentration of 1 × 10 ¹⁵ to 1 × 10 ¹⁹ / cm ^3. An impurity region 508 indicating a mold is formed. In addition, boron (B) is used as an impurity element imparting p-type, and is selectively introduced into the semiconductor films 505c and 505e so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Impurity regions 509 are formed.

  Subsequently, an insulating film is formed so as to cover the gate insulating film 506 and the gate electrode 507. The insulating film is formed by a single layer or a stacked layer of a film containing an inorganic material such as silicon, silicon oxide, or silicon nitride, or a film containing an organic material such as an organic resin, by plasma CVD or sputtering. To do. Next, the insulating film is selectively etched by anisotropic etching mainly in the vertical direction, so that an insulating film 510 (also referred to as a sidewall) in contact with the side surface of the gate electrode 507 is formed. The insulating film 510 is used as a mask for doping when forming an LDD (Lightly Doped Drain) region.

Subsequently, an impurity element imparting n-type conductivity is added to the semiconductor films 505a, 505b, 505d, and 505f at a high concentration by using a resist mask formed by a photolithography method, the gate electrode 507, and the insulating film 510 as masks. Thus, an n-type impurity region 511 is formed. Here, phosphorus (P) is used as an impurity element imparting n-type, and the semiconductor films 505a, 505b, 505d, and 505f are selectively used so as to be included at a concentration of 1 × 10 ¹⁹ to 1 × 10 ²⁰ / cm ^3. Then, an impurity region 511 having an n-type concentration higher than the impurity region 508 is formed.

  Through the above steps, n-channel thin film transistors 500a, 500b, 500d, and 500f and p-channel thin film transistors 500c and 500e are formed as shown in FIG. Note that these thin film transistors 500a to 500f are thin film transistors that constitute a semiconductor device such as an RFID of the present invention. Needless to say, the thin film transistor manufactured in this manner can be used as a thin film transistor constituting the oscillation circuit of the present invention.

  Note that the n-channel thin film transistor 500a includes a channel formation region in a region of the semiconductor film 505a that overlaps with the gate electrode 507, an impurity region 511 that forms a source region or a drain region in a region that does not overlap with the gate electrode 507 and the insulating film 510, and insulation. A low-concentration impurity region (LDD region) is formed between the channel formation region and the impurity region 511 in a region overlapping with the film 510. Similarly, in the n-channel thin film transistors 500b, 500d, and 500f, a channel formation region, a low-concentration impurity region, and an impurity region 511 are formed.

  The p-channel thin film transistor 500c includes a channel formation region in a region of the semiconductor film 505c that overlaps with the gate electrode 507 and an impurity region 509 that forms a source region or a drain region in a region that does not overlap with the gate electrode 507. Yes. Similarly, the channel formation region and the impurity region 509 are also formed in the p-channel thin film transistor 500e. Note that the p-channel thin film transistors 500c and 500e are not provided with an LDD region here, but the p-channel thin film transistor may be provided with an LDD region, or the n-channel thin film transistor may not be provided with an LDD region. Good.

  Next, as illustrated in FIG. 8A, an insulating film is formed as a single layer or a stacked layer so as to cover the semiconductor films 505a to 505f, the gate electrode 507, and the like, and the thin film transistors 500a to 500f are formed over the insulating film. A conductive film 513 which is electrically connected to impurity regions 509 and 511 which form a source region or a drain region is formed. Insulating films can be formed by CVD, sputtering, SOG, droplet ejection, screen printing, etc., inorganic materials such as silicon oxide and silicon nitride, polyimide, polyamide, benzocyclobutene, acrylic, epoxy, etc. These are formed as a single layer or stacked layers using an organic material or a siloxane material. Here, the insulating film is provided in two layers, and a silicon nitride oxide film is formed as the first insulating film 512a, and a silicon oxynitride film is formed as the second insulating film 512b. The conductive film 513 forms a source electrode or a drain electrode of the thin film transistors 500a to 500f.

  Before forming the insulating films 512a and 512b, or after forming one or more thin films of the insulating films 512a and 512b, recovery of crystallinity of the semiconductor film or activation of impurity elements added to the semiconductor film, Heat treatment for the purpose of hydrogenating the semiconductor film is preferably performed. For the heat treatment, thermal annealing, laser annealing, RTA, or the like is preferably applied.

  The conductive film 513 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), CVD, sputtering, or the like. Elements selected from copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or alloys containing these elements as main components The material or compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive film 513 may employ, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. . Note that the barrier film corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are suitable materials for forming the conductive film 513 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the semiconductor film, the natural oxide film is reduced and good contact is made with the semiconductor film. Can do.

  Next, an insulating film 514 is formed so as to cover the conductive film 513, and a conductive film 515 that is electrically connected to the conductive film 513 that forms a source electrode or a drain electrode of the thin film transistor is formed over the insulating film 514. . Note that FIG. 8B illustrates a conductive film 515 that is electrically connected to a conductive film 513 that forms a source electrode or a drain electrode of the thin film transistor 500a. The conductive film 515 can be formed using any of the materials shown for the conductive film 513 described above.

  Next, as illustrated in FIG. 8B, a conductive film 516 functioning as an antenna is formed so as to be electrically connected to the conductive film 515.

  The insulating film 514 is formed by a CVD method, a sputtering method, or the like using an insulating film containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or a film containing carbon such as DLC (diamond-like carbon), It can be provided in a single layer or laminated structure made of an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The conductive film 516 is formed using a conductive material by a CVD method, a sputtering method, a printing method such as screen printing or gravure printing, a droplet discharge method, a dispenser method, a plating method, or the like. Conductive materials are aluminum (Al), titanium (Ti), silver (Ag), copper (Cu), gold (Au), platinum (Pt) nickel (Ni), palladium (Pd), tantalum (Ta), molybdenum An element selected from (Mo) or an alloy material or a compound material containing these elements as a main component is formed in a single layer structure or a laminated structure.

  For example, when the conductive film 516 functioning as an antenna is formed using a screen printing method, a conductive paste in which conductive particles having a particle size of several nanometers to several tens of micrometers are dissolved or dispersed in an organic resin. Can be provided by selectively printing. Conductor particles include silver (Ag), gold (Au), copper (Cu), nickel (Ni), platinum (Pt), palladium (Pd), tantalum (Ta), molybdenum (Mo) and titanium (Ti). Any one or more metal particles, silver halide fine particles, or dispersible nanoparticles can be used. In addition, as the organic resin contained in the conductive paste, one or more selected from organic resins that function as a binder of metal particles, a solvent, a dispersant, and a coating material can be used. Typically, an organic resin such as an epoxy resin or a silicone resin can be given. In forming the conductive film, it is preferable to fire after extruding the conductive paste. For example, when fine particles containing silver as a main component (for example, a particle size of 1 nm or more and 100 nm or less) are used as a conductive paste material, the conductive film is obtained by being cured by baking in a temperature range of 150 to 300 ° C. Can do. Further, fine particles mainly composed of solder or lead-free solder may be used. In this case, it is preferable to use fine particles having a particle diameter of 20 μm or less. Solder and lead-free solder have the advantage of low cost.

Next, as illustrated in FIG. 8C, after an insulating film 517 is formed so as to cover the conductive film 516, a layer including the thin film transistors 500 a to 500 f, the conductive film 516, and the like (hereinafter referred to as “element formation layer 518”). Is removed from the substrate 501. Here, by irradiating laser light (for example, UV light), an opening is formed in a region avoiding the thin film transistors 500a to 500f, and then the element formation layer 518 is peeled from the substrate 501 using physical force. Yes. In addition, before the element formation layer 518 is peeled from the substrate 501, an etching agent may be introduced into the formed opening to selectively remove the peeling layer 503. As the etchant, a gas or liquid containing halogen fluoride or an interhalogen compound is used. For example, chlorine trifluoride (ClF ₃ ) is used as a gas containing halogen fluoride. Then, the element formation layer 518 is peeled from the substrate 501. Note that a part of the peeling layer 503 may be left without being removed. By doing so, the consumption of the etching agent can be suppressed, and the processing time required for removing the release layer can be shortened. Further, the element formation layer 518 can be held over the substrate 501 even after the peeling layer 503 is removed. In addition, cost can be reduced by reusing the substrate 501 from which the element formation layer 518 is separated.

  The insulating film 517 is formed by an CVD method, a sputtering method, or the like using an insulating film containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or a film containing carbon such as DLC (diamond-like carbon). It can be provided in a single layer or laminated structure made of an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin.

  In this embodiment mode, as shown in FIG. 9A, after an opening is formed in the element formation layer 518 by laser light irradiation, one surface of the element formation layer 518 (an exposed surface of the insulating film 517). ), The element formation layer 518 is peeled from the substrate 501.

  Next, as illustrated in FIG. 9B, after the second sheet material 520 is attached to the other surface (the surface exposed by peeling) of the element formation layer 518, one of heat treatment and pressure treatment is performed. Or both are performed and the 2nd sheet | seat material 520 is bonded together. As the first sheet material 519 and the second sheet material 520, a hot melt film or the like can be used.

  In addition, as the first sheet material 519 and the second sheet material 520, films provided with antistatic measures for preventing static electricity (hereinafter referred to as antistatic films) can be used. Examples of the antistatic film include a film in which an antistatic material is dispersed in a resin, a film on which an antistatic material is attached, and the like. The film provided with an antistatic material may be a film provided with an antistatic material on one side, or a film provided with an antistatic material on both sides. Furthermore, a film provided with an antistatic material on one side may be attached to the layer so that the surface provided with the antistatic material is on the inside of the film, or on the outside of the film. It may be pasted. Note that the antistatic material may be provided on the entire surface or a part of the film. The antistatic material here is a surfactant such as metal, oxide of indium and tin (ITO: Indium Tin Oxide), amphoteric surfactant, cationic surfactant, and nonionic surfactant. Can be used. In addition, as the antistatic material, a resin material containing a crosslinkable copolymer polymer having a carboxyl group and a quaternary ammonium base in the side chain can be used. An antistatic film can be obtained by sticking, kneading, or applying these materials to a film. By sealing with an antistatic film, it is possible to prevent the semiconductor element from being adversely affected by external static electricity when handled as a product.

  Through the above steps, the semiconductor device of the present invention can be manufactured. Note that although an example in which the antenna is formed over the same substrate as the thin film transistor is described in this embodiment mode, the present invention is not limited to this structure. The thin film transistor and the antenna are electrically connected to each other by bonding a first substrate over which a layer having a thin film transistor is formed and a second substrate over which a conductive layer functioning as an antenna is formed using a resin containing conductive particles. You may connect.

  In the above, the step of peeling after forming an element such as a thin film transistor on the substrate is shown, but the product may be used as it is without peeling. In addition, after an element such as a thin film transistor is provided over a glass substrate, the semiconductor substrate can be thinned and miniaturized by polishing the glass substrate from the side opposite to the surface where the element is provided.

  This embodiment can be combined with any of the other embodiments in this specification as appropriate.

(Embodiment 5)
In this embodiment, a method for manufacturing a transistor included in the oscillation circuit or the semiconductor device of the present invention, which is different from that in the above embodiment, will be described. The transistor included in the oscillation circuit or the semiconductor device of the present invention can be formed using a MOS transistor over a single crystal substrate in addition to the thin film transistor over the insulating substrate described in the above embodiment mode.

  In this embodiment, an example of a method for manufacturing a transistor included in the oscillation circuit or the semiconductor device of the present invention will be described with reference to partial cross-sectional views shown in FIGS.

  First, as illustrated in FIG. 10A, regions 902 and 903 (hereinafter also referred to as regions 902 and 903) in which elements are separated are formed in a semiconductor substrate 900. The regions 902 and 903 provided in the semiconductor substrate 900 are separated by an insulating film 901 (also referred to as a field oxide film). Note that here, an example in which a single crystal Si substrate having n-type conductivity is used as the semiconductor substrate 900 and a p-well 904 is provided in a region 903 of the semiconductor substrate 900 is shown.

  The substrate 900 can be used without any particular limitation as long as it is a semiconductor substrate. For example, a single crystal Si substrate having n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by Implanted) An SOI (Silicon on Insulator) substrate manufactured using an Oxygen method or the like can be used.

  For the element isolation regions 902 and 903, a selective oxidation method (LOCOS (Local Oxidation of Silicon) method), a trench isolation method, or the like can be used as appropriate.

  The p well formed in the region 903 of the semiconductor substrate 900 can be formed by selectively introducing an impurity element having p-type conductivity into the semiconductor substrate 900. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Note that in this embodiment, a semiconductor substrate having an n-type conductivity is used as the semiconductor substrate 900; therefore, no impurity element is introduced into the region 902; however, an impurity element exhibiting n-type is introduced. Thus, an n-well may be formed in the region 902. As the impurity element exhibiting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. On the other hand, in the case where a semiconductor substrate having p-type conductivity is used, an n-type impurity element is introduced into the region 902 to form an n-well, and the impurity element is not introduced into the region 903.

  Next, insulating films 905 and 906 are formed so as to cover the regions 902 and 903, respectively (FIG. 10B).

  The insulating films 905 and 906 can be formed of a silicon oxide film by performing heat treatment to oxidize the surfaces of the regions 902 and 903 provided in the semiconductor substrate 900, for example. In addition, after the silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing a nitriding treatment, and a stacked structure of the silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) It may be formed.

  Alternatively, the insulating films 905 and 906 may be formed using plasma treatment. For example, a silicon oxide film or a silicon nitride film is formed as the insulating films 905 and 906 by performing oxidation treatment or nitridation treatment by high-density plasma treatment on the surfaces of the regions 902 and 903 provided in the semiconductor substrate 900. Can do. Alternatively, the surface of the regions 902 and 903 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 902 and 903, and a silicon oxynitride film is formed over the silicon oxide film. Therefore, the insulating films 905 and 906 are films in which a silicon oxide film and a silicon oxynitride film are stacked. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 902 and 903 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  Note that the insulating films 905 and 906 function as gate insulating films in transistors to be completed later.

  Next, a conductive film is formed so as to cover the insulating films 905 and 906 formed over the regions 902 and 903 (FIG. 10C). Here, an example is shown in which a conductive film 907 and a conductive film 908 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 907 and 908 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as a main component. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 907 is formed using tantalum nitride, and the conductive film 908 is formed over the conductive film 908 with a stacked structure using tungsten. In addition, as the conductive film 907, a single layer or a stacked film selected from tungsten nitride, molybdenum nitride, or titanium nitride is used. As the conductive film 908, a single layer or a stacked film selected from tantalum, molybdenum, or titanium is used. Can be used.

  Next, the conductive films 907 and 908 provided in a stacked manner are selectively etched and removed, so that the conductive films 907 and 908 are left in portions above the regions 902 and 903, so that FIG. , Gate electrodes 909 and 910 are formed, respectively.

  Next, a resist mask 911 is selectively formed so as to cover the region 902, and impurity regions are formed by introducing an impurity element into the region 903 using the resist mask 911 and the gate electrode 910 as masks (FIG. 11). (B)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, phosphorus (P) is used as the impurity element.

  By introducing the impurity element, an impurity region 912 that forms a source region or a drain region and a channel formation region 913 are formed in the region 903 as shown in FIG.

  Next, a resist mask 914 is selectively formed so as to cover the region 903, and an impurity region is formed by introducing an impurity element into the region 902 using the resist mask 914 and the gate electrode 909 as masks (FIG. 11 (A)). C)). As the impurity element, an impurity element imparting n-type conductivity or an impurity element imparting p-type conductivity is used. As the impurity element exhibiting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, in FIG. 11B, an impurity element having a different conductivity type from the impurity element introduced into the region 903 (eg, boron (B)) is introduced. As a result, an impurity region 915 that forms a source region or a drain region and a channel formation region 916 are formed in the region 902.

  Next, a second insulating film 917 is formed so as to cover the insulating films 905 and 906 and the gate electrodes 909 and 910, and impurity regions 912 formed in regions 902 and 903 on the second insulating film 917, respectively. A wiring 918 electrically connected to 915 is formed (FIG. 12).

  The second insulating film 917 is formed of an insulating film containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or carbon such as DLC (diamond-like carbon) by a CVD method, a sputtering method, or the like. It can be provided in a single layer or a laminated structure made of a film including, an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as siloxane resin. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  The wiring 918 is formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt), copper (Cu) by CVD or sputtering. ), Gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or an alloy material containing these elements as a main component, or The compound material is formed as a single layer or a stacked layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The wiring 918 may employ, for example, a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, or a stacked structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Note that the barrier film corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are optimal materials for forming the wiring 918 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made.

  As described above, a MOS transistor can be manufactured using a single crystal substrate. Note that the structure of the transistor is not limited to the above structure, and may be, for example, an inverted stagger structure or a fin FET structure. Note that in the fin FET structure, the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

  This embodiment can be combined with any of the other embodiments in this specification as appropriate.

(Embodiment 6)
In this embodiment, a method for manufacturing a transistor included in the oscillation circuit or the semiconductor device of the present invention, which is different from that in the above embodiment, will be described. The transistor in the oscillation circuit or the semiconductor device of the present invention can be formed using a MOS transistor provided by a different manufacturing method from the MOS transistor over the single crystal substrate described in the above embodiment mode.

  In this embodiment, an example of a method for manufacturing a transistor included in the oscillation circuit or the semiconductor device of the present invention will be described with reference to partial cross-sectional views shown in FIGS.

  First, as illustrated in FIG. 13A, an insulating film is formed over the substrate 1200. Here, single crystal Si having n-type conductivity is used as the substrate 1200, and the insulating film 1201 and the insulating film 1202 are formed over the substrate 1200. For example, by performing heat treatment on the substrate 1200, silicon oxide is formed as the insulating film 1201, and silicon nitride is formed over the insulating film 1201 by a CVD method.

  Further, the substrate 1200 can be used without any particular limitation as long as it is a semiconductor substrate. For example, a single crystal Si substrate having an n-type or p-type conductivity, a compound semiconductor substrate (GaAs substrate, InP substrate, GaN substrate, SiC substrate, sapphire substrate, ZnSe substrate, etc.), bonding method or SIMOX (Separation by IMplanted) An SOI (Silicon on Insulator) substrate manufactured using an OXygen method or the like can be used.

  Alternatively, the insulating film 1202 may be provided by nitriding the insulating film 1201 by high-density plasma treatment after the insulating film 1201 is formed. Note that the insulating film provided over the substrate 1200 may be provided with a single layer or a stacked structure of three or more layers.

  Next, as illustrated in FIG. 13B, a pattern of a resist mask 1203 is selectively formed over the insulating film 1202 and selectively etched using the resist mask 1203 as a mask, so that the substrate 1200 is selectively etched. A recess 1204 is formed in the substrate. Etching of the substrate 1200 and the insulating films 1201 and 1202 can be performed by dry etching using plasma.

  Next, as shown in FIG. 13C, after the pattern of the resist mask 1203 is removed, an insulating film 1205 is formed so as to fill the recess 1204 formed in the substrate 1200.

  The insulating film 1205 is formed using an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide by a CVD method, a sputtering method, or the like. Here, as the insulating film 1205, a silicon oxide film is formed using TEOS (tetraethoxysilane) gas by an atmospheric pressure CVD method or a low pressure CVD method.

  Next, as shown in FIG. 14A, a surface of the substrate 1200 is exposed by performing a grinding process, a polishing process, or a CMP (Chemical Mechanical Polishing) process. Here, regions 1207 and 1208 are provided between the insulating films 1206 formed in the recesses 1204 of the substrate 1200 by exposing the surface of the substrate 1200. Note that the insulating film 1206 is obtained by removing the insulating film 1205 formed over the surface of the substrate 1200 by grinding, polishing, or CMP. Subsequently, a p-well 1209 is formed in the region 1208 by selectively introducing an impurity element having p-type conductivity.

  As the p-type impurity element, boron (B), aluminum (Al), gallium (Ga), or the like can be used. Here, boron (B) is introduced into the region 1208 as the impurity element.

  Note that in this embodiment, since a semiconductor substrate having n-type conductivity is used as the substrate 1200, an impurity element is not introduced into the region 1207; however, by introducing an impurity element exhibiting n-type conductivity An n-well may be formed in the region 1207. As the impurity element exhibiting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used.

  On the other hand, in the case of using a semiconductor substrate having p-type conductivity, an n-type impurity element may be introduced into the region 1207 to form an n-well, and the impurity element may not be introduced into the region 1208.

  Next, as illustrated in FIG. 14B, insulating films 1210 and 1211 are formed over the surfaces of the regions 1207 and 1208 of the substrate 1200, respectively.

  For example, the insulating films 1210 and 1211 can be formed using silicon oxide films by oxidizing the surfaces of the regions 1207 and 1208 provided in the substrate 1200 by heat treatment. In addition, after the silicon oxide film is formed by a thermal oxidation method, the surface of the silicon oxide film is nitrided by performing a nitriding treatment, and a stacked structure of the silicon oxide film and a film containing oxygen and nitrogen (silicon oxynitride film) It may be formed.

  In addition, as described above, the insulating films 1210 and 1211 may be formed by plasma treatment. For example, the surfaces of the regions 1207 and 1208 provided in the substrate 1200 are subjected to oxidation treatment or nitridation treatment by high-density plasma treatment, whereby silicon oxide (SiOx) films or silicon nitride (SiNx) films are formed as the insulating films 1210 and 1211. Can be formed. Alternatively, the surface of the regions 1207 and 1208 may be oxidized by high-density plasma treatment, and then nitridation may be performed by performing high-density plasma treatment again. In this case, a silicon oxide film is formed in contact with the surfaces of the regions 1207 and 1208, and a silicon oxynitride film is formed over the silicon oxide film. Therefore, the insulating films 1210 and 1211 are films in which a silicon oxide film and a silicon oxynitride film are stacked. Alternatively, after a silicon oxide film is formed on the surfaces of the regions 1207 and 1208 by a thermal oxidation method, oxidation treatment or nitridation treatment may be performed by high-density plasma treatment.

  Note that the insulating films 1210 and 1211 formed in the regions 1207 and 1208 of the substrate 1200 function as gate insulating films in transistors to be completed later.

  Next, as illustrated in FIG. 14C, a conductive film is formed so as to cover the insulating films 1210 and 1211 formed over the regions 1207 and 1208 provided in the substrate 1200. Here, an example is shown in which a conductive film 1212 and a conductive film 1213 are sequentially stacked as the conductive film. Needless to say, the conductive film may be formed of a single layer or a stacked structure of three or more layers.

  The conductive films 1212 and 1213 are selected from tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), and the like. Or an alloy material or a compound material containing these elements as a main component. Alternatively, a metal nitride film obtained by nitriding these elements can be used. In addition, a semiconductor material typified by polycrystalline silicon doped with an impurity element such as phosphorus can be used.

  Here, the conductive film 1212 is formed using tantalum nitride, and the conductive film 1213 is formed using tungsten as the conductive film 1213 over the stacked structure. In addition, the conductive film 1212 is a single layer or a stacked film selected from tantalum nitride, tungsten nitride, molybdenum nitride, or titanium nitride, and the conductive film 1213 is selected from tungsten, tantalum, molybdenum, or titanium. A single layer or a laminated film can be used.

  Next, as shown in FIG. 15A, the conductive films 1212 and 1213 provided in a stacked manner are selectively removed by etching, so that a portion of the substrate 1200 above the regions 1207 and 1208 is electrically conductive. The films 1212 and 1213 are left to form conductive films 1214 and 1215 that function as gate electrodes, respectively. Here, in the substrate 1200, the surfaces of the regions 1207 and 1208 that do not overlap with the conductive films 1214 and 1215 are exposed.

  Specifically, in the region 1207 of the substrate 1200, a portion of the insulating film 1210 formed below the conductive film 1214 that does not overlap with the conductive film 1214 is selectively removed, so that the conductive film 1214 and the insulating film 1210 It forms so that an edge part may correspond substantially. In the region 1208, a portion of the insulating film 1211 formed below the conductive film 1215 that does not overlap with the conductive film 1215 is selectively removed, so that the end portions of the conductive film 1215 and the insulating film 1211 substantially match. To form.

  In this case, an insulating film or the like that does not overlap with the formation of the conductive films 1214 and 1215 may be removed, or after the formation of the conductive films 1214 and 1215, the remaining resist mask or the conductive films 1214 and 1215 may be used as a mask. An insulating film or the like that does not overlap may be removed.

  Next, as illustrated in FIG. 15B, an impurity element is selectively introduced into the regions 1207 and 1208 of the substrate 1200. Here, a low concentration impurity element imparting n-type conductivity is selectively introduced into the region 1208 using the conductive film 1215 as a mask, so that the impurity region 1217 is formed. On the other hand, an impurity region 1216 is formed in the region 1207 by selectively introducing a low-concentration impurity element imparting p-type conductivity using the conductive film 1214 as a mask. As the impurity element imparting n-type conductivity, phosphorus (P), arsenic (As), or the like can be used. As the impurity element imparting p-type conductivity, boron (B), aluminum (Al), gallium (Ga), or the like can be used.

  Next, sidewalls 1218 in contact with the side surfaces of the conductive films 1214 and 1215 are formed. Specifically, a film including an inorganic material of silicon, silicon oxide, or silicon nitride, or a film including an organic material such as an organic resin is formed in a single layer or stacked layers by a plasma CVD method, a sputtering method, or the like. Form. Then, the insulating film can be selectively etched by anisotropic etching mainly in the vertical direction so as to be in contact with the side surfaces of the conductive films 1214 and 1215. Note that the sidewall 1218 is used as a mask for doping when an LDD (Lightly Doped Drain) region is formed. Here, the sidewalls 1218 are formed so as to be in contact with the side surfaces of the insulating films and the floating gate electrodes formed below the conductive films 1214 and 1215.

  Subsequently, as illustrated in FIG. 15C, an impurity element is introduced into the regions 1207 and 1208 of the substrate 1200 using the sidewalls 1218 and the conductive films 1214 and 1215 as masks, thereby functioning as a source region or a drain region. An impurity region to be formed is formed. Here, a high concentration n-type impurity element is introduced into the region 1208 of the substrate 1200 with the sidewalls 1218 and the conductive film 1215 as masks. Further, an impurity element imparting high concentration p-type is introduced into the region 1207 using the sidewall 1218 and the conductive film 1214 as masks.

  As a result, an impurity region 1220 that forms a source region or a drain region, a low-concentration impurity region 1221 that forms an LDD region, and a channel formation region 1222 are formed in the region 1207 of the substrate 1200. In the region 1208 of the substrate 1200, an impurity region 1223 that forms a source region or a drain region, a low-concentration impurity region 1224 that forms an LDD region, and a channel formation region 1225 are formed.

  Note that in this embodiment mode, the impurity element is introduced in a state where the regions 1207 and 1208 of the substrate 1200 that do not overlap with the conductive films 1214 and 1215 are exposed. Accordingly, the channel formation regions 1222 and 1225 formed in the regions 1207 and 1208 of the substrate 1200 can be formed in a self-aligned manner with the conductive films 1214 and 1215.

  Next, a second insulating film 1226 is formed so as to cover insulating films, conductive films, and the like provided over the regions 1207 and 1208 of the substrate 1200, and an opening 1227 is formed in the insulating film 1226 (FIG. 16). (A)).

  The second insulating film 1226 is formed using an insulating film containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxynitride, or silicon nitride oxide, or carbon such as DLC (diamond-like carbon) by a CVD method, a sputtering method, or the like. It can be provided in a single layer or a laminated structure made of a film including, an organic material such as epoxy, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic, or a siloxane material such as a siloxane resin. Note that the siloxane material corresponds to a material including a Si—O—Si bond. Siloxane has a skeleton structure formed of a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aryl group) is used. A fluoro group can also be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  Next, a conductive film 1228 is formed in the opening 1227 by a CVD method, and conductive films 1229a to 1229d are selectively formed over the insulating film 1226 so as to be electrically connected to the conductive film 1228 (FIG. 16). (B)).

  The conductive films 1228 and 1229a to 1229d are formed of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), molybdenum (Mo), nickel (Ni), platinum (Pt) by CVD or sputtering. ), Copper (Cu), gold (Au), silver (Ag), manganese (Mn), neodymium (Nd), carbon (C), silicon (Si), or these elements as main components The alloy material or the compound material is formed as a single layer or a laminated layer. The alloy material containing aluminum as a main component corresponds to, for example, a material containing aluminum as a main component and containing nickel, or an alloy material containing aluminum as a main component and containing nickel and one or both of carbon and silicon. The conductive films 1228 and 1229a to 1229d include, for example, a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, and a barrier film, and a laminated structure of a barrier film, an aluminum silicon (Al—Si) film, a titanium nitride film, and a barrier film. Should be adopted. Note that the barrier film corresponds to a thin film formed of titanium, a nitride of titanium, molybdenum, or a nitride of molybdenum. Aluminum and aluminum silicon are suitable materials for forming the conductive film 1228 because they have low resistance and are inexpensive. In addition, when an upper layer and a lower barrier layer are provided, generation of hillocks of aluminum or aluminum silicon can be prevented. In addition, when a barrier film made of titanium, which is a highly reducing element, is formed, even if a thin natural oxide film is formed on the crystalline semiconductor film, the natural oxide film is reduced, and the crystalline semiconductor film is excellent. Contact can be made. Here, the conductive film 1228 can be formed by selectively growing tungsten (W) by a CVD method.

  Through the above steps, an oscillation circuit or a semiconductor device including a p-type transistor formed in the region 1207 of the substrate 1200 and an n-type transistor formed in the region 1208 can be obtained.

  Note that the structure of the transistor is not limited to the above structure, and may be, for example, an inverted stagger structure or a fin FET structure. Note that in the fin FET structure, the short channel effect accompanying the miniaturization of the transistor size can be suppressed.

  This embodiment can be combined with any of the other embodiments in this specification as appropriate.

(Embodiment 7)
In this embodiment mode, application of a semiconductor device such as an RFID of the present invention will be described. The semiconductor device of the present invention includes, for example, banknotes, coins, securities, bearer bonds, certificate documents (driver's license, resident card, etc.), packaging containers (wrapping paper, bottles, etc.), recording media (DVD software) And video tapes), vehicles (bicycles, etc.), personal items (such as bags and glasses), foods, plants, animals, human bodies, clothing, daily necessities, electronic devices, etc. and luggage tags It can be used as a so-called ID label, ID tag, or ID card provided on an article. Electronic devices refer to liquid crystal display devices, EL display devices, television devices (also simply referred to as televisions, television receivers, television receivers), mobile phones, and the like. Although the power supply voltage value obtained by RFID is easily changed depending on the distance to the reader / writer or the like, even if the power supply voltage value is changed by using the oscillation circuit of the present invention, it is caused by the power supply voltage value. A stable clock can be generated by suppressing changes in the clock signal. Thus, a highly reliable semiconductor device capable of transmitting and receiving information wirelessly can be obtained.

  In this embodiment, an application example of the present invention and an example of a product with the application will be described with reference to FIG.

  FIG. 17A illustrates an example of a state of a completed semiconductor device having an RFID according to the present invention. A plurality of ID labels 1603 incorporating RFID 1602 are formed on a label mount 1601 (separate paper). The ID label 1603 is stored in the box 1604. On the ID label 1603, information (product name, brand, trademark, trademark owner, seller, manufacturer, etc.) related to the product or service is recorded, while the built-in RFID includes An ID number unique to the product (or product type) is attached, and it is possible to easily grasp illegal activities such as forgery, infringement of intellectual property rights such as trademark rights and patent rights, and unfair competition. In addition, in the RFID, a great deal of information that cannot be clearly stated on the container or label of the product, for example, the product's production area, sales place, quality, raw materials, efficacy, use, quantity, shape, price, production method, usage method, The production time, use time, expiration date, instruction, intellectual property information about the product, etc. can be input, and the trader and the consumer can access the information with a simple reader. In addition, rewriting and erasing can be easily performed from the producer side, but rewriting and erasing cannot be performed from the trader and consumer side.

  FIG. 17B illustrates a label-like ID tag 1611 with a built-in RFID 1612. By providing the ID tag 1611 on the product, product management becomes easy. For example, when a product is stolen, the culprit can be quickly grasped by following the route of the product. As described above, by providing the ID tag, it is possible to distribute a product excellent in so-called traceability.

  FIG. 17C is an example of a state of a finished product of the ID card 1621 including the RFID 1622 according to the present invention. The ID card 1621 includes all kinds of cards such as a cash card, a credit card, a prepaid card, an electronic ticket, electronic money, a telephone card, and a membership card.

  FIG. 17D shows the state of a completed product of bearer bond 1631. An RFID 1632 is embedded in the bearer bond 1631, and the periphery thereof is molded with resin to protect the RFID. Here, the resin is filled with a filler. The bearer bond 1631 can be manufactured in the same manner as the ID label, ID tag, and ID card according to the present invention. The bearer bonds include stamps, tickets, tickets, admission tickets, gift certificates, book tickets, stationery tickets, beer tickets, gift tickets, various gift certificates, various service tickets, etc. Is not to be done. Further, by providing the RFID 1632 of the present invention to bills, coins, securities, bearer bonds, certificates, etc., an authentication function can be provided, and forgery can be prevented by utilizing this authentication function. .

  FIG. 17E illustrates a book 1643 attached with an ID label 1641 that includes an RFID 1642 according to the present invention. The RFID 1642 of the present invention is fixed to an article by being pasted or embedded on the surface. As shown in FIG. 17E, a book is embedded in paper, or a package made of an organic resin is embedded in the organic resin, and is fixed to each article. The RFID 1642 of the present invention realizes a small size, a thin shape, and a light weight, and thus does not impair the design of the product itself even after being fixed to the product.

  Although not shown here, by providing the RFID of the present invention to packaging containers, recording media, personal items, foods, clothing, daily necessities, electronic devices, etc., the efficiency of systems such as inspection systems can be improved. Can be planned. In addition, forgery and theft can be prevented by providing RFID for vehicles. In addition, it is possible to easily identify individual creatures by embedding them in creatures such as animals. For example, by burying a wireless tag in a living creature such as livestock, it is possible to easily identify the year of birth, gender or type.

  As described above, the RFID of the present invention can be provided and used for any goods (including living creatures).

  This embodiment can be combined with any of the other embodiments in this specification as appropriate.

The figure explaining the oscillation circuit of this invention The figure explaining the oscillation circuit of this invention 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. 6A and 6B illustrate a structure of a semiconductor device of the present invention. Partial sectional view of the semiconductor device of the present invention Partial sectional view of the semiconductor device of the present invention Partial sectional view of the semiconductor device of the present invention The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The fragmentary sectional view of the transistor which the oscillation circuit or semiconductor device of this invention has The figure explaining an example of the article | item concerning this invention

Explanation of symbols

10 constant current circuit 11 voltage controlled oscillation circuit 201 PMOS
202 PMOS
203 NMOS
204 NMOS
205 PMOS
206 NMOS
207 Resistor 208 Terminal 209 Terminal 210 PMOS
211 NMOS
212 PMOS
213 PMOS
214 NMOS
215 NMOS
216 PMOS
217 PMOS
218 NMOS
219 NMOS
220 PMOS
221 PMOS
222 NMOS
223 NMOS
224 Capacity 230 Output terminal 300 RFID
301 Antenna Circuit 302 Signal Processing Circuit 303 Rectifier Circuit 304 Power Supply Circuit 305 Demodulation Circuit 306 Oscillation Circuit 307 Logic Circuit 308 Memory Control Circuit 309 Memory Circuit 310 Logic Circuit 311 Amplifier 312 Modulation Circuit 351 Antenna 352 Signal Processing Circuit 360 RFID
361 Battery 401 Antenna 402 Resonance capacity 403 Antenna circuit 404 Diode 405 Diode 406 Smoothing capacity 407 Rectifier circuit

Claims (4)

A first terminal having a function of supplying a first potential;
A second terminal having a function of supplying a second potential lower than the first potential;
A voltage controlled oscillation circuit having a function of outputting a signal having a different frequency according to the power supply voltage and a potential input to an input terminal, using a potential difference between the first potential and the second potential as a power supply voltage;
A capacitor, a p-channel first transistor, an n-channel second transistor, a p-channel third transistor, a p-channel fourth transistor, and an n-channel fifth transistor A transistor, an n-channel sixth transistor, and a resistance element,
One of a source and a drain of the first transistor is electrically connected to the first terminal;
The other of the source and the drain of the first transistor is electrically connected to one of the second source and the drain and the gate of the second transistor;
A gate of the second transistor is electrically connected to the second terminal via the capacitor;
The other of the source and the drain of the second transistor is electrically connected to the second terminal;
A gate of the second transistor is electrically connected to the input terminal;
A gate of the first transistor is connected to a gate of the third transistor;
One of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to the first terminal;
The other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor;
The other of the source and the drain of the fifth transistor is electrically connected to the second terminal via the resistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor and one of the source and the drain of the sixth transistor;
The other of the source and the drain of the sixth transistor is electrically connected to the second terminal;
An oscillation circuit, wherein the gate of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor. A first terminal having a function of supplying a first potential;
A second terminal having a function of supplying a second potential higher than the first potential;
A voltage controlled oscillation circuit having a function of outputting a signal having a different frequency according to the power supply voltage and a potential input to an input terminal, using a potential difference between the first potential and the second potential as a power supply voltage;
A capacitor, an n-channel first transistor, a p-channel second transistor, an n-channel third transistor, an n-channel fourth transistor, and a p-channel fifth transistor A p-channel sixth transistor, and a resistance element,
One of a source and a drain of the first transistor is electrically connected to the first terminal;
The other of the source and the drain of the first transistor is electrically connected to one of the second source and the drain and the gate of the second transistor;
A gate of the second transistor is electrically connected to the second terminal via the capacitor;
The other of the source and the drain of the second transistor is electrically connected to the second terminal;
A gate of the second transistor is electrically connected to the input terminal;
A gate of the first transistor is connected to a gate of the third transistor;
One of a source and a drain of the third transistor and one of a source and a drain of the fourth transistor are electrically connected to the first terminal;
The other of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the fifth transistor, the gate of the third transistor, and the gate of the fourth transistor;
The other of the source and the drain of the fifth transistor is electrically connected to the second terminal via the resistor;
The other of the source and the drain of the fourth transistor is electrically connected to the gate of the fifth transistor and one of the source and the drain of the sixth transistor;
The other of the source and the drain of the sixth transistor is electrically connected to the second terminal;
An oscillation circuit, wherein the gate of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor. A semiconductor device using the oscillation circuit according to claim 1. 4. The semiconductor device comprising: the oscillation circuit according to claim 1; an antenna circuit; and a rectifier circuit that generates the power supply voltage from a signal received by the antenna circuit. .

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