JP2003168291A - Semiconductor integrated circuit and power source supply method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which influence of noise in high voltage is little, dispersion of voltage in low voltage is eliminated, and current consumption at standby is little, and a power source supply method. <P>SOLUTION: A Vdet signal becomes a signal 'H' of a high level when external power source voltage is high. Hence, when external power source voltage is high, a nMOS 75 is turned on and a pMOS 74 is turned off, thereby, a power source of a nMOS regulator generating power source 72 is supplied to an internal circuits 73. Also, when external power source voltage is low, a nMOS 75 is turned off and a pMOS 74 is turned on, thereby, a power source of a pMOS regulator generating power source 71 is supplied to the internal circuits 73. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a power supply method, and more particularly to a semiconductor integrated circuit having two step-down power supplies for stepping down an external power supply voltage to a predetermined internal power supply voltage and a power supply method.

[0002]

2. Description of the Related Art DRAM (Dynamic Rando)
m Access Memory) is a notebook PC
Applications for portable devices such as (Personal Computer) and mobile phones are expanding. Such a portable device uses a battery as a power source, and is required to operate with low power consumption in order to extend the battery life.

Therefore, in order to reduce the power consumption in the DRAM, it has been conventionally practiced to step down the external power supply voltage and use this stepped down voltage as the operating power supply voltage.

Referring to FIG. 1, a conventional semiconductor integrated circuit (D
The RAM 5) will be described. The semiconductor integrated circuit of FIG. 1 includes a memory core 1, an interface circuit 2, a logic circuit 3 and a power supply 4. The interface circuit 2 includes a CPU (Central Processes) (not shown).
signal, control signal and data signal from the address / control line (Add / Cont) and the data line (DQ) from the Sing Unit, and sends them to the logic circuit 3 and the signal received from the logic circuit 3. Is sent to the CPU via the data line (DQ). The logic circuit 3 generates a control signal that determines the operation timing of each internal circuit based on an address signal, a control signal, and the like received from the CPU, writes and reads the memory core 1, and writes data and read data. Generate data. The power supply 4 receives power from an external power supply (high voltage Vdd / ground voltage Vss) and supplies a predetermined potential to the memory core 1, the interface circuit 2 and the logic circuit 3.

The power supply provided by the power supply circuit 4 will be described with reference to FIG. The power supply circuit 4 includes a step-down power supply 12 and a step-up power supply 1.
3, the precharge power supply 14 and the negative power supply 15 are supplied to the internal circuit 6 having the memory core 1, the interface circuit 2, and the logic circuit. These step-down power source 12 and step-up power source 1
3. The precharge power source 14 and the negative voltage source 15 generate a predetermined voltage by referring to the reference voltage output from the reference voltage generator 11 and output it.

The voltage generated by the step-down power supply 12 is an internal power supply voltage and is supplied to, for example, the bit line of the memory core 1, the interface circuit 2 and the logic circuit 3. Step-up power supply 1
The voltage generated by 3 is a boosted voltage, for example,
It is supplied to the word line of the memory core 1. The precharge power supply 14 supplies a precharge voltage to the memory core 1, for example. The negative voltage source 15 is supplied to the substrate of the memory core 1, for example.

FIG. 3 shows the step-down power supply 12 and the step-up power supply 1 when the external power supply voltage Vcc rises from zero voltage when the external power supply is turned on.
3 shows the relationship between the voltages output from the precharge power supply 14 and the negative power supply 15. The voltage output from the negative power supply 15 is Vbb when the external power supply voltage Vcc reaches a predetermined voltage.
(Negative voltage) 21. Further, the voltage output from the precharge power supply 14 becomes Vpr (precharge voltage) 22 when the external power supply voltage Vcc reaches a predetermined voltage. Similarly, the voltage output from the step-down power supply 12 and the step-up power supply 13 is Vi when the external power supply voltage Vcc reaches a predetermined voltage.
i (internal power supply voltage) 23 and Vpp (boosted voltage)
24.

An example of a reference voltage generating circuit in the reference voltage generator 11 will be described with reference to FIG. The circuit of FIG.
S31, pMOS32, nMOS33, nMOS34,
It is composed of a buffer amplifier 35 and a resistance element 36.

The pMOS 31 and pMOS 32 form a current mirror circuit. Here, if the power supply voltage Vcc rises, the current of the pMOS 31 increases and nM
The OS 34 enters a deep conductive state, the voltage drop in the resistance element 36 increases, and the potential at the point B rises. As a result, the nMOS 33 becomes deeply conductive and the potential at the point A decreases. Similarly, if the power supply voltage Vcc decreases, the potential at the point A increases. In this way, point A is
It is set to a stable potential with respect to fluctuations in the power supply voltage Vcc.

The potential at the point A compensates for temperature fluctuations and fluctuations in the external power supply voltage, but the effects of variations in the transistors forming the circuit remain. So A
A buffer amplifier 35 is connected to the point to eliminate the variation of the transistor and output of the reference voltage generator 11 (Vre
f).

An example of the pMOS regulator generation power supply will be described with reference to FIG. The pMOS regulator generation power source of FIG. 5A is composed of pMOS41, pMOS42, pMOS
43, nMOS44, nMOS45 and nMOS46. Note that pMOS41 and pMOS42
Constitutes a current mirror circuit, and includes nMOS44, nM
The OS 45 and the nMOS 46 form a differential amplifier 48, and the pMOS 43 functions as a driver 47. FIG. 5 (A) can be simply illustrated as FIG. 5 (B).

To explain the operation, the output voltage Vii of the driver 47 and the reference voltage Vref are compared by the differential amplifier 48, and the output (Vref-vii) is controlled to be zero. As a result, finally, the output voltage Vii of the driver 47 becomes the same voltage as the reference voltage Vref.

Since the pMOS regulator generation power supply of FIG. 5 feeds back the output voltage Vii of the driver 47, the output voltage Vii independent of the load current can be obtained. Since the external power supply voltage is applied to the source electrode of the driver 47, the sensitivity to the noise of the external power supply voltage Vcc tends to be high. In order to improve the stability of the output voltage Vii with respect to load current fluctuations, it is necessary to improve the responsiveness of the differential amplifier 48. For this purpose, the current consumption in the differential amplifier 48 needs to be on the order of mA, which increases the current consumption.

The pMOS regulator generated power supply has the advantages that the generated voltage has a high flatness and the area can be easily saved. On the other hand, the pMOS regulator generated power supply has the disadvantages that the noise influence is large and the power consumption is large. Note that the high flatness means that there is little influence when the output fluctuation and / or the external power supply voltage approaches the internal power supply voltage with respect to the load fluctuation.

An example of the nMOS regulator generated power supply will be described with reference to FIG. The nMOS regulator generation power source of FIG. 6A is composed of pMOS51, pMOS52, and nMOS.
54, an nMOS 55n, a MOS 56, a first driver 57 including a pMOS 53, a second driver 61 including an nMOS 59, a Vth canceller 62 including a diode-connected nMOS 60, and a resistance element 63. The pMOS 51 and the pMOS 52 form a current mirror circuit, and the nMOS 54 and the nMOS 55 are included.
And the nMOS 56 form a differential amplifier 58.
FIG. 6A can be simply illustrated as FIG. 6B.

In the nMOS regulator generation power supply of FIG. 6A, the reference potential Vref and the feedback voltage Vin are applied to the differential amplifier 58. Vth canceller 6
2 exists, the nMOS 59 of the second driver 61 is present.
The voltage of (Vin + Vth) is applied to the gate of the
This means that the output of the th canceller 62 is reduced in potential by Vth. ). Therefore, n
Since a potential Vth lower than the gate potential of the nMOS 59 is output from the source of the MOS 59, the voltage Vin can be obtained.

In operation, the output voltage (Vin + Vth) of the first driver 57 is the Vth canceller 62.
Then, it becomes Vin and is applied to the differential amplifier 58. The differential amplifier 58, the first driver 57, and the Vth canceller 62 control the reference voltage Vref and the output Vin of the Vth canceller 62 so that they have the same potential. as a result,
Finally, the output voltage of the driver 57 (Vin + Vt
h) becomes (Vref + Vth), and from the source of the nMOS 59 to the gate potential of the nMOS 59 is Vt.
It is possible to obtain a voltage having the same potential as the reference voltage Vref which is a low potential.

If the Vth canceller 62 is not provided, (Vref-Vth) is output from the second driver 61, and since the output voltage is related to Vth, the output voltage Vii is an output that depends on temperature. Become.

Since the nMOS regulator generation power supply of FIG. 6 does not feed back the output voltage Vii of the driver 61, it becomes a voltage dependent on the load current and fluctuates with respect to the load current. Further, depending on the operating state, when the power supply voltage Vcc of the driver 61 fluctuates and approaches the output voltage Vii, the drain-source voltage (Vds) of the nMOS 59 becomes small, and there is a problem that the flatness deteriorates. The driver 61 is composed of an nMOS and has an external power supply voltage V
The stability of cc against noise is high. However, if the drive capability is reduced to operate (operate in the low voltage region),
The influence on the fluctuation of the external power supply voltage Vcc is small. The output of the driver 57 does not fluctuate, and the responsiveness of the differential amplifier 48 is not required. Therefore, the differential amplifier 48 has μA
The order is sufficient and the current consumption is small.

The nMOS regulator generated power source has the advantage of high noise resistance, but has the disadvantage of low flatness of the output voltage.

[0021]

As described above, the pMOS
The regulator generated power supply has a high flatness of generated voltage,
While it has the advantage of being easy to save area, it has the disadvantage of high noise impact and high power consumption. Further, the nMOS regulator generated power source has an advantage of high noise resistance, but has a disadvantage of low generated voltage flatness.

As described above, the pMOS regulator generation power supply and the nMOS regulator generation power supply have advantages and disadvantages, respectively. From the viewpoint of the external power supply voltage operating in a wide range, the pMOS regulator generation power supply is concerned about the influence of noise on the high voltage side, and the nMOS regulator generation power supply has a problem in stability due to variation in a region where the external power supply voltage is low. is there.

In the pMOS regulator generation power source,
There is a problem that the current consumption during standby is large.

The present invention has been made in view of the above problems, and has a small influence of noise at high voltage, no variation in voltage at low voltage, and a small current consumption during standby, and a semiconductor integrated circuit and a power supply. The purpose is to provide a supply method.

[0025]

In order to solve the above problems, the present invention employs means for solving the problems having the following features.

According to a first aspect of the present invention, in a semiconductor integrated circuit having a step-down means for stepping down an external power supply voltage to a predetermined internal power supply voltage, a first step-down power supply, a second step-down power supply, and the first step-down power supply are provided. A switching means for switching between the output of the first step-down power supply and the output of the second step-down power supply, and the switching means sets the first step-down power supply to an internal circuit when the external power supply voltage is higher than a predetermined voltage. And the external power supply voltage is lower than a predetermined voltage, the second step-down power supply is switched to be supplied to the internal circuit.

According to the invention described in claim 1, when the external power supply voltage is higher than a predetermined voltage, the first step-down power supply is supplied to the internal circuit, and when the external power supply voltage is lower than the predetermined voltage. By switching the second step-down power supply to supply to the internal circuit, only the part having good characteristics of the two step-down power supplies can be used, the influence of noise at high voltage is small, and the voltage at low voltage is small. It is possible to provide a semiconductor integrated circuit having no variation.

According to a second aspect of the present invention, in the semiconductor integrated circuit according to the first aspect, there is provided a clamp means for clamping the external power supply voltage to a predetermined voltage, and at the standby time, the clamp means provides a predetermined voltage. The voltage clamped at is supplied to the internal circuit.

According to the second aspect of the present invention, during standby, the clamp means supplies a voltage clamped to a predetermined voltage to the internal circuit, thereby preventing wasteful power consumption during standby. be able to.

According to a third aspect of the present invention, in the semiconductor integrated circuit according to the first or second aspect, the first step-down power supply is an nMOS regulator generation power supply, and the second
The step-down power supply of is a pMOS regulator generation power supply.

According to the invention described in claim 3, the first
The step-down power supply is an nMOS regulator generation power supply, and the second step-down power supply is a pMOS regulator generation power supply, thereby providing a semiconductor integrated circuit in which the influence of noise at high voltage is small and there is no voltage variation at low voltage. be able to.

According to a fourth aspect of the present invention, in the semiconductor integrated circuit according to the third aspect, the pMOS regulator generating power source sets a step-down power source voltage generating circuit for generating a step-down power source voltage and an external power source voltage to predetermined voltages. The pMOS regulator generating power supply outputs the step-down power supply voltage generated by the step-down power supply voltage generation circuit when active, and stops the operation of the step-down power supply voltage generation circuit when not active. However, the external power supply voltage clamped to a predetermined voltage by the clamp means is output.

According to the invention described in claim 4, pM
The OS regulator generation power supply has a step-down power supply voltage generation circuit that generates a step-down power supply voltage and a clamp unit that clamps an external power supply voltage to a predetermined voltage. The pMOS regulator generation power supply is a step-down power supply voltage generation circuit when active. The generated step-down power supply voltage is output, and when it is not active, the operation of the step-down power supply voltage generation circuit is stopped, and the external power supply voltage clamped to a predetermined voltage by the clamp means is output, so that the pMOS regulator generated power supply is characterized. It can be used in a good condition, and the problem of current consumption during standby in the pMOS regulator generated power supply can be eliminated.

According to a fifth aspect of the present invention, in the semiconductor integrated circuit according to any one of the first to fourth aspects, there is provided a power supply voltage detecting means for detecting a voltage of the external power supply voltage, and the power supply voltage detecting means. The switching means switches to supply the first step-down power supply and the second step-down power supply to an internal circuit based on the output of the means.

According to the invention described in claim 5, based on the output of the power supply voltage detection means, the switching means is
By switching the first step-down power supply and the second step-down power supply to supply to the internal circuit, it is possible to automatically select the power supply suitable for the external power supply voltage based on the connected external power supply.

According to a sixth aspect of the present invention, in the semiconductor integrated circuit according to the fifth aspect, the power supply voltage detecting means includes a comparing means for comparing a voltage of the external power supply voltage with a predetermined voltage, and the comparing means. A latch circuit for latching the output of the means, and a switch circuit that can be connected between the output part of the latch circuit and the ground potential of the semiconductor integrated circuit, and when the external power supply voltage exceeds a predetermined voltage, When a detection signal is output from the output section of the latch circuit and the external power supply voltage is equal to or lower than a predetermined voltage, the switch circuit is turned on,
As the output of the power supply voltage detecting means, a ground potential is output from the output section of the latch circuit.

According to the sixth aspect of the invention, the power supply voltage detecting means is provided for both the nMOS regulator generating power supply and the pMOS regulator generating power supply by providing the latch circuit and the switch circuit at the output portion thereof. can do.

According to a seventh aspect of the invention, in the semiconductor integrated circuit according to any one of the first to fourth aspects, there is provided control means for controlling switching of the switching means,
The control means is characterized in that the control content is determined at the mask generation stage in the semiconductor integrated circuit.

According to the invention described in claim 7, it is possible to set only the power source suitable for the power source voltage used in the mask generation step. As a result, it is possible to use a step-down power supply suitable for the external power supply used during actual use. In addition, in actual use, the voltage of the external power supply voltage is not detected, and an error such as an erroneous detection can be prevented.

The invention described in claim 8 is the semiconductor integrated circuit according to any one of claims 1 to 4, further comprising control means for controlling switching of the switching means,
The control means has a fuse, and the control content of the control means is determined based on melting / non-melting of the fuse.

According to the invention described in claim 8, in the test stage, it can be set so that only the power source suitable for the actually used power source voltage is used. As a result, it is possible to use a step-down power supply suitable for the external power supply used during actual use. In addition, in actual use, the voltage of the external power supply voltage is not detected, and an error such as an erroneous detection can be prevented.

According to a ninth aspect of the present invention, two step-down power sources for stepping down the external power source voltage to a predetermined internal power source voltage are provided.
A power supply method in a semiconductor integrated circuit, comprising a switching means for switching the outputs of the two step-down power supplies,
The switching means supplies the first step-down power supply to the internal circuit when the external power supply voltage is higher than a predetermined voltage, and supplies the second step-down power supply to the internal circuit when the external power supply voltage is lower than the predetermined voltage. It is characterized by switching to supply to.

The invention described in claim 10 is claim 9
In the power supply method described above, the external power supply voltage clamped to a predetermined voltage is supplied to the internal circuit during standby.

The invention according to claim 9 or 10 is the same as claim 1.
8 is a power supply method suitable for a semiconductor integrated circuit having a step-down means for stepping down the external power supply voltage to a predetermined internal power supply voltage.

[0045]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings. FIG. 7 is a block example of the present embodiment. That is, the block of FIG. 7 includes a pMOS regulator generation power source 71 and an nMOS regulator generation power source 7
2, an internal circuit 73, a first transfer gate 74, and a second transfer gate 75. These circuits are one in the semiconductor integrated circuit, or in a place where a stable power supply circuit is required in the semiconductor integrated circuit,
Any number may be provided.

NMOS regulator generated power source 72 (first
Step-down power supply) and pMOS regulator generation power supply (second
The Vdet signal controls the first transfer gate 74 and the second transfer gate 75 so as to connect the internal circuit 73 to the step-down power supply of FIG.

Regarding the Vdet signal, referring to FIG.
As will be described later, this is a signal that becomes a high level signal “H” when the external power supply voltage is high. Therefore, when the external power supply voltage is high, the second transfer gate 75 is turned on and the first transfer gate 74 is turned off, so that the power of the nMOS regulator generation power supply 72 is supplied to the internal circuit 73. . When the external power supply voltage is low, the second transfer gate 75 is turned off and the first transfer gate 74 is turned on. Therefore, the internal circuit 73 is supplied with the power of the pMOS regulator generation power supply 71. .

As described above, when the external power supply voltage is higher than the predetermined voltage, the nMOS regulator generation power supply 72 is supplied to the internal circuit 73, and when the external power supply voltage is lower than the predetermined voltage, the pMOS regulator generation power supply 71 is supplied. By switching to supply to the internal circuit 73, it is possible to obtain a power supply circuit in which the influence of noise at high voltage is small and there is no voltage variation at low voltage.

An example of the pMOS regulator generation power source used in FIG. 7 will be described with reference to FIG. The nMOS regulator generation power supply used in FIG. 7 can use the nMOS regulator generation power supply of FIG.

PMOS41, pMOS42, pMOS43, nM in the pMOS regulator generation power supply of FIG.
The circuit including the OS 44, the nMOS 45, and the nMOS 46 is the same as that in FIG. PMO of FIG.
The S regulator generated power source is the same as the circuit shown in FIG.
It is a circuit to which an OS 81, an nMOS 82, and an inverter 83 are added.

The Vref signal in the figure is a reference voltage generated for the step-down power supply 12 by the reference voltage generator 11 in FIG. 2, for example, as in FIG. 5A. Further, the Active signal in the figure is a signal output from the logic circuit 3 to the power supply circuit 4 and the memory core 1 as shown in FIG. 9, and when an access request to the DRAM is issued from the outside, the DRAM Is a signal generated by the logic circuit 3 when a refresh request is issued.

When activated, the active signal becomes a high level signal "H", the pMOS 81 turns off, the nMOS 46 turns on, and the nMOS 82 turns off. As a result, pMOS41, pMOS42, pMO
S43, nMOS44, nMOS45 and nMOS46
The pMOS regulator generated power supply equivalent to that in FIG. 5 configured in the same manner operates as in FIG.

When the signal becomes inactive, the active signal becomes the low level signal "L", the pMOS 81 is turned on, the nMOS 46 is turned off, and the nMOS 46 is turned off.
82 is turned on.

Since the nMOS 46 is turned off, the drain sides of the differential amplifiers 44 and 45 float, and the pMOS 81
Is turned on, a current flows from the external power supply Vcc to the source of the nMOS 44 in addition to the current mirror circuits 41 and 42, and the differential amplifiers 44 and 45 stop functioning as differential amplifiers.

Since the nMOS 82 is turned on, p
The output voltage Vii of the MOS regulator generated power supply is (V
cc-Vth).

According to the circuit shown in FIG. 8, only pMO is activated in the active state.
By operating the S regulator generation power supply, the problem of power consumption is eliminated, and when the pMOS regulator generation power supply is inactive, its output is clamped to (Vcc-Vth), so the problem of power consumption when inactive is eliminated. be able to.

A voltage detection circuit for outputting a high level signal "H" when the external power supply voltage is higher than a predetermined voltage will be described with reference to FIG.

In the voltage detection circuit of FIG. 10A, a resistance element 91 (its resistance value: R91), a resistance element 92 (its resistance value: R92), a resistance element 93, and n-stage diode-connected nMOS94 ₁ ... nMOS94 _N , differential amplifier 9
5, inverter 96, nMOS101, nMOS10
2, the latch circuit 103 and the inverter 104. The latch circuit 103 includes a pMOS 97,
It is composed of an nMOS 98, a pMOS 99 and an nMOS 103.

External power supply voltage Vcc is divided by resistance element 91 and resistance element 92 to obtain voltage Vc.
c '(Vcc' = Vcc × R92 / (R91 + R9
2)) is applied to the inverting input terminal of the differential amplifier 95. On the other hand, the non-inverting input terminal of the differential amplifier 95 has n-stage diode-connected nMOS94 _{1 to} nMOS94.
The _N, the voltage of the N × Vth is applied.

When Vcc ′> = N × Vth (1), the differential amplifier 95 outputs a low level “L” signal. This "L" signal is inverted by the inverter 96, and a high level "H" signal is applied to the gate of the nMOS 101 and the inverter 104. nMOS10
The "H" signal applied to the gate of 1 is applied to the latch circuit 10
3 is applied as an “L” signal, and the latch circuit 103 outputs an “H” signal. In addition, the inverter 104
The "H" signal applied to the inverter is inverted by the inverter 104, and the "L" signal is applied to the gate of the nMOS 102. As a result, the nMOS 102 is turned off. As a result, the voltage detection circuit outputs the "H" signal.

On the other hand, when Vcc ′ <N × Vth (2), the differential amplifier 95 outputs a high level “H” signal. The "H" signal is inverted by the inverter 96, and the "L" signal is applied to the gate of the nMOS 101 and the inverter 104. The “L” signal applied to the gate of the nMOS 101 is applied to the latch circuit 103 as an “H” signal, and the latch circuit 103 outputs the “L” signal.

Further, the "L" signal applied to the inverter 104 is inverted by the inverter 104 and the nMO signal is output.
The "H" signal is applied to the gate of S102. As a result, the nMOS 102 is turned on, and the signal of the ground potential Vss is output as the Vdet signal.

As a comparison signal in the differential amplifier 95,
Since the Vth level of the diode is used, this voltage detection circuit is affected by temperature, but the latch circuit 103
Is provided and the level is further shifted to suppress the level fluctuation in the detection output. This voltage detection circuit is
The circuit is easy to use because it can be used for the OS regulator generation power supply and the pMOS regulator generation power supply.

FIG. 10B shows the voltage range in which Vdet is detected. Thus, it is effective when there is an unused area of Vcc.

The determination of the Vdet signal at the mask generation stage in the semiconductor integrated circuit will be described with reference to FIG. In this case, at the stage of creating the semiconductor integrated circuit,
This is the case when the operating voltage of the external power supply voltage used for this semiconductor integrated circuit is already known. Two kinds of masks are prepared at the mask generation stage in the semiconductor integrated circuit so that a signal of Vdet corresponding to the external power supply voltage used can be obtained.

FIG. 11A shows two switches SW0 and SW provided between the external power supply voltage Vcc and the ground voltage Vss.
1 and an inverter 105. Two masks are prepared at the mask generation stage in the semiconductor integrated circuit. As shown in FIG. 11B, when the external power supply voltage is low, the switch SW0 is turned on and the switch SW1 is turned off. Mask with. On the other hand, when the external power supply voltage is high, masking is performed by selecting a mask that turns off the switch SW0 and turns on the switch SW1.

As a result, as the Vdet signal, a low level signal "L" can be obtained when the external power supply voltage is low, and a high level signal "H" can be obtained when the external power supply voltage is high.

Instead of obtaining the Vdet signal corresponding to the external power supply voltage used as described above, two masks are prepared at the mask generation stage in the semiconductor integrated circuit, for example, , In FIG. 7, Vd
The first transfer gate 74 and the second transfer gate 75 themselves controlled by the et signal may be controlled (modified). That is, when the external power supply voltage is low, masking is performed by selecting a mask that turns on or off the first transfer gate 74 and turns off or disconnects the second transfer gate 75. On the other hand, when the external power supply voltage is high, the first transfer gate 7
4 is turned off or cut off, and the second transfer gate 7
Masking is performed by selecting a mask that connects or short-circuits 5.

The determination of the Vdet signal in the semiconductor integrated circuit, for example, at the test stage will be described with reference to FIG. In this case, the used voltage of the external power supply voltage for using the semiconductor integrated circuit is already known at the test stage of the semiconductor integrated circuit. In the test stage of the semiconductor integrated circuit, the fuse is melted / unmelted so that a signal of Vdet corresponding to the external power supply voltage used can be obtained.

The circuit of FIG. 12 has pMOS111, nMO.
S112, pMOS113, pMOS114, nMOS
115, pMOS 116, nMOS 117 and fuse 118. In addition, pMOS111, n
The MOS 112 and the fuse 118 are circuits for setting the fuse state, and include the pMOS 113, the pMOS 114, and the nM.
The OS 115, the pMOS 116, and the nMOS 117 form a latch circuit.

As shown in FIG. 12B, when the external power supply voltage is low, the fuse is unmelted, while when the external power supply voltage is high, the fuse is melted. As a result, V
As the det signal, a low level signal "L" can be obtained when the external power supply voltage is low, and a high level signal "H" can be obtained when the external power supply voltage is high.

The operation of FIG. 12A will be described. First, the case where the fuse is not melted will be described. nMOS11
2 and the gate of pMOS113, s generated at startup
The ttz signal is received from the control circuit. The sttz signal is a signal that outputs a positive signal for a predetermined period at startup. At startup, a positive signal is applied to the gate of the nMOS 112, so that the nMOS 112 becomes conductive and the pMOS 113 becomes non-conductive. As a result, the point P of the latch circuit becomes the ground potential Vss, and the latch circuit is reset. Then
After a lapse of a predetermined time, the sttz signal becomes a low level signal. Then, the gate of the pMOS111, the nMOS
Since a low-level signal is applied to the gate of 112 and the gate of pMOS 113, the nMOS 112 becomes non-conductive and the pMOS 111 and pMOS 113 become conductive.
In this state, the external power supply voltage V
Power is supplied from cc through the pMOS 111 and goes to a high level “H”. As a result, a low level “L” signal is always obtained at the point Q of the output of the latch circuit.

On the other hand, the case where the fuse is melted will be described. Similarly, at the time of startup, a positive signal is applied to the gate of the nMOS 112, so that the nMOS 112 becomes conductive, the point P of the latch circuit becomes the ground potential Vss, and the latch circuit is reset. Next, after a lapse of a predetermined time, the sttz signal becomes a low level signal, and the nMOS 11
2 becomes non-conductive, and the pMOS 111 becomes conductive. In this state, the external power supply voltage Vcc is applied to the point P of the latch circuit.
Therefore, the power is supplied from the pMOS 111, but the fuse is melted and the point P maintains the low level state. As a result, a high level "H" signal is always obtained at the point P of the output of the latch circuit.

A specific example applied to a DRAM will be described with reference to FIGS. 13 and 14. FIG. 13 is a circuit diagram showing a part of the memory core of FIG. The sense amplifier circuit amplifies the signals of the cell array A and the cell array B. BT0, B
The cell array processed by the sense amplifier circuit is selected by the signal applied to the line T1. Memory cell is nM
It is composed of an OS 121 and a capacitor 122. n
The word line (WL) supplies Vpp to the gate of the MOS 121. The source of the nMOS 121 is connected to the bit line (BL), and the drain of the nMOS 121 is connected to the capacitor 122. In addition,
The cell plate potential is supplied to the other end of the capacitor 122. The write operation and the read operation of the memory cell are performed by a well-known method. Here, the description will focus on the power supplied.

The PSA line and the NSA line are supplied with the internal power supply voltage (Vii) and Vss generated by the pMOS regulator generation power supply 71 or the nMOS regulator generation power supply 72. PM for the bit lines (BL, / BL)
OS111, pMOS112, nMOS113 and nM
Via the OS 114, the internal power supply voltage (Vii), Vss
Is supplied. Based on the control signal applied to the BRS line, the precharge potential Vpr of the VPR line is applied to the bit lines (BL, / BL) at a predetermined timing.

The read operation will be briefly described with reference to FIG. When the sense amplifier is inactive, the BRS signal is supplied to the BRS line in order to control the bit line to the Vpr level. The cell array connection of the sense amplifier circuit shared by the left and right cell arrays is selected by the signal applied to the lines BT0 and BT1. The logic circuit generates a request signal based on a read request for reading data from the capacitor 122 of the memory cell, whereby the WL signal of the word line is activated and becomes the Vpp level. When Vpp is applied to the gate of the nMOS 121, the charge (data) of the capacitor 122 is read (X). Vii and Vs supplied from PSA line and NSA line
Amplified data is obtained on the bit lines (BL, / BL) by the signal s (Y). The read data is output via the DB line.

[0077]

As described above, according to the present invention, there is provided a semiconductor integrated circuit and a power supply method in which the influence of noise at a high voltage is small, there is no voltage variation at a low voltage, and the current consumption in standby is small. Can be provided.

[0078]

[Brief description of drawings]

FIG. 1 is a diagram for explaining a conventional semiconductor integrated circuit.

FIG. 2 is a diagram for explaining power supplied by a power supply circuit.

FIG. 3 is a diagram for explaining a relationship among voltages output from a step-down power source, a boost power source, a precharge power source, and a negative power source when an external power source is turned on.

FIG. 4 is a diagram for explaining a reference voltage generation circuit in the reference voltage generator.

FIG. 5 is a diagram for explaining an example of a pMOS regulator generated power supply.

FIG. 6 is a diagram for explaining an example of an nMOS regulator generated power supply.

FIG. 7 is an example of a block configuration diagram for explaining the present embodiment.

FIG. 8 is a diagram for explaining an example of a pMOS regulator generation power source used in FIG. 7.

FIG. 9 is a diagram for explaining an active signal.

FIG. 10 is a diagram for explaining an example of a voltage detection circuit.

FIG. 11 is a diagram for explaining a circuit for obtaining a signal of a predetermined Vdet by using a mask.

[Fig. 12] Predetermined Vde depending on whether the fuse is melted or not melted
It is a figure for demonstrating the circuit which obtains the signal of t.

FIG. 13 is a diagram for explaining a specific example applied to a DRAM.

FIG. 14 is a diagram for explaining a read operation.

[Explanation of symbols]

1 memory core 2 Interface circuit 3 logic circuits 4 power supply circuit 5 Semiconductor integrated circuits (DRAM) 6 Internal circuit 11 Reference voltage generator 12 Step-down power supply 13 Step-up power supply 14 Precharge power supply 15 Negative voltage source 57 First Driver 58 Differential amplifier 61 Second driver 62 Vth canceller 71 pMOS regulator power supply 72 nMOS regulator power supply 73 Internal circuit 74,75 Transfer Gate 103 Latch circuit

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03K 19/00 H01L 21/82 SF term (reference) 5F038 AV06 AV12 AV13 AV15 BB01 BB08 DF05 DF08 EZ20 5F064 BB14 BB35 CC09 DD34 EE45 FF08 FF27 FF36 FF48 5H420 NB02 NB16 NC02 NC26 NE26 5J056 AA00 BB17 BB40 CC00 CC04 CC10 CC12 CC14 DD13 DD28 DD29 DD51 DD60 GG06 KK01 5M024 AA14 AFF22 FF30 FF29 FF30 FF29 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02 FF29FF02FFFFFF20FFFFFF20FF

Claims (10)

[Claims] 1. A semiconductor integrated circuit having a step-down means for stepping down an external power supply voltage to a predetermined internal power supply voltage, wherein a first step-down power supply, a second step-down power supply, an output of the first step-down power supply and the Switching means for switching the output of the second step-down power supply, the switching means supplies the first step-down power supply to the internal circuit when the external power supply voltage is higher than a predetermined voltage, and the external power supply voltage A semiconductor integrated circuit, wherein when the voltage is lower than a predetermined voltage, the second step-down power supply is switched to be supplied to the internal circuit. 2. A clamp means for clamping the external power supply voltage to a predetermined voltage, wherein the clamp means supplies the voltage clamped to the predetermined voltage to the internal circuit during standby. 2. The semiconductor integrated circuit according to item 1. 3. The first step-down power supply is an nMOS regulator generation power supply, and the second step-down power supply is pMO.
3. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is an S regulator generation power source. 4. The pMOS regulator generation power source,
A step-down power supply voltage generation circuit that generates a step-down power supply voltage and a clamp unit that clamps an external power supply voltage to a predetermined voltage, and the pMOS regulator generation power supply is a step-down power supply generated by the step-down power supply voltage generation circuit when active. 4. The semiconductor integrated circuit according to claim 3, wherein a voltage is output, and when it is not active, the operation of the step-down power supply voltage generation circuit is stopped and the external power supply voltage clamped to a predetermined voltage by the clamp means is output. circuit. 5. A power supply voltage detecting means for detecting a voltage of the external power supply voltage, wherein the switching means is configured to control the first step-down power supply and the second step-down power supply based on an output of the power supply voltage detecting means. 5. The semiconductor integrated circuit according to claim 1, wherein the power supply is switched so as to be supplied to an internal circuit. 6. The power supply voltage detection means includes a comparison means for comparing the voltage of the external power supply voltage with a predetermined voltage, a latch circuit for latching an output of the comparison means, an output section of the latch circuit, and And a switch circuit that can be connected between the ground potential of the semiconductor integrated circuit, when the external power supply voltage exceeds a predetermined voltage, the detection signal is output from the output unit of the latch circuit, the external power supply voltage is 6. The semiconductor integrated circuit according to claim 5, wherein when the voltage is equal to or lower than a predetermined voltage, the switch circuit is turned on, and the ground potential is output from the output section of the latch circuit as an output of the power supply voltage detecting means. . 7. The control means for controlling the switching of the switching means, wherein the control means determines the control content at a mask generation stage in a semiconductor integrated circuit.
5. The semiconductor integrated circuit according to claim 4. 8. A control unit for controlling switching of the switching unit, the control unit having a fuse, and the control content of the control unit is determined based on melting / non-melting of the fuse. 5. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is a semiconductor integrated circuit. 9. A power supply method in a semiconductor integrated circuit, comprising: two step-down power supplies for stepping down an external power supply voltage to a predetermined internal power supply voltage; and switching means for switching outputs of the two step-down power supplies. The means supplies the first step-down power supply to the internal circuit when the external power supply voltage is higher than a predetermined voltage, and supplies the second step-down power supply to the internal circuit when the external power supply voltage is lower than the predetermined voltage. A power supply method characterized by switching to 10. The power supply method according to claim 9, wherein an external power supply voltage clamped to a predetermined voltage is supplied to the internal circuit during standby.