JPH1027027A - Internal voltage dropping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an internal voltage dropping circuit which can supply an internal power-supply voltage stably maintained at a level by suppressing the dropping of the internal powersupply voltage caused by the fluctuation of the current consumption in an internal circuit which uses the internal power- supply voltage as operating power. SOLUTION: A differential amplifier 10 outputs a control voltage VOUT by differentially amplifying the voltage levels of a reference voltage VREF and internal power-supply voltage VDD by using first external power-supply voltage VCC and second external power-supply voltage VBB having a negative potential. A PMOS PT3 receives the control voltage VOUT through its gate and supplies the voltage VOUT to the internal power-supply voltage VDD from the first external power-supply voltage VCC.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a reference voltage in a semiconductor device, and more particularly to an internal step-down circuit for generating an internal power supply voltage by lowering an external power supply voltage.

[0002]

2. Description of the Related Art In a semiconductor memory device, with an increase in storage capacity, higher density and higher integration have been promoted. The technology for realizing the high density and the high integration is the technology for miniaturizing the constituent elements.

[0003] However, while the miniaturization of the constituent elements is progressing,
The insulated gate type electric field transistor (hereafter,
MOS transistors) have been reduced. Therefore, if a power supply voltage received from the outside as an operating power supply voltage is applied to a MOS transistor as it is, the MOS transistor exceeds its withstand voltage capability, so that it is not possible to sufficiently secure the reliability such as the withstand voltage of the insulating film.

For this reason, for example, a dynamic semiconductor memory device of 16 Mbits or more (hereinafter referred to as DRAM)
In such a case, the reliability of each component is ensured by operating each component using an internal power supply voltage internally reduced from an external power supply voltage.

FIG. 11 is a schematic block diagram showing an overall configuration of a DRAM 90 as an example of a conventional semiconductor memory device. 11, DRAM 90 includes an internal voltage down converter 91, an internal circuit 92, and an external power supply use circuit 93.

Internal voltage down converter 91 lowers external power supply voltage VCC applied on the VCC power supply node to generate internal power supply voltage VDD on the VDD power supply node.

The internal circuit 92 operates using the internal power supply voltage VDD on the VDD power supply node as an operation power supply. An example of such an internal circuit 92 is a memory cell array including a plurality of MOS transistors as constituent elements.

The external power supply use circuit 93 operates using the external power supply voltage VCC on the VCC power supply node as an operation power supply.
As such an external power supply use circuit 93, a circuit for inputting / outputting data is exemplified.

The internal step-down circuit 91, the internal circuit 92, and the external power supply use circuit 93 use a power supply voltage VSS (hereinafter referred to as a ground voltage) different from the external power supply voltage VCC.
Receive from power supply node.

Therefore, in the memory cell array which is the internal circuit 92, the MOS transistor which is a component thereof receives the internal power supply voltage VDD obtained by stepping down the external power supply voltage VCC as an operation power supply voltage.

That is, even if the density of the memory cell array is increased and the integration thereof is advanced and the MOS transistor as a constituent element is miniaturized and the withstand voltage is reduced, the voltage applied to the gate insulating film can be kept low. The reliability of the elements can be ensured, and reliable and stable operation can be expected as the whole DRAM 90.

FIG. 12 is a circuit diagram showing a configuration of the conventional internal voltage down converter 91 shown in FIG. In FIG.
The internal step-down circuit 91 includes a differential amplifier 11 and a P-channel M
OS transistor (hereinafter, referred to as PMOS) PT3.

The differential amplifier 11 receives the internal power supply voltage VDD, which is the output of the internal voltage down converter 91, at its positive input, and receives a reference voltage VR from a reference voltage generating circuit (not shown) at its negative input.
Receive EF. Differential amplifier 11 differentially amplifies reference voltage VREF and internal power supply voltage VDD to output node 1
Outputs the control voltage VOUT from the controller.

The PMOS PT3 adjusts the voltage level of the internal power supply voltage VDD on the VDD power supply node by supplying a current from the VCC power supply node to the VDD power supply node under the control of the control voltage VOUT.

As shown in FIG. 12, the differential amplifier 11 is a current mirror type differential amplifier including PMOSs PT1 and PT2, N-channel MOS transistors (hereinafter referred to as NMOS) NT1 and NT2, and a constant current source circuit I2. Is configured.

[0016] PMOS PT1 and NMOS NT1
And the PMOS PT2 and the NMOS NT2 are connected in parallel with each other, and both are connected between the VCC power supply node and one terminal of the constant current source I2.

NMOS NT1 receives at its gate the reference voltage VREF, while NMOS NT2 receives at its gate the internal power supply voltage VDD on the VDD power supply node.

The constant current source circuit I2 has the other terminal connected to V
Connect to SS power supply node. The constant current source circuit I2 is NM
The current amount of the differential amplifier 11 is controlled such that the sum of the current amount flowing from the OS NT1 and the current amount flowing from the NMOS NT2 always becomes a constant value.

A control voltage VOUT of the differential amplifier 11 is output from an output node 1 which is a connection point between the PMOS PT1 and the NMOS NT1.

On the other hand, PMOS PT2 and NMOS NT
A connection node 2 which is a connection point with the PMOS PT1
And PMOS PT2.

The differential amplifier 11 has an external power supply voltage VC
When the voltage level of internal power supply voltage VDD rises above reference voltage VREF using C and ground voltage VSS as an operation power supply, the voltage level of output node 1, that is, control voltage VO
The UT is raised up to the voltage level of the external power supply voltage VCC at the maximum.

As a result, the PMOS PT3 receiving the control voltage VOUT at its gate has a large channel resistance,
The current supply from the VCC power supply node to the DD power supply node is reduced to lower the voltage level of the internal power supply voltage VDD.

On the other hand, when the internal power supply voltage VDD becomes lower than the reference voltage VREF, the differential amplifier 11 lowers the control voltage VOUT to the ground voltage VSS (= 0V) at a minimum.

As a result, the PMOS PT3 conducts, and V
The current supply from the CC power supply node to the VDD power supply node is increased to increase the voltage level of the internal power supply voltage VDD.

That is, the internal step-down circuit 91 feeds back the internal power supply voltage VDD, compares it with the reference voltage VREF, and controls the power supply driving PMOS PT3 with the control voltage VOUT obtained by amplifying the result. It operates to keep VDD at a constant voltage level, that is, a reference voltage level.

[0026]

However, FIG.
In the internal step-down circuit 91, the internal power supply voltage VDD, which is the output of the internal step-down circuit 91, is operated by the operation state of the internal circuit 92, and the voltage level of the internal power supply voltage VDD remains substantially lower than the reference voltage VREF. There is a problem that the voltage level of the reference voltage VREF as the value cannot be secured. Hereinafter, this problem will be specifically described.

When the internal circuit 92 operates, VD
Assume that the current on the D power supply node has been consumed.

As described above, the internal step-down circuit 91 in FIG. 12 receives the change in the voltage level on the VDD power supply node, and when the internal power supply voltage VDD becomes lower than the reference voltage VREF, reduces the control voltage VOUT. The power supply driving PMOS PT3 is turned on.

FIG. 13 is a timing chart of the control voltage VOUT and the internal power supply voltage VDD in the conventional internal voltage down converter 91. The vertical axis indicates voltage V, and the horizontal axis indicates time.

During the period from time t1 to t2, the internal circuit 92
Operating period. Here, it is assumed that the current consumption from the VDD power supply node of the internal circuit 92 is large.

In this case, the control voltage VOUT changes at time t1
In response to the decrease in internal power supply voltage VDD, the voltage level is lowered, and the supply of current from PMOS PT3 to the VDD power supply node is promoted.

However, as described above, the voltage of output node 1, that is, control voltage VOUT, is equal to ground voltage VSS (=
0V).

As a result, the amount of current that can be supplied from the VCC power supply node to the VDD power supply node is limited by the influence of the channel resistance of PMOS PT3 receiving control voltage VOUT at its gate.

The difference ΔV between the internal power supply voltage VDD and the reference voltage VREF between times t1 and t2 in FIG. 13 indicates this result.

That is, in the internal voltage down converter 91 of the conventional example in FIG. 12, the internal power supply voltage VDD is changed to the reference voltage VRE.
When the power supply voltage is greatly reduced with respect to F, there is a problem that even if the external power supply voltage VCC is held, the voltage level cannot be restored to the target reference voltage VREF.

As a result, the operation of the internal circuit 92 using the internal power supply voltage VDD as an operation power supply is seriously affected.

The present invention has been made in order to solve the above-mentioned problem. Even when the current consumption in an internal circuit using an internal power supply voltage as an operation power supply becomes large, the internal power supply voltage having a stable voltage level can be obtained. It is an object of the present invention to provide an internal step-down circuit for supplying the voltage.

[0038]

An internal step-down circuit according to claim 1 steps down a first external power supply voltage on a first node to generate an internal power supply voltage on a second node. An internal step-down circuit for operating an internal circuit with a power supply voltage, comprising: a comparison unit that differentially amplifies and outputs a result of comparing an internal reference voltage with an internal power supply voltage on a second node; Step-down means for receiving the first external power supply voltage and the first external power supply voltage to generate the internal power supply voltage on the second node by lowering the first external power supply voltage. And a second external power supply voltage having a different negative potential as an operating power supply.

The internal step-down circuit according to claim 2 is based on claim 1
Control means connected to a third node connecting the comparing means and the step-down means, and selectively stepping down an output of the comparing means based on a logic level of a clock signal indicating an operation state of the internal circuit. Further included.

The internal step-down circuit according to claim 3 is based on claim 2
In the internal step-down circuit, the control means receives a clock signal on one electrode, and the other electrode is a capacitor connected to the third node.

The internal step-down circuit according to claim 4 is based on claim 2
In the internal step-down circuit, the control means uses the first external power supply voltage and the second external power supply voltage as operation power supplies, and inverts and amplifies the voltage level of the clock signal; and gates the output of the level shift circuit. , An insulated gate field-effect transistor having one conduction terminal connected to the third node and the other conduction terminal receiving a second external power supply voltage.

According to a fifth aspect of the present invention, in the internal step-down circuit of the first aspect, the comparing means is a sense amplifier, the step-down means is connected to one of the conductive terminals to the first node, and connected to the other conductive terminal. An insulated-gate field-effect transistor connected to the second node and having a gate connected to the third node.

According to a sixth aspect of the present invention, there is provided an internal step-down circuit which steps down a first external power supply voltage on a first node to generate an internal power supply voltage on a second node, and controls the internal circuit with the internal power supply voltage. An internal step-down circuit to be operated, comprising: an internal reference voltage;
Comparison means for differentially amplifying and outputting the result of comparison with the internal power supply voltage on the second node, and step-down means for lowering the first external power supply voltage to generate the internal power supply voltage on the second node And control means connected between the comparing means and the step-down means, for controlling the step-down means based on the output of the comparing means.

The internal step-down circuit according to claim 7 is based on claim 6
In the internal step-down circuit, the control means uses the first external power supply voltage and the second external power supply voltage having a negative potential different from the first external power supply voltage as an operation power supply, and inverts the output of the comparison means. An inverter circuit that amplifies and outputs the output signal, and a constant current source circuit connected between the inverter circuit and a node that receives the second external power supply voltage.

The internal step-down circuit according to claim 8 is based on claim 6
In the internal step-down circuit, the comparing means is a sense amplifier using the first external power supply voltage and the ground voltage as operating power supplies, the step-down means has one conduction terminal connected to the first node, and the other conduction terminal connected to the other conduction terminal. An insulated gate type electric field transistor connected to the second node and having its gate receiving the output of the inverter circuit.

According to a ninth aspect of the present invention, there is provided an internal voltage step-down circuit which steps down a first external power supply voltage on a first node to generate an internal power supply voltage on a second node. An internal step-down circuit to be operated, comprising: an internal reference voltage;
A comparison means for differentially amplifying and outputting the result of comparison with the internal power supply voltage on the second node, and receiving the control of the output of the comparison means to lower the first external power supply voltage and A step-down unit that generates the internal power supply voltage; and a reference voltage control unit that selectively switches a voltage level of an internal reference voltage based on a logic level of a clock signal indicating an operation state of an internal circuit.

According to a tenth aspect of the present invention, in the internal step-down circuit according to the ninth aspect, the reference voltage control means receives the clock signal at the gate and receives the first reference voltage at one of the conduction terminals. A first insulated gate type electric field transistor for outputting an internal reference voltage from the other conduction terminal, an inverter circuit for inverting a clock signal, and a gate receiving an output of the inverter circuit and having a voltage level different from the first reference voltage. A second insulated gate electric field transistor that receives the second reference voltage at one conduction terminal and outputs an internal reference voltage from the other conduction terminal.

An internal step-down circuit according to claim 11 is the internal step-down circuit according to claim 9, wherein the comparing means is a sense amplifier using the first external power supply voltage and the ground voltage as operating power supplies,
A step-down means having one of the conduction terminals connected to the first node;
The other conduction terminal is connected to the second node, and an insulated gate type electric field transistor receiving the output of the comparison means at its gate.

According to a twelfth aspect of the present invention, in the internal step-down circuit according to the ninth aspect, the comparing means includes the first external power supply voltage and the second external power supply voltage having a negative potential different from the first external power supply voltage. A sense amplifier using an external power supply voltage as an operating power supply; and a step-down means having one conductive terminal connected to the first node, the other conductive terminal connected to the second node, and a gate of the comparison means connected to its gate. It is an insulated gate type electric field transistor that receives an output.

[0050]

BEST MODE FOR CARRYING OUT THE INVENTION

[First Embodiment] FIG. 1 is a circuit diagram showing an entire configuration of an internal voltage down converting circuit 100 according to a first embodiment of the present invention. Components in common with the conventional example of FIG. The reference numerals are used and the description is omitted.

Internal voltage down converter 100 according to the first embodiment
12 is different from the conventional example of FIG.
1 receives the ground voltage VSS as one operation power supply voltage, whereas the differential amplifier 10 of FIG. 1 receives an operation voltage VBB having a negative potential.

That is, the differential amplifier 11 shown in FIG.
Does not fall below 0V, but the voltage level at the output node 1 of the differential amplifier 10 in the first embodiment of FIG. 1 falls below 0V.

FIG. 2 shows internal power supply voltage VDD and control voltage VO of internal voltage down converter 100 according to the first embodiment of the present invention.
It is a timing chart figure of UT.

During the period from time t1 to t2, the internal circuit 92
The operation period of FIG. Here, it is assumed that current consumption from the VDD power supply node of internal circuit 92 is large.

In this case, control voltage VOUT, which is the voltage of output node 1, can be reduced to a negative potential.

As a result, the channel resistance of the PMOS PT3 receiving the control voltage VOUT at its gate becomes smaller than the channel resistance of the PMOS PT3 in FIG. 12 in which the control voltage VOUT does not fall below the ground voltage VSS (= 0V).

That is, in the internal step-down circuit 100 of the first embodiment, the effect of the channel resistance of the power supply driving PMOS PT3 can be suppressed.

Therefore, FIG.
13 can supply a larger amount of current to the VDD power supply node than in the conventional example of FIG. 13, the voltage level decrease ΔV1 of the internal power supply voltage VDD with respect to the reference voltage VREF between time t1 and t2 is smaller than ΔV in FIG. (ΔV1 <ΔV).

That is, even when the current consumption of internal circuit 92 increases, internal step-down circuit 100 operates at internal power supply voltage VD of a voltage level very close to reference voltage VREF.
D can be provided.

[Second Embodiment] FIG. 3 is a circuit diagram showing an overall configuration of an internal voltage down converting circuit 200 according to a second embodiment of the present invention. The reference numerals are used and the description is omitted.

Internal voltage down converter 200 according to the second embodiment
However, the difference from the conventional example of FIG. 12 is that, like Embodiment 1, differential amplifier 10 receives operating voltage VBB having a negative potential instead of ground voltage VSS, and includes capacitor C1.

The output node of the capacitor C1 is connected to the node 3 which is a connection point between the differential amplifier 10 and the PMOS PT3, and the input node 4 receives a signal (hereinafter referred to as a / PB signal) from the outside. .

Here, the control voltage VOUT output from the differential amplifier 10 falls to the negative potential as described in the first embodiment.

On the other hand, upon receiving the / PB signal at L level from input node 4, capacitor C1 receives the voltage on node 3, ie, control voltage V, by its charge pump function.
OUT is further reduced.

Here, as the / PB signal, for example, a signal generated in the DRAM when the memory cell array of the DRAM, which is one of the internal circuits 92, operates, that is, DRA.
A signal indicating the operation status of the M memory cell array is given.

A DRAM (not shown) has a plurality of memory cells, and the memory cells are connected by word lines in the row direction and by bit lines in the column direction. Each memory cell is 1
By specifying the row address of 1 and the column address of 1,
One word line and one bit line are activated and specified. Internal power supply voltage VDD is used to specify the memory cell and perform a data read operation or the like.

A / RAS signal (RAS indicates a row address strobe signal) as a clock signal for controlling the activation of the word line, and a / CAS (CAS for CAS) is a clock signal for controlling the activation of the bit line. Column address strobe signal).

When the / RAS signal shifts from the H level to the L level, a row-related circuit (not shown) is activated. Subsequently, when the / CAS signal shifts from the H level to the L level, a column-related circuit (not shown) is activated to perform a read operation of a specific memory cell and the like.

First, the clock buffer 96 in the DRAM
A signal synchronized with the / RAS signal in which the occurs occurs as the / PB signal. This / PB signal receives a row address and generates an internal row address signal (not shown).
Controls the row address buffer in the.

FIG. 4 shows clock buffer 96 and / RA
FIG. 4 is a schematic block diagram illustrating a relationship between an S signal and a / PB signal.

Further, FIG. 5 shows the / RAS signal when the / PB signal in FIG.
FIG. 4 is a timing chart illustrating a relationship between a B signal and a control voltage VOUT.

In FIG. 5, when the / RAS signal shifts from the H level to the L level at time t1, the clock buffer 96 receiving the signal shifts to the H level (= VDD) at time t2.
To the L level (= VSS). When this is input to the capacitor C1, the voltage level of the node 3 is further reduced by the charge pump function, and accordingly, the channel resistance of the PMOS PT3 is further reduced.

As a result, even if the current consumption from the VDD power supply node increases during the operation period of the memory cell array, the power supply driving PMOS of the internal voltage down converter 200
The amount of current supplied from above the VCC power supply node to above the VDD power supply node via the PT3 can be sufficiently ensured compared to the conventional example of FIG. Therefore, a decrease in internal power supply voltage VDD with respect to reference voltage VREF (ΔV2) can be suppressed to a small value (ΔV2 <ΔV).

Further, as the / PB signal, a signal obtained by inverting the CDE signal (column decoder activating signal) can be mentioned. This CDE signal is a signal generated in the internal control circuit 97 in the DRAM, and activates a column decoder in the DRAM (not shown). Here, the column decoder decodes an internal column address signal from the address buffer and selects a column (bit line) of the memory cell.

FIG. 6 is a schematic block diagram showing the relationship among the internal control circuit 97, the / RAS signal, the / CAS signal, the CDE signal, and the / PB signal. Where inverter N
2 inverts the CDE signal.

FIG. 7 shows a / RAS signal when the / PB signal in FIG. 6 is input to the capacitor C1, and a / C signal.
AS signal, CDE signal, / PB signal and control voltage V
FIG. 4 is a timing chart illustrating a relationship with OUT.

In FIG. 7, at time t1, the / RAS signal shifts from the H level to the L level, and at time t2, the / CAS signal shifts from the H level to the L level. In response,
At time t3, the internal control circuit 97 generates a CDE signal. This CDE signal is inverted by the inverter N2 / PB
When a signal is input to the capacitor C1, the voltage level of the node 3 is lower than that of the conventional example of FIG. 12 due to the charge pump function.

Therefore, as in the case of FIGS. 4 and 5,
When the current consumption from the VDD power supply node increases due to the operation of the memory cell array of the DRAM, the internal power supply voltage VDD decreases with respect to the reference voltage VREF (△ V3)
Can be kept small (小 さ く V3 <△ V).

From the above results, even when the current consumption of the internal circuit 92 increases, the internal voltage down converting circuit 200 can provide the internal power supply voltage VDD at a voltage level very close to the reference voltage VREF.

[Third Embodiment] FIG. 8 is a circuit diagram showing an entire configuration of an internal voltage down converter 300 according to a third embodiment of the present invention. Components common to FIG. 1 have the same reference numerals and the same components. And the description thereof is omitted.

Internal voltage down converter 300 according to the third embodiment
12 is different from the conventional example of FIG. 12 in that differential amplifier 10 receives operating voltage VBB having a negative potential instead of ground potential VSS as in the first embodiment.
NT3 and a level shift circuit 20.

The level shift circuit shown in FIG.
SPT4, PT5, NMOS NT4, NT5 and inverter N1.

The PMOS PT4 and the NMOS NT4 are connected in series, and the PMOS PT5 and the NMOS NT5 are connected.
Are connected in series.

One of the conduction terminals of PMOSs PT4 and PT5 is both connected to the VCC power supply node, while
One of the conduction terminals of NT4 and NT5 is connected to the VBB power supply node.

The gate of the PMOS PT4 is a PMOS
It is connected to a connection node 5 corresponding to a connection point between PT5 and NMOS NT5. On the other hand, the gate of the PMOS PT5 is connected to a connection node 4 corresponding to a connection point between the PMOS PT4 and the NMOS NT4.

The gate of NMOS NT4 receives the / PB signal input from the outside. On the other hand, the gate of NMOS NT5 receives a signal obtained by inverting the / PB signal by inverter N1. Therefore, according to the logic level of the / PB signal, one of the NMOSs NT4 and NT5 is turned on and the other is turned off.

The NMOS NT3 has one conduction terminal connected to the node 3 corresponding to the connection point between the differential amplifier 10 and the PMOS PT3, and the other conduction terminal connected to the operating voltage VB.
B is connected to a VBB power supply node. further,
The gate of the NMOS NT3 is connected to the connection node 4 of the level shift circuit 20.

As the / PB signal, there is a signal indicating the operation status of the memory cell array of the DRAM described with reference to FIGS.

Here, the clock buffer 96 shown in FIG.
The operation of internal step-down circuit 300 according to the third embodiment will be described assuming that the / PB signal output from is input to level shift circuit 20.

As described above, the / PB signal is output from the DRAM
When the row-related circuit is activated, it shifts from H level to L level.

If the voltage level of the / PB signal is at the H level, NMOS NT4 becomes conductive (NMOS NT5 becomes non-conductive), and the voltage level of connection node 4 becomes operating voltage V.
Take a negative value according to BB. As a result, PMOS PT5 receiving the voltage of connection node 4 at its gate conducts, and the voltage level of connection node 5 takes a positive value according to external power supply voltage VCC. On the other hand, PMOS PT4 receiving the voltage of connection node 5 at its gate becomes non-conductive, so that the voltage level of connection node 4 holds a negative value.

In this case, NMOS NT3 receiving the negative voltage of ground node 4 at its gate is non-conductive, so that the voltage level of node 3 (= control voltage VOUT) does not change.

However, if the voltage level of the / PB signal is at the L level, the NMOS NT5 becomes conductive (NMOS
NT4 is turned off), and the voltage level of connection node 5 takes a negative value according to operating voltage VBB. As a result, PMOS PT4 which receives the voltage of connection node 5 at its gate conducts, and the voltage level of connection node 4 becomes external power supply voltage VC.
Take a positive value according to C. On the other hand, the PMOS PT5 that receives the voltage of the connection node 4 at its gate becomes non-conductive,
The voltage level of connection node 5 holds a negative value.

In this case, NMOS NT3, which receives the positive voltage of connection node 4 at its gate, conducts. As a result, the voltage level of node 3 (= control voltage VOUT) becomes NMO
Negative operating voltage VBB at one conduction terminal of SNT3
Go down according to.

That is, if the current consumption from the VDD power supply node increases during the operation of the DRAM memory cell array, the control voltage VO output from the differential amplifier 10
Although the UT drops to the negative potential as described in the first embodiment, the voltage level is further lowered by the NMOS NT3. In response to this, compared to the conventional example of FIG.
, The current supply from the VCC power supply node to the VDD power supply node can be sufficiently ensured.

Therefore, a decrease in internal power supply voltage VDD with respect to reference voltage VREF (ΔV4) can be suppressed to a small value (ΔV4 <ΔV).

[Fourth Embodiment] FIG. 9 is a circuit diagram showing an entire configuration of an internal voltage down converter 400 according to a fourth embodiment of the present invention. Components in common with FIG. And the description thereof is omitted.

Internal voltage down converter 400 according to the fourth embodiment
Is different from the conventional example in that a differential amplifier 12 is used in place of the differential amplifier 11,
In other words, the inverter circuit 30 and the constant current source circuit I3 are included between the OSPT3. Here, the differential amplifier 12 outputs the control voltage VOUT from the connection node 2, and the output node 1 is connected to the respective gates of the PMOSs PT1 and PT2. Here, for simplicity, the connection node 2 is replaced with the output node 2 and the output node 1 is replaced with the connection node 1.

The inverter circuit 30 includes a PMOS PT6
And NMOS NT6, and each gate is connected to output node 2. In addition, PMOS PT6 and NM
A connection node 4 which is a connection point with the OSNT 6 is a PMOS.
Connected to the gate of PT3.

One conduction terminal of PMOS PT6 is connected to VC
Connected to the C power supply node, one conduction terminal of NMOS NT6 is connected to one terminal of constant current source circuit I3. Further, the other terminal of constant current source circuit I3 is connected to a VBB power supply node.

When the voltage level of internal power supply voltage VDD rises above reference voltage VREF, differential amplifier 12 lowers the voltage level of output node 2, ie, control voltage VOUT. On the other hand, when the voltage level of internal power supply voltage VDD falls below reference voltage VREF, control voltage VOUT increases.

On the other hand, the inverter circuit 30 controls the control voltage V
OUT is inverted and amplified, and the power supply driving PMOS PT3 is controlled via the connection node 4.

The constant current source circuit I3 is a PMOS P
The amount of current flowing through T6 and NMOS NT6 is adjusted.

Here, the operation of internal voltage down converter 400 in the fourth embodiment will be described. When the voltage level of the internal power supply voltage VDD is higher than the reference voltage VREF, the differential amplifier 12 lowers the control voltage VOUT. This control voltage V
PMOS PT6 receiving OUT at its gate conducts,
Similarly, NMOS NT6 received at the gate is rendered non-conductive, and raises the voltage level of connection node 4 in accordance with external power supply voltage VCC. As a result, the power-supply driving PMOS PT3 receiving this at the gate becomes nonconductive and reduces the current supply from the VCC power supply node to the VDD power supply node.

On the other hand, when the internal circuit 92 operates to consume current from the VDD power supply node, the internal power supply voltage VDD on the VDD power supply node falls below the reference voltage VREF. In response, the differential amplifier 12 increases the control voltage VOUT. PMOS receiving this control voltage VOUT at its gate
PT6 becomes non-conductive, and also receives NMOS at the gate
NT6 conducts, and lowers the voltage level of connection node 4 according to negative operating voltage VBB. As a result, the channel resistance of power supply driving PMOS PT3 receiving the gate thereof is smaller than that of the conventional example of FIG. 12, so that a sufficient amount of current can be supplied from above the VCC power supply node to above the VDD power supply node. it can.

Therefore, even when the current consumption from the VDD power supply node increases, the reference voltage VRE
A decrease in internal power supply voltage VDD with respect to F (ΔV5) can be suppressed (ΔV5 <ΔV).

[Fifth Embodiment] FIG. 10 is a circuit diagram showing the entire structure of an internal voltage down converter 500 according to a fifth embodiment of the present invention. And the description thereof is omitted.

Internal voltage down converter 500 according to the fifth embodiment
The difference from the conventional example of FIG.
Is to include.

The reference voltage control circuit 40 in FIG.
It includes a PMOS PT7, a PMOS PT8, and an inverter circuit N3.

The PMOS PT7 has, on one conductive terminal, a reference voltage VRE generated from a reference voltage generation circuit (not shown).
Receiving the F _H, receiving external from / PB signal at its gate.

The PMOS PT8 has one conduction terminal connected to a reference voltage VRE generated from a reference voltage generation circuit (not shown).
Receiving the F _L, receiving a signal obtained by inverting the receiving / PB signal from the outside to the gate with an inverter circuit N3. here,
Have a relationship of VREF _H> VREF _L.

Further, another conduction terminal of PMOS PT7 and another conduction terminal of PMOS PT8 are connected at input node 5. Input node 5 is NMOS of differential amplifier 11
Connected to the gate of NT1.

As the / PB signal, there is a signal indicating the operation status of the memory cell array of the DRAM described in FIGS. 4 and 6 of the second embodiment.

Here, the clock buffer 96 shown in FIG.
The operation of internal step-down circuit 500 in the fifth embodiment will be described assuming that the / PB signal output from FB is input to reference voltage control circuit 40.

As described above, the / PB signal shifts from the H level to the L level when the row circuit of the DRAM is activated.

[0116] In this case, the PMOS PT7 is conducting (PMOS PT8 is nonconductive), the voltage level of the input node 5 becomes VREF _H. Therefore, the differential amplifier 11
Reference voltage VREF is at a high voltage level (= VREF
F _H ).

On the other hand, while the / PB signal is at the H level, the PMOS PT8 is conductive (the PMOS PT7 is nonconductive), and the voltage level on the input node 5 is at VREF _L. Therefore, the reference voltage VREF of the differential amplifier 11
Are set to a low voltage level (= VREF _L ).

That is, while the DRAM memory cell array is not operating, reference voltage VREF is set to a low voltage level.

On the other hand, if VREF _H is set to a value higher than the reference voltage VREF of the conventional example of FIG. 12, while the memory cell array of the DRAM operates by consuming the current on the VDD power supply node of the internal voltage down converter 500, Reference voltage VREF
Is set to a higher voltage level than usual, so that even if the current consumption increases, a decrease in the voltage level of the internal power supply voltage VDD (△ V6) can be suppressed (△ V6 <△).
V).

Note that a configuration using the differential amplifier 10 instead of the differential amplifier 11 may be used.

[0121]

As described above, in the internal voltage down converter of the present invention, even when the current consumption in the internal circuit using the internal power supply voltage as the operating power supply increases, the internal power supply voltage at a stable voltage level is obtained. Can be supplied.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an overall configuration of an internal voltage down converter according to a first embodiment of the present invention.

FIG. 2 is a timing chart of an internal power supply voltage and a control voltage of the internal step-down circuit according to the first embodiment of the present invention.

FIG. 3 is a circuit diagram showing an overall configuration of an internal voltage down converter according to a second embodiment of the present invention.

FIG. 4 is a schematic block diagram showing a relationship among a clock buffer, a / RAS signal, and a / PB signal.

FIG. 5 shows the / RAS signal and / PB when the / PB signal is input to capacitor C1 according to the second embodiment of the present invention.
FIG. 4 is a timing chart illustrating a relationship between a signal and a control voltage.

FIG. 6 is a schematic block diagram showing a relationship among an internal control circuit, a / RAS signal, a / CAS signal, a CDE signal, and a / PB signal.

FIG. 7 shows the / RAS signal and / CA when the / PB signal is input to capacitor C1 according to the second embodiment of the present invention.
FIG. 4 is a timing chart illustrating a relationship among an S signal, a CDE signal, a / PB signal, and a control voltage.

FIG. 8 is a circuit diagram showing an entire configuration of an internal voltage down converter according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing an overall configuration of an internal voltage down converter according to a fourth embodiment of the present invention.

FIG. 10 is a circuit diagram showing an overall configuration of an internal voltage down converter according to a fifth embodiment of the present invention.

FIG. 11 is a schematic block diagram showing the entire configuration of a conventional DRAM.

FIG. 12 is a circuit diagram showing a configuration of a conventional internal voltage down converter.

FIG. 13 is a timing chart of a control voltage and an internal power supply voltage in a conventional internal voltage down converter.

[Explanation of symbols]

91, 100, 200, 300, 400, 500 Internal step-down circuit, 20 level shift circuit, 30 inverter circuit, 40 reference voltage control circuit, 10, 11, 12 differential amplifier, 90 DRAM, 92 internal circuit, 93 using external power supply Circuit, 96 clock buffer, 97 internal control circuit, PT1 to PT8 P channel MOS transistor, NT1 to NT6 N channel MOS transistor, N1, N2, N3 inverter circuit, I2, I3
Constant current source circuit, C1 capacitor.

Claims (12)

[Claims] 1. An internal step-down circuit for stepping down a first external power supply voltage on a first node to generate an internal power supply voltage at a second node, and operating an internal circuit with the internal power supply voltage. Comparison means for differentially amplifying and outputting the result of comparing an internal reference voltage with the internal power supply voltage on the second node; receiving the output of the comparison means, Step-down means for stepping down to generate the internal power supply voltage on the second node, wherein the comparing means includes: a first external power supply voltage; and a negative potential different from the first external power supply voltage. An internal step-down circuit using a second external power supply voltage as an operating power supply. 2. The method according to claim 1, further comprising: a third node connected to said comparing means and said step-down means, for selectively stepping down an output of said comparing means based on a logic level of a clock signal indicating an operation state of said internal circuit. 2. The internal step-down circuit according to claim 1, further comprising control means for performing the operation. 3. The internal step-down circuit according to claim 2, wherein said control means receives said clock signal at one electrode, and said other electrode is a capacitive element connected to said third node. 4. A level shift circuit that inverts and amplifies a voltage level of the clock signal using the first external power supply voltage and the second external power supply voltage as an operation power supply, and the level shift circuit. 3. An insulated gate field-effect transistor receiving the output of the gate of the first transistor, connecting one conductive terminal to the third node, and the other conductive terminal including the second external power supply voltage. Internal buck circuit. 5. The comparison means is a sense amplifier, and the step-down means connects one conduction terminal to the first node, connects the other conduction terminal to the second node, and sets a gate thereof. 2. The internal step-down circuit according to claim 1, wherein the internal step-down circuit is an insulated gate type electric field transistor that connects the third node to the third node. 6. An internal step-down circuit for lowering a first external power supply voltage on a first node to generate an internal power supply voltage on a second node and operating an internal circuit with the internal power supply voltage. Comparing means for differentially amplifying and outputting a result of comparing an internal reference voltage with the internal power supply voltage on the second node; and reducing the first external power supply voltage to generate the second node. An internal step-down circuit including: a step-down unit for generating the internal power supply voltage; and a control unit connected between the comparison unit and the step-down unit, for controlling the step-down unit based on an output of the comparison unit. . 7. The comparison means according to claim 1, wherein said control means uses said first external power supply voltage and a second external power supply voltage having a negative potential different from said first external power supply voltage as an operation power supply. 7. The internal voltage step-down circuit according to claim 6, further comprising: an inverter circuit that inverts and amplifies an output to output the constant current source circuit connected between the inverter circuit and a node receiving the second external power supply voltage. 8. The comparing means is a sense amplifier using the first external power supply voltage and a ground voltage as operating power supplies, and the step-down means connects one conduction terminal to the first node, Connecting the other conduction terminal to the second node;
7. The internal step-down circuit according to claim 6, wherein the gate is an insulated gate type electric field transistor receiving an output of the inverter circuit. 9. An internal step-down circuit that steps down a first external power supply voltage on a first node to generate an internal power supply voltage on a second node and operates an internal circuit with the internal power supply voltage. Comparing means for differentially amplifying and outputting the result of comparing an internal reference voltage with the internal power supply voltage on the second node; and receiving the control of the output of the comparing means, Step-down means for stepping down a power supply voltage to generate the internal power supply voltage on the second node; and selectively selecting a voltage level of the internal reference voltage based on a logic level of a clock signal indicating an operation state of the internal circuit. And a reference voltage control means for switching to the internal voltage step-down circuit. 10. The first reference voltage control means receives a clock signal at a gate, receives a first reference voltage at one conduction terminal, and outputs the internal reference voltage from the other conduction terminal. An insulated gate electric field transistor; an inverter circuit for inverting the clock signal;
10. A second insulated-gate field-effect transistor receiving a second reference voltage having a voltage level different from that of the second reference voltage at one conduction terminal and outputting the internal reference voltage from the other conduction terminal. Internal buck circuit. 11. The comparison means is a sense amplifier using the first external power supply voltage and a ground voltage as operation power supplies, and the step-down means connects one conduction terminal to the first node, 10. The internal step-down circuit according to claim 9, wherein the other step-down terminal is an insulated gate type electric field transistor connected to the second node and receiving the output of the comparing means at its gate. 12. The sense amplifier using the first external power supply voltage and a second external power supply voltage having a negative potential different from the first external power supply voltage as an operation power supply. The step-down means connects one conduction terminal to the first node, and connects the other conduction terminal to the second node;
10. The internal step-down circuit according to claim 9, wherein the internal step-down circuit is an insulated gate type electric field transistor whose gate receives the output of the comparing means.