JP2002083494A - Semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve such a problem that current consumption can be reduced as much as possible at the time of a standby mode and required voltage can be generated quickly when a mode is restored to an operation mode. SOLUTION: First and second voltage dropping circuits 11, 12 are operate simultaneously at the time of an operation mode, and only the first voltage dropping circuit is operated at the time of a standby mode. The first and the second voltage dropping circuits are stopped together at the time of a stop mode, and only a stop circuit is operated. The stop circuit 13 charges an output node OUT to slightly lower voltage than voltage at the time of the operation mode and the standby mode.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit applied to, for example, a portable device which requires particularly low power consumption, and more particularly to a semiconductor integrated circuit which consumes almost no current during standby.

[0002]

2. Description of the Related Art Semiconductor integrated circuits, especially DRAM (Dynamic RAM), flash memory, ferroelectric memory (Ferro electric RAM (hereinafter referred to as FeRAM))
And the like require an internal power supply voltage different from the external power supply voltage. For example, in a FeRAM, a voltage boosted from an external power supply voltage by a booster circuit is supplied to a word line. Further, the internal power supply voltage of the peripheral circuit, the plate line voltage, the bit line voltage, the reference voltage of the dummy cell, and the like are supplied from the external power supply voltage.

FIG. 8A shows a cell array 5 of FeRAM.
1 and an example of the sense amplifier 52 are shown. In the cell array 51, the selection transistor 53 is connected to the bit line BL.
Is connected to one end of the current path of the selection transistor 5.
A capacitor 54 for a ferroelectric memory is connected to the other end of the third current path. The gate of the selection transistor 53 is connected to the word line WL. One end of the current path of the dummy selection transistor 55 is connected to the bit line / BL (/ indicates an inverted signal), and the other end of the current path of the dummy selection transistor 55 is connected to the dummy cell capacitor 56. I have. The gate of the dummy selection transistor 55 is connected to the dummy word line DWL. The sense amplifier 52 is controlled by two control signals SAP and / SAN.

FIG. 8 (b) shows the voltage of each part in FIG. 8 (a). In this example, the external power supply voltage VDD is, for example, 3.3V. The external power supply voltage VDD is boosted by a boosting circuit to generate a boosted voltage VPP, for example, 4 V, and is lowered by a step-down circuit, thereby reducing the internal step-down voltage VINT1, for example, 2.5V,
2, e.g. 2.0 V, internal step-down voltage VDC, e.g.
5V is generated.

A boosted potential VPP is supplied to the word line WL, and an internal step-down voltage VINT1 is supplied as the cell plate voltage VPL of the capacitor 54. The internal step-down voltage VDC is supplied to the dummy word line DWL and the cell plate of the dummy capacitor 55. Further, in sense amplifier 52, control signal SAP uses internal step-down voltage VINT2, and control signal / SAN uses ground voltage VSS. An internal power supply voltage VINT2 is supplied to a peripheral circuit (not shown) inside the chip.

In general, a semiconductor memory device has two modes, a standby mode and an operation mode. The standby mode is a state where the chip enable signal / CE is at a high level and no chip is selected. At this time, if all the circuits operated by the internal power supply voltage can be stopped and the internal power supply voltage can be set to the ground potential (0 V), the current consumed by the internal voltage generation circuit including the booster circuit and the step-down circuit can be reduced. Can be zero.

However, if all the internal power supply voltages are set to zero in the standby mode, it takes time to increase the voltage from 0 V to a desired internal power supply voltage when shifting from the standby mode to the operation mode. That is, the output terminals of the booster circuit and the step-down circuit are connected to a large wiring capacitance and a large wiring resistance.
For this reason, it takes time to raise the potential due to the large CR time constant caused by the wiring capacitance and the wiring resistance. Therefore, it becomes difficult to operate within the range of the specification of the access time required for reading and writing.

Therefore, as one method for avoiding the above problem, a method has been proposed in which the internal power supply voltage is held in a load capacitor in a standby mode. in this case,
The internal power supply voltage is detected by the operational amplifier and the resistance voltage dividing circuit. In order to reduce the current consumption of the operational amplifier and the resistor voltage divider circuit, the current flowing through the operational amplifier is reduced, or a resistor voltage divider circuit having a high resistance is used. However, a slight DC current still flows. Further, when the potential of the load capacitor drops below a desired potential, it is necessary to operate an internal voltage generating circuit including a step-down circuit and a booster circuit to charge the load capacitor to a desired potential. For this reason, it is necessary to consume an alternating current.

As described above, in the case of the method in which the internal voltage is held in the load capacitor, since the direct current and the alternating current are consumed, it is difficult to reduce the current consumption in the standby mode to zero.

FIG. 9 shows an example of a conventional step-down circuit. This step-down circuit includes a first step-down circuit 61 and a second step-down circuit 62.

In the first step-down circuit 61, the control signal S
When W1 is set to the high level, the N-channel MOS transistor 63 is turned on. In this state, the connection node TS of the resistance voltage dividing circuit composed of the high resistances RS1 and RS2
And the reference potential Vref are supplied to the operational amplifier OPS. In the operational amplifier OPS, these potentials are compared and amplified, and the P-channel MOS transistor 64 is driven by the output signal of the operational amplifier OPS. In response to the operation of transistor 64, an internal power supply voltage VINT whose power supply voltage is reduced is generated at output node OUT.

In the second step-down circuit 62, when the control signal SW2 is set to a high level, an N-channel MOS
The transistor 65 is turned on. In this state,
The potential of the connection node TA of the resistance voltage dividing circuit composed of the low resistances RA1 and RA2 and the reference potential Vref are supplied to the operational amplifier OPA. In the operational amplifier OPA, these potentials are compared and amplified, and the P-channel MOS transistor 66 is driven by the output signal of the operational amplifier OPA. According to the operation of transistor 66, output node O
An internal power supply voltage VINT whose power supply voltage is reduced is generated in the UT.

A load capacitor CL is connected to the output node OUT. This load capacitor CL is a wiring capacitance of an internal circuit (not shown).

In the first and second step-down circuits 61 and 62, the resistance value of the resistor constituting the resistor voltage dividing circuit is RS2
> RA2, RS1> RA1, and their ratios are set substantially the same as in the following equation. RS2 / RS1 = RA2 / RA1 Therefore, the same step-down voltage VINT is generated in both the standby mode and the operation mode.

The reason for setting the resistance value of the second step-down circuit 62 as described above is as follows. First, the current flowing through the resistors RA1 and RA2 during operation can be made relatively large. Furthermore, it is required to make the value of the resistor relatively small in order to follow the fluctuation of the power supply during operation.

The switching between the operation mode and the standby mode is performed by a chip control signal. When the chip enable signal / CE is at a low level, the operation mode is set, and the read and write operations are enabled. On the other hand, when the chip enable signal / CE is set to the high level, the standby mode is set.

In the operation mode, an N-channel MOS
The control signals SW1 and SW2 supplied to the gates of the transistors 63 and 65 are both at a high level. Therefore, both the first and second step-down circuits 61 and 62 are operated.

In the standby mode, the control signal S
W1 is at a high level and SW2 is at a low level. Therefore, only the first step-down circuit 61 is operated.

The internal power supply voltage VINT in the standby mode is
It is expressed by the following equation. VINT = [1+ (RS2 / RS1)] · Vref On the other hand, the internal power supply voltage VINT in the operation mode is expressed by the following equation. VINT = [1+ (RA2 / RA1)] · Vref FIG. 10 shows an example of a conventional booster circuit. This booster circuit includes a first voltage limiting circuit 71 for a standby mode, a second voltage limiting circuit 72 for an operation mode, an OR circuit 73,
It has a ring oscillator (ROSC) 74 and a charge pump circuit (CP) 75.

In the first voltage limiting circuit 71, when the control signal SWS is at a high level and / SWS is at a low level, an N-channel MOS transistor 76, a P-channel M
The OS transistor 77 turns on. Accordingly, high resistance R
The potential of the connection node TS of the resistance voltage dividing circuit composed of S1 and RS2 and the reference potential Vref are supplied to the operational amplifier OPS. The operational amplifier OPS compares and amplifies these potentials. When potential TS is lower than reference potential Vref, oscillator activating signal OS output from operational amplifier OPS
CS goes high. This oscillator activation signal O
The SCS is supplied to a ring oscillator 74 via an OR circuit 73. Therefore, the ring oscillator 74 oscillates, the charge pump circuit 75 operates, and the boosted potential VPP
Is generated.

In the second voltage limiting circuit 72, when the control signal SWA is at a high level and / SWA is at a low level, an N-channel MOS transistor 78, a P-channel M
The OS transistor 79 turns on. Accordingly, low resistance R
The potential of the connection node TA of the resistance voltage dividing circuit including A1 and RA2 and the reference potential Vref are supplied to the operational amplifier OPA. The operational amplifier OPA compares and amplifies these potentials. When potential TA is lower than reference potential Vref, oscillator activation signal OS output from operational amplifier OPA
CA goes high. This oscillator activation signal O
The SCA is supplied to a ring oscillator 74 via an OR circuit 73. Therefore, the ring oscillator 74 oscillates, the charge pump circuit 75 operates, and the boosted potential VPP
Is generated.

The first and second voltage limiting circuits 71 and 72
, The resistance value of the resistance constituting the resistance voltage dividing circuit is R
S2> RA2 and RS1> RA1 are set, and these ratios are set to be substantially the same as in the following equation. RS2 / RS1 = RA2 / RA1 Therefore, substantially the same boosted voltage VPP is generated in both the standby mode and the operation mode.

The switching between the operation mode and the standby mode uses the chip enable signal / CE as described above.
In the operation mode, the control signals SWS and SWA are both at a high level. Therefore, both the first and second voltage limiting circuits 71 and 72 are operated.

In the standby mode, the control signal S
WS is at a high level and SWA is at a low level. Therefore, only the first voltage limiting circuit 71 operates.

The boost voltage VPP in the standby mode is represented by the following equation. VPP = [1+ (RS2 / RS1)] · Vref On the other hand, the boosted voltage VPP in the operation mode is expressed by the following equation. VPP = [1+ (RA2 / RA1)]. Vref For example, RS2 = 2.75MΩ, RS1 = 1.25M
If Ω and Vref = 1.25 V (output potential of a band gap reference circuit known as a reference potential generating circuit), VPP = 4 V is obtained. For example, RA2 = 2.
75 kΩ, RA1 = 1.25 kΩ, Vref = 1.25
Assuming V, VPP = 4V is obtained.

[0026]

By the way, the above-mentioned conventional step-down circuit and step-up circuit include the first step-down circuit 61 and the first voltage limiting circuit 7 for the standby mode even in the standby mode.
1 is working. Therefore, since these circuits consume current, it has been difficult to reduce current consumption. In particular, in the case of a device driven by a battery, such as a portable device, when the standby state continues for a long time, the battery voltage is greatly consumed. Therefore, it is desired to develop a semiconductor integrated circuit capable of further reducing current consumption in the standby mode and generating a required voltage at a high speed when returning to the operation mode.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce current consumption in a standby mode as much as possible. It is an object of the present invention to provide a semiconductor integrated circuit capable of generating a required voltage at high speed.

[0028]

In order to solve the above problems, a semiconductor integrated circuit according to the present invention sets an output node to a first potential at least in a standby mode, and suspends operation for a longer period than in the standby mode. A first potential setting circuit that is stopped in the sleep mode, and a second potential setting circuit that charges the output node to a second potential slightly lower than the first potential in the sleep mode. I have.

[0029]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) FIG. 1 shows a first embodiment of the present invention, in which a semiconductor integrated circuit according to the present invention is applied to a step-down circuit. 1, the step-down circuit 10 includes a first step-down circuit 11, a second step-down circuit 12, and a pause circuit 13.

In the first step-down circuit 11, P-channel MOS transistors 21, 22 and resistors RS2, RS are connected between a node to which the external power supply voltage VDD is supplied and ground.
1. An N-channel MOS transistor 23 is connected in series. The resistances RS2 and RS1 form a resistance voltage dividing circuit composed of a high resistance, and the resistance voltage dividing circuit outputs the output node OU.
The potential of T is detected. A control signal SW1 is supplied to a gate of the transistor 23. This control signal S
W1 is the transistor 2 via an inverter circuit I1.
2 gates. The resistors RS2 and RS1
Is connected to the non-inverting input terminal of the operational amplifier OPS. A reference potential Vref is supplied to an inverting input terminal of the operational amplifier OPS. The output terminal of the operational amplifier OPS is connected to the gate of the transistor 21. The connection node between the transistor 22 and the resistor RS2 is connected to the output node OUT.

The first step-down circuit 11 includes a control signal SW
1 is operated at a high level. That is,
When the control signal SW1 is set to the high level, the transistors 22 and 23 are turned on. Then, the resistors RS2 and RS
The potential of the connection node TS and the reference potential Vref of the resistance voltage dividing circuit composed of 1 are supplied to the operational amplifier OPS. These potentials are compared and amplified by the operational amplifier OPS, and the P-channel MOS transistor 21 is driven by the output signal of the operational amplifier OPS. In response to the operation of transistor 21, an internal power supply voltage VINT whose power supply voltage is reduced is generated at output node OUT.

In the second step-down circuit 12, between the node supplied with the external power supply voltage VDD and the ground, P-channel MOS transistors 24 and 25 and resistors RA2 and RA
1. An N-channel MOS transistor 26 is connected in series. The resistors RA2 and RA1 form a resistor voltage dividing circuit composed of a low resistor.
The potential of the UT is detected. The control signal SW2 is supplied to the gate of the transistor 26. This control signal SW2 is supplied to the gate of the transistor 25 via the inverter circuit I2. The resistors RA2 and RA
One connection node TA is connected to the non-inverting input terminal of the operational amplifier OPA. A reference potential Vref is supplied to an inverting input terminal of the operational amplifier OPA. The output terminal of the operational amplifier OPA is connected to the gate of the transistor 24. The connection node between the transistor 25 and the resistor RA2 is connected to the output node OUT.

The second step-down circuit 12 is provided with a control signal SW
2 is operated at a high level. That is,
When the control signal SW2 is set to the high level, the transistors 24 and 25 are turned on. Then, the resistances RA1 and RA
The potential of the connection node TA and the reference potential Vref of the resistance voltage dividing circuit composed of 2 are supplied to the operational amplifier OPA. These potentials are compared and amplified by the operational amplifier OPA, and the P-channel MOS transistor 24 is driven by the output signal of the operational amplifier OPA. In response to the operation of transistor 24, an internal power supply voltage VINT having a reduced power supply voltage is generated at output node OUT.

In the pause circuit 13, the external power supply voltage VDD (or the boosted voltage VP obtained by boosting the power supply voltage VDD) is used.
P) between the node to which P) is supplied and the output node OUT, a P-channel MOS transistor 27, an intrinsic transistor 2 whose threshold voltage is set to approximately 0V,
8, and an N-channel MOS transistor 29 are connected in series. The gate of the transistor 27 is supplied with a control signal DST. The gate of the transistor 28 is connected to a connection node between the transistor 27 and the transistor 28. The gate of the transistor 29 is connected to a connection node between the transistor 28 and the transistor 29. That is, the transistors 28 and 29 are so-called diode-connected. A wiring capacitance CL of an internal circuit (not shown) is connected to the output node OUT.

The pause circuit 13 is operated when the control signal DST is at a low level.

In the first and second step-down circuits 11 and 12, the resistance value of the resistance constituting the resistance voltage dividing circuit is RS2.
> RA2, RS1> RA1, and their ratios are set substantially the same as in the following equation. RS2 / RS1 = RA2 / RA1 Therefore, it is possible to generate the internal power supply voltage VINT substantially the same in both the standby mode and the operation mode.

The present invention has a sleep mode (Deep Stand-by mode) in addition to the operation mode and the standby mode. This sleep mode is set when the operation is stopped for a longer time than in the standby mode. Switching between the operation mode and the standby mode is performed by a chip control signal. If the chip enable signal / CE (not shown) is at a low level, the operation mode is set, and the read and write operations are enabled. On the other hand, when the chip enable signal / CE is set to the high level, the standby mode is set.

The following three conditions can be considered when shifting to the sleep mode. (1) When the standby mode has elapsed for a predetermined time or more, the standby mode is set. In this case, for example, a timer circuit that operates when the chip enable signal / CE is at the high level is provided, and the sleep mode is set when the time set in the timer circuit has elapsed. (2) The sleep mode is set by a command supplied from the outside. (3) An external power supply voltage detection circuit is provided, and when the external power supply voltage falls below the reference voltage by this detection circuit, the sleep mode is set.

In the above operation mode, N channels M
The control signals SW1 and SW2 supplied to the gates of the OS transistors 23 and 26 are both at a high level. Therefore, both the first and second step-down circuits 21 and 22 are operated.

In the standby mode, the control signal S
W1 is at a high level and SW2 is at a low level. Therefore, only the first step-down circuit 11 is operated.

The step-down voltage VINT in the standby mode is expressed by the following equation. VINT = [1+ (RS2 / RS1)] · Vref For example, RS2 = 1.25 MΩ, RS1 = 1.25 M
Assuming that Ω and Vref = 1.25 V (output potential of a band gap reference circuit known as a reference potential generating circuit), 2.5 V is obtained as the step-down voltage VINT.

On the other hand, the step-down voltage VINT in the operation mode
Is represented by the following equation. VINT = [1+ (RA2 / RA1)]. Vref For example, RA2 = 1.25 kΩ, RA1 = 1.25 k
Ω, Vref = 1.25 V, the step-down voltage VINT
As a result, 2.5 V is obtained.

Further, in the sleep mode, the control signal S
Both W1 and SW2 are at low level. The sleep mode is a mode with lower power consumption than the standby mode. Therefore, both the first and second step-down circuits 11, 12 are stopped, and the current flowing through the first and second step-down circuits 11, 12 is reduced to zero. At this time, the control signal DST is set to low level, and the pause circuit 13 is activated. The pause circuit 13 maintains the internal power supply voltage VINT at a voltage slightly lower than the internal power supply voltage VINT in the operation mode or the standby mode.

That is, in the idle mode, when the control signal DST goes low and the transistor 27 is turned on, the internal power supply voltage VINT is given by the following equation. VINT = VDD−VTHI (VINT) −VTHE
(VINT) Here, VTHI (VINT) is the threshold voltage of the intrinsic transistor 28 when the substrate bias effect of VINT is present, and VTHE (VINT) is VI
Transistor 29 when there is a substrate bias effect of NT
Is the threshold voltage. For example, the external power supply voltage VDD = 3.3
V, VTHI (VINT) = 0.3V, VTHE (VI
NT) = 1.0 V, VINT is as follows. VINT = 3.3−0.3−1.0 = 2.0 V When the boosted voltage VPP is supplied to the source electrode of the P-channel MOS transistor 27 instead of the external power supply voltage VDD, the internal power supply voltage VINT Is given by the following equation: VINT = VPP-VTHI (VINT) -VTHE
(VINT) In this case, for example, VDD = 3.3 V, VPP = 3.8
V, VTHI (VINT) = 0.3V, VTHE (VI
NT) = 1.0 V, VINT is as follows. VINT = 3.8-0.3-1.0 = 2.5 V When the above-mentioned pause circuit 13 is used, the internal power supply voltage VINT
Changes according to the variation between the external power supply voltage VDD (or the boosted voltage VPP) and the threshold voltages of the transistors 28 and 29. However, since the pause circuit 13 does not use a feedback circuit like the first and second step-down circuits 11 and 12, a through current does not occur in the resistance voltage dividing circuit. Moreover, the pause circuit 13 only charges the load capacitor CL. Therefore, if there is no current consumption source or leak source in the internal circuit, current consumption can be reduced to zero in the sleep mode.

The internal power supply voltage VINT in the sleep mode is
The present invention is not limited to the first embodiment, but can be set as desired by changing the number of transistors connected in series or changing the threshold voltage of the transistors in the pause circuit 13.

According to the first embodiment, for example, when the standby mode elapses a predetermined time, the standby mode is set, and the first mode is set.
Both the second step-down circuits 11 and 12 are stopped, and the pause circuit 13 is operated. For this reason, in the sleep mode, by charging the load capacitor CL (output node OUT) from the external power supply through the sleep circuit 13, the required internal power supply voltage VINT slightly lower than in the operation mode or the standby mode is supplied to the internal circuit. Supplying. Moreover, this pause circuit 1
In No. 3, when the load capacitor CL is charged, the transistor is turned off, and no current flows. Therefore, in the sleep mode, the power consumption can be further reduced as compared with the conventional standby mode, and the current consumption can be reduced to almost zero. Therefore, for example, in a portable device or the like driven by a battery, the life of the battery can be extended.

Further, in the sleep mode, the internal power supply voltage VINT is maintained at a required voltage slightly lower than that in the operation mode or the standby mode. Therefore, when switching from the sleep mode to the operation mode or the standby mode, it is possible to shift at a high speed.

FIG. 2 shows a modification of the first embodiment.

That is, in the pause circuit 13 of FIG. 1, a PN junction diode D is used instead of the diode-connected transistors 28 and 29. In this case, the internal power supply voltage VINT in the sleep mode can change the number of diodes in series according to a desired potential.

FIG. 3 also shows a modification of the first embodiment. In the first embodiment, in the sleep mode, the output node OUT is set to the internal power supply voltage VINT slightly lower than in the operation mode or the standby mode by the sleep circuit 13. On the other hand, in this modified example, the output node O
The UT is set to the ground potential (0 V).

That is, as shown in FIG. 3, an N-channel M
The OS transistor 30 is connected. The control signal / DST is supplied to the gate of the transistor 30.

In the above configuration, when the sleep mode is set and the control signal / DST is set to the high level, the transistor 30 is turned on. Therefore, output node OUT is set to the ground potential.

In this case, it is not advantageous because it takes time to return from the sleep mode to the operation mode. But,
For example, when returning from the sleep mode to the standby mode, there is no operational problem even if it takes some time. Therefore, the present invention can be applied to a semiconductor integrated circuit having such a return mode. (Second Embodiment) FIG. 4 shows a second embodiment of the present invention. The same parts as those in the first embodiment are denoted by the same reference numerals, and only different parts will be described.

In FIG. 4, first and second step-down circuits 1
Reference numerals 1 and 12 denote boosted voltages VPP obtained by boosting the power supply voltage VDD.
Are supplied as power.

In the first step-down circuit 11, an N-channel MOS transistor 31 is connected between the P-channel MOS transistors 21 and 22. The gate and the drain of the transistor 31 are connected to each other. Further, an N-channel MOS transistor 32 is connected between the node supplied with the power supply voltage VDD and the output node OUT. This transistor 32
Is connected to the drain of the transistor 31. That is, in the first step-down circuit 11, the stepped-down internal power supply voltage VINT is output via the transistor 32.

In the second step-down circuit 12, an N-channel MOS transistor 33 is connected between the P-channel MOS transistors 24 and 25. The gate of the transistor 33 is connected to the transistors 31 and 3
3 is connected to the drain. Further, the power supply voltage VD
An N-channel MOS transistor 34 is connected between the node to which D is supplied and the output node OUT.
The gate of the transistor 34 is the transistor 33
Connected to the drain of That is, in the second step-down circuit 12, the stepped-down internal power supply voltage VINT is output via the transistor.

The transistor 31 and the transistor 32
Are substantially equal, and the source potentials of the transistors 33 and 34 are substantially equal. Transistors 32 and 34 are in a sub-threshold region (triode region)
Works with Therefore, the transistors 32 and 34 can operate at high speed.

Further, between the output node OUT and the ground,
The shunt circuit 35 is connected. The shunt circuit 35 includes a resistor RL and an N-channel MOS transistor 36.
Are connected in series. The control signal DST is supplied to the gate of the transistor 36.

In the case of the circuit shown in FIG. 4, in the standby mode or the operation mode, transistors 32 and 34 operate in the sub-threshold region, and internal power supply voltage VINT is generated via these transistors 32 and 34. Therefore, it is possible to follow a change in the current consumption of the internal power supply voltage VINT more quickly than when the circuit shown in FIG. 1 is used, and to generate a stable internal power supply voltage VINT.
However, the N-channel MOS transistors 32, 34
Is not completely off in the sub-threshold region when there is no load current. Therefore, when no current is consumed in an internal circuit (not shown) connected to output node OUT, the potential of internal power supply voltage VINT gradually increases. To avoid this, shunt circuit 3
5 are provided.

That is, the control signal DST is at a high level in operation modes other than the sleep mode and in the standby mode. Therefore, the transistor 36 is turned on, and the current IL is slightly increased through the transistor 36 and the resistor RL.
Flows. Therefore, an increase in internal power supply voltage VINT is suppressed, and internal power supply voltage VINT is stabilized.

On the other hand, in the sleep mode, the control signal DS
T goes low. Therefore, the transistor 36 is turned off, and the slight current IL is also cut off. For this reason,
In the sleep mode, the output node OUT is connected to the sleep circuit 13
Thus, the internal power supply voltage VINT is charged, and the current consumption is reduced to almost zero.

According to the second embodiment, when the first and second step-down circuits 11 and 12 are circuits operating in the sub-threshold region, the shunt circuit 35 using the control signal DST in the idle mode. Is off.
For this reason, it is possible to prevent a current from flowing through the shunt circuit 35 in the sleep mode. Further, in the sleep mode, the load capacitor CL is charged by the sleep circuit 13, so that the output node OUT can be held at the required internal power supply voltage VINT. (Third Embodiment) FIG. 5 shows a third embodiment of the present invention, and shows an example in which the present invention is applied to a booster circuit. In FIG. 5, the same portions as those in FIG. 10 are denoted by the same reference numerals, and only different portions will be described.

In FIG. 5, a pause circuit 41 is connected to the output node OUT. In this pause circuit 41, a node supplied with power supply voltage VDD and output node O
A P-channel MOS transistor 4 is provided between the UTs.
2. Intrinsic transistors 43 are connected in series. The control signal DST is supplied to the gate of the transistor 42 via an inverter circuit I3, and the control signal DST is supplied to the gate of the transistor 43.

In the above configuration, operations in the operation mode and the standby mode are the same as those of the circuit shown in FIG. That is, in the operation mode, both the first and second voltage limiting circuits 71 and 72 are operated, and in the standby mode, only the first voltage limiting circuit 71 is operated.

On the other hand, in the sleep mode, the control signal SW
S and SWA are both at a low level. Therefore, both the first and second voltage limiting circuits 71 and 72 are stopped. At this time, the control signal DST is set to the high level.
Therefore, both the transistors 42 and 43 are turned on, and the load capacitor CL is connected to the transistors 42 and 43.
3 is charged. At this time, boosted voltage VPP output from output node OUT is set to a voltage substantially equal to power supply voltage VDD.

According to the third embodiment, in the idle mode, the control signals SWS and SWA are both at the low level, and the first and second voltage limiting circuits 71 and 72, the ring oscillator ROSC and the charge pump CP are set. Operation is stopped. Therefore, current consumption by these circuits is reduced to zero. At this time, only the pause circuit 41 is operated, and the output node OUT is connected to the power supply voltage VDD by the pause circuit 41.
Is charged to a voltage substantially equal to. Moreover, the pause circuit 41 is turned off when the load capacitor CL is charged to a voltage substantially equal to the power supply voltage VDD. Therefore, almost no current is consumed. Therefore, the current consumption can be made substantially zero in the sleep mode. Further, since the potential of the output node OUT is maintained at a voltage substantially equal to the power supply voltage VDD in the sleep mode, the boosted voltage VPP can be generated at high speed when the standby mode or the operation mode is restored from the sleep mode. It is. (Fourth Embodiment) FIG. 6 shows a fourth embodiment of the present invention, in which the present invention is applied to a case where there are a plurality of step-down circuits. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different parts will be described.

FIG. 6 shows VINT as the internal power supply voltage.
(2.5 V), VINT2 (2.0 V), VDC (1.
5V), and includes three step-down circuits 101, 102, and 103 for generating these three step-down potentials. Step-down circuit 1
01 is a first step-down circuit 111, a second step-down circuit 12,
A pause circuit 13 is provided. The step-down circuit 102 has a first step-down circuit 112, a second step-down circuit 12, and a pause circuit 13. The step-down circuit 103 includes the first step-down circuit 11
3, a second step-down circuit 12, and a pause circuit 13.

The first step-down circuits 111 to 113 are different from the first step-down circuit 11 shown in FIG.
The difference is that the signals P1, P2, and P3 obtained by inverting the output of S are respectively extracted, and that control signals SW11 to SW13 are input instead of the control signal SW1.

FIG. 7A shows control signals SW11 to SW1.
3 will be described.

As shown in FIG. 7A, the control signal SW1
Each of the circuits for generating 1 to SW13 is formed of two NOR flip-flops.

An RS flip-flop for generating the control signal SW11 has an initialization signal SET and a signal P
3 and an output signal of the other NOR, and a reset signal RST and a signal P1 are supplied to the other NOR.
, And an output signal of one NOR. The output signal of the other NOR is output as the control signal SW11.

The RS flip-flop for generating the control signal SW12 is connected to one NOR by a signal / inverted from the signal P1.
P1 and the output signal of the other NOR are supplied, and the other
A signal / P obtained by inverting the reset signal RST and the signal P2 to R
2 and one NOR output signal are supplied. Then, the output signal of the other NOR is output as the control signal SW12.

An RS flip-flop that generates control signal SW13 has a signal NOR that is obtained by inverting signal P2 in one NOR.
P2 and the output signal of the other NOR are supplied, and the other NO
A signal / P obtained by inverting the reset signal RST and the signal P3 to R
3 and one NOR output signal are supplied. The output signal of the other NOR is output as the control signal SW13.

The initialization signal SET is used at the time of initialization, the reset signal RST is used at the time of termination, and the initialization signal S is used in a steady state.
Both the ET and the reset signal RST are at a low level.

In the operation mode, the control signal SW11
To SW13 and the control signal SW2 are both at a high level. Therefore, both the first step-down circuits 111 to 113 and the second step-down circuit 12 operate. This is the same as in the first embodiment.

In the operation in the standby mode, the control signal SW2 is at the low level. Therefore, the second step-down circuit 12 does not operate. First, the control signal SW11 becomes high level, and the first step-down circuit 111 operates. And
When the internal power supply voltage VINT becomes lower than the reference potential Vref, the output of the operational amplifier OPS goes low, the signal P1 goes high, and the signal / P1 goes low.
When the output of the operational amplifier OPS becomes low level, the transistor 21 is turned on, so that the internal power supply voltage VINT
Is raised to the external power supply voltage VDD. Then, the output of the operational amplifier OPS goes high, the signal P1 goes low, and the signal / P1 goes high. Signal / P1
Becomes high level, the control signal SW11
Is at a low level, and the control signal SW12 is at a high level.
As a result, the first step-down circuit 111 stops, and the first step-down circuit 112 operates.

When the internal power supply voltage VINT2 becomes lower than the reference potential Vref, the output of the operational amplifier OPS goes low, the signal P2 goes high, and the signal / P
2 becomes low level. Then, the internal power supply voltage VINT
2 is raised to the external power supply voltage VDD and the reference potential Vre
Therefore, the output of the operational amplifier OPS goes high, the signal P2 goes low, and the signal / P2 goes high. In response to this, the control signal SW12 signal goes low and the control signal SW13 goes high, the first step-down circuit 112 stops, and the first step-down circuit 113 operates.

Then, the internal power supply voltage VDC is changed to the reference potential V
When it becomes lower than ref, the output of the operational amplifier OPS becomes low level, the signal P3 becomes high level, and the signal / P3 becomes low level. Then, the internal power supply voltage VDC is raised to the external power supply voltage VDD and becomes higher than the reference potential Vref, so that the output of the operational amplifier OPS goes high, the signal P3 goes low, and the signal / P3 goes high. In response to this, the control signal SW13 becomes low level,
The control signal SW11 becomes high level, the first step-down circuit 113 stops, and the first step-down circuit 111 operates. This operation is sequentially repeated.

The operation in the sleep mode is the same as the operation in the first mode.
As described in the embodiment.

As described above, in the fourth embodiment, the three first step-down circuits 111 to 113 are sequentially operated (partially suspended), so that the plurality of step-down circuits can be operated even in the standby mode. It is possible to reduce the power consumption consumed by the operational amplifier and the voltage dividing resistor in the standby mode, as compared with the related art in which each is operated.

The present invention is not limited to the FeRAM, but can be applied to a semiconductor integrated circuit requiring a voltage different from the external power supply voltage, such as a DRAM and a flash memory.

Of course, various modifications can be made without departing from the scope of the invention.

[0083]

As described in detail above, according to the present invention,
In the standby mode, it is possible to provide a semiconductor integrated circuit capable of reducing current consumption to zero and generating a required voltage at high speed when the operation mode is restored.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a modification of the first embodiment.

FIG. 3 is a circuit diagram showing a modification of the first embodiment.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is a circuit diagram showing a fourth embodiment of the present invention.

7A is a block diagram for generating control signals SW11 to SW13, and FIG. 7B is a waveform diagram of main signals shown in FIG.

8A is a circuit diagram illustrating an example of a semiconductor integrated circuit, and FIG. 8B is a diagram illustrating a relationship between voltages applied to the semiconductor integrated circuit illustrated in FIG. 8A.

FIG. 9 is a circuit diagram showing an example of a conventional step-down circuit.

FIG. 10 is a circuit diagram illustrating an example of a conventional booster circuit.

[Explanation of symbols]

 11, 12: first and second step-down circuits, 13: pause circuit, 71, 72: first and second voltage limiting circuits, 41: pause circuit, OUT: output node.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/04 H01L 27/04 GF (72) Inventor Takashi Ogiwara Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa 1st address F-term in Toshiba Microelectronics Center (reference)

Claims (8)

[Claims] A first potential setting circuit for setting an output node to a first potential at least in a standby mode and stopping in a sleep mode in which operation is stopped for a longer period than in the standby mode; And a second potential setting circuit for charging the output node to a second potential slightly lower than the first potential. 2. The circuit according to claim 2, wherein the second potential setting circuit is connected to at least one first transistor connected between a node to which an external power supply voltage is supplied and the output node, and is connected in series with the first transistor. A second transistor that is turned on in the sleep mode, wherein the potential of the output node is set to a potential lower than the external power supply voltage by a threshold voltage of at least one transistor in the sleep mode. The semiconductor integrated circuit according to claim 1. 3. The second potential setting circuit includes a third transistor connected between the output node and a ground potential, wherein the third transistor is turned on during the sleep mode. 2. The semiconductor integrated circuit according to claim 1, wherein said output node is set to a ground potential. 4. The first potential setting circuit comprises a step-down circuit for stepping down a power supply voltage, wherein the step-down circuit detects a potential of the output node by using a resistive voltage dividing circuit. 2. The semiconductor according to claim 1, further comprising: an operational amplifier to which the set potential and the reference potential are supplied; and a fourth transistor that controls the potential of the output node according to an output signal of the operational amplifier. Integrated circuit. 5. The first potential setting circuit comprises a step-down circuit for stepping down a power supply voltage, wherein the step-down circuit detects a potential of the output node, and detects the potential at the output node. An operational amplifier to which the supplied potential and the reference potential are supplied; a fifth transistor having a current amount controlled in accordance with an output signal of the operational amplifier; a mutual connection between the node to which the external power supply voltage is supplied and the output node A sixth transistor formed of an N-channel MOS transistor having a gate potential controlled by the fifth transistor, connected between the output node and ground, being conductive during the operation mode and the standby mode; 2. The semiconductor integrated circuit according to claim 1, further comprising a shunt circuit for suppressing a rise in the potential of the output node. 6. The first potential setting circuit comprises a booster circuit for boosting a power supply voltage, wherein the booster circuit includes a resistor voltage divider circuit for detecting a potential of the output node, and a voltage detected by the resistor voltage divider circuit. An operational amplifier to which the supplied potential and the reference potential are supplied; an oscillation circuit that oscillates according to an output signal of the operational amplifier; a boosted voltage higher than a power supply voltage according to an output signal of the oscillation circuit; 2. The semiconductor integrated circuit according to claim 1, further comprising: a voltage generating circuit that supplies a voltage to an output node. 7. The semiconductor device according to claim 1, wherein a plurality of said first potential setting circuits are provided, and only a part of said plurality of first potential setting circuits is operated in said standby mode. 7. The semiconductor integrated circuit according to item 6. 8. A flip-flop circuit for generating an operation signal for controlling each of the plurality of first potential setting circuits, wherein one of the plurality of first potential setting circuits is provided in accordance with each of the operation signals. 8. The semiconductor integrated circuit according to claim 7, wherein a part of the operation is stopped, and the another first potential setting circuit which has been stopped until then is operated.