JP2015179557A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory that can cause a generation voltage of a voltage generation circuit to rapidly reach a desired voltage value from when starting operation of the voltage generation circuit with a downsized configuration and at low power consumption.SOLUTION: A semiconductor memory comprises: a first transistor Q1 that has a first terminal receiving first potential, a second terminal connected to a first line EN, and a control terminal receiving a control signal CE; a second transistor Q2 that has the first terminal connected to the first line, has second potential applied to the second terminal, and has the control terminal connected to a voltage supply line RL; a third transistor Q3 which has the first potential applied to the first terminal, and has a signal causing a logical level of the control signal to be inverted input into the control terminal; and a fourth transistor Q4 that has the first terminal connected to a second terminal of the third transistor, has the second terminal connected to the voltage supply line, and has the control terminal connected to the first line.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a voltage supply line.

  Currently, semiconductor memories mounted on information control devices such as computers are required to have large capacity, low power consumption, and high speed access. Therefore, in order to reduce the power consumption, the operation of the sense amplifier belonging to the memory block that is not the memory read target and the reference voltage generation circuit that supplies the reference voltage to the sense amplifier is forcibly stopped. A semiconductor memory has been proposed (see, for example, FIG. 2 of Patent Document 1).

  In such a semiconductor memory, when the sense amplifier that has been in the operation stop state becomes a data read target, the operation of the reference voltage generation circuit is started. However, there is a problem that it takes time until the reference voltage actually reaches a desired voltage value after the operation of the reference voltage generation circuit is started.

JP 2000-149469 A

  An object of the present invention is to provide a semiconductor device capable of obtaining a generated voltage that rises to a predetermined voltage value quickly from the start of operation of a voltage generating circuit with a small configuration and low power consumption. And

  A semiconductor device according to the present invention is a semiconductor device having a voltage supply line, and includes a first terminal that receives a first potential, a second terminal connected to the first line, and a control terminal that receives a control signal. A second transistor having a first transistor, a first terminal connected to the first line, a second terminal receiving a second potential, and a control terminal connected to the voltage supply line; A third transistor having a first terminal for receiving the first potential, a control terminal for receiving a signal obtained by inverting the logic level of the control signal, and a second transistor connected to the second terminal of the third transistor. And a fourth transistor having a first terminal, a second terminal connected to the voltage supply line, and a control terminal connected to the first line.

  The semiconductor device according to the present invention is a semiconductor device having a voltage supply line, and includes a first terminal that receives a first potential, a second terminal connected to the first line, and a control terminal that receives a control signal. A second terminal having a first terminal connected to the first line, a second terminal receiving a second potential, and a control terminal connected to the voltage supply line. A third transistor having a transistor, a first terminal that receives the first potential, and a control terminal that receives a signal obtained by inverting the logic level of the control signal, and is connected to the second terminal of the third transistor A fourth transistor having a first terminal connected to the first line; a control terminal connected to the first line; a first terminal connected to a second terminal of the fourth transistor; and the voltage supply. Including a second terminal connected to the in, a fifth transistor having a control terminal for receiving a predetermined fixed potential.

  According to the present invention, when the voltage generator supplies a predetermined voltage to the voltage supply line according to the control signal, the voltage is forcibly and temporarily applied to the voltage supply line. As a result, the voltage rise with time in the voltage riser of the generated voltage becomes steep, so that the generated voltage can be immediately converged to a desired voltage value as a target.

It is a block diagram which shows the internal structure of a semiconductor memory. 2 is a schematic circuit diagram of a reference amplifier 4. FIG. FIG. 3 is a circuit diagram showing an example of a high-speed startup drive circuit 5. 4 is a time chart for explaining the operation of a high-speed startup drive circuit 5 having the circuit configuration shown in FIG. FIG. 6 is a circuit diagram showing another example of the high-speed startup drive circuit 5. 6 is a time chart for explaining the operation of the high-speed start-up drive circuit 5 having the circuit configuration shown in FIG. FIG. 6 is a circuit diagram showing another example of the high-speed startup drive circuit 5. It is a time chart for demonstrating operation | movement of the high-speed start-up drive circuit 5 which has a circuit structure shown in FIG. It is a block diagram which shows an example of the utilization form of the high-speed start-up drive circuit.

  FIG. 1 is a diagram showing an internal configuration of a semiconductor memory.

  Such a semiconductor memory includes a memory control unit 1, a memory cell array 2, a sense amplifier 3, a reference amplifier 4, and a high-speed startup drive circuit 5.

  In response to the write signal WR, the memory control unit 1 controls the memory cell array 2 to write information data at the address indicated by the address data. The memory control unit 1 controls the memory cell array 2 to read information data from the address indicated by the address data according to the read signal RD, and at the logic level 1 to activate the operation of each module. The enable signal CE is supplied to each of the sense amplifier 3, the reference amplifier 4, and the high-speed startup drive circuit 5. The memory control unit 1 outputs a logic level 0 enable signal CE to be deactivated and stops the operation during a period when the information data read operation is not performed, and the sense amplifier 3 and the reference amplifier 4. And is supplied to each of the high-speed startup drive circuits 5.

The sense amplifier 3 is inactive while the logic level 0 enable signal CE is supplied, while the sense amplifier 3 is active while the logic level 1 enable signal CE is supplied. Only while in this active state, the sense amplifier 3 detects a current flowing in a data line (not shown) connected to each memory cell (not shown) of the memory cell array 2, and the current value is a reference value. It is determined whether or not the threshold value is higher than the threshold value indicated by the voltage V _ref . The sense amplifier 3 outputs information data of logic level 1 as read data when the current value detected as described above is higher than the threshold value indicated by the reference voltage V _ref and logic level 0 when it is lower.

  In response to the write signal WR, the memory cell array 2 takes in the externally supplied information data via the sense amplifier 3 and writes it into a memory cell (not shown) belonging to the address indicated by the address data. The memory cell array 2 sends a current corresponding to the data stored in the memory cell at the address indicated by the address data to the sense amplifier 3 through the data line in response to the read signal RD.

The reference amplifier 4 becomes inactive while the logic level 0 enable signal CE is supplied, while it becomes active while the logic level 1 enable signal CE is supplied. Reference amplifier 4, starts generating the reference voltage V _ref with a predetermined threshold voltage V _R on the power supply voltage when a transition from an inactive state to an active state such as described above, the reference over while in the active state The voltage V _ref is supplied to the sense amplifier 3 via the reference voltage supply line RL. The threshold voltage value V _R of the reference voltage V _ref indicates whether the current value sent to the data line of the memory cell array 2 in the sense amplifier 3 indicates a logic level 0 or 1 as described above. This is a threshold value for determination.

  FIG. 2 is a diagram showing an internal configuration of the reference amplifier 4.

As shown in FIG. 2, the reference amplifier 4 includes a differential amplifier 21, a transistor 22 that is a p-channel MOS type FET, a transistor 22 that is an n-channel MOS type FET, and an inverter 24. Differential amplifier 21 supplies a difference signal corresponding to the voltage difference between the voltage on the threshold voltage V _R and the reference voltage supply line RL to the gate terminal of the transistor 22. A voltage VCC is applied to the drain terminal of the transistor 22, and its source terminal is connected to the reference voltage supply line RL. A ground potential VSS is applied to the source terminal of the transistor 23, and its drain terminal is connected to the reference voltage supply line RL. Transistor 23, based on the voltage VCC, the output voltage corresponding to the difference signal, i.e. to produce an output voltage having a threshold voltage V _R, and sends it out to the reference voltage supply line RL as the reference voltage V _ref. An inverted enable signal obtained by inverting the logic level of the enable signal CE by the inverter 24 is supplied to the gate terminal of the transistor 23.

With this configuration, the reference amplifier 4, from the transistor 23 is turned off while the enable signal CE of logic level 1 is supplied, it becomes active state, the output voltage having a threshold voltage value V _R as described above It is generated and sent to the reference voltage supply line RL as the reference voltage V _ref . However, when the logic level of the enable signal CE transitions from 1 to 0, the transistor 23 is turned on, so that the ground potential VSS is applied to the reference voltage supply line RL via the transistor 23. Therefore, during this time, the reference voltage supply line RL is maintained at 0 volt corresponding to the ground potential VSS. That is, the reference amplifier 4 is in a state where the reference voltage V _ref is not generated, that is, a so-called inactive state. Here, when the logic level of the enable signal CE transitions from 0 to 1, the transistor 23 switches from the on state to the off state, so that the reference amplifier 4 transitions to the active state as described above. At this time, the reference voltage supply line RL is at 0 volt immediately before switching from the inactive state to the active state, so that the voltage on the RL is immediately after the transistor 23 is switched from the on state to the off state. thereby leading to the threshold voltage value V _R gradually increases.

The high-speed start-up drive circuit 5 applies the voltage VCC to the reference voltage supply line RL for a predetermined period immediately after the enable signal CE is switched from the logic level 0 to the logic level 1 to thereby change the reference voltage V _ref A voltage rising part is generated.

  FIG. 3 is a diagram showing an example of the internal configuration of the high-speed startup drive circuit 5.

  As shown in FIG. 3, the high-speed start-up drive circuit 5 includes transistors Q1 and Q3 that are p-channel MOS type FETs, transistors Q2 and Q4 that are n-channel MOS type FETs, and an inverter IV1. Each of these transistors Q2, Q4, Q1, and Q3 is an enhancement type FET.

  The enable signal CE is supplied to the gate terminal of the transistor Q1. The voltage VCC is applied to the source terminal of the transistor Q1, and the drain terminal is connected to the drain terminal of the transistor Q2 and the gate terminal of the transistor Q4 via the line EN. A ground potential VSS is applied to the source terminal of the transistor Q2, and its gate terminal is connected to the source terminal of the transistor Q4 and the reference voltage supply line RL.

  Hereinafter, the operation of the semiconductor memory shown in FIG. 1 will be described with reference to FIG.

When the read signal RD is not supplied, that is, during the period when the information data read operation is not performed, the memory control unit 1 enables the logic level 0 enable signal CE to deactivate each module and stop the operation. Is supplied to each of the sense amplifier 3, the reference amplifier 4, and the high-speed startup drive circuit 5. During this time, since the reference amplifier 4 and the high-speed rising drive circuit 5 are in an inactive state, the reference voltage V _ref on the reference voltage supply line RL is 0 volt as shown in FIG. That is, the transistor Q1 of the high-speed start-up drive circuit 5 is turned on and Q3 is turned off in response to the logic level 0 enable signal CE, and Q2 is turned off because the voltage on the reference voltage supply line RL is 0 volts. Is in a state. At this time, since the transistor Q1 is in the on state and Q2 is in the off state, the voltage on the line EN in the high-speed startup drive circuit 5 becomes a high voltage corresponding to the voltage VCC, and the transistor Q4 is in the on state. However, since the transistor Q3 is in the OFF state, the high-speed startup drive circuit 5 does not apply a voltage to the reference voltage supply line RL. Further, since the reference amplifier 4 is not operated while the enable signal CE is in the logic level 0, no voltage is applied to the reference voltage supply line RL. Therefore, during this period, the reference voltage V _ref on the reference voltage supply line RL is 0 volt as shown in FIG.

  As described above, in the semiconductor memory shown in FIG. 1, the operation of not only the sense amplifier 3 but also the reference amplifier 4 is forcibly stopped during a period in which no read access is made. Can be reduced.

Thereafter, when the read signal RD is supplied, the memory control unit 1 supplies the enable signal CE of the logic level 1 for activating each module to each of the sense amplifier 3, the reference amplifier 4, and the high-speed start-up drive circuit 5. To do. When the enable signal CE shifts to the state of the logic level 1, the reference amplifier 4 starts the generation of the reference voltage V _ref with a predetermined threshold voltage V _R on the power supply voltage, the voltage reference voltage supply line RL Apply on top. In this case, the reference amplifier 4 alone, in the form shown in dashed line in FIG. 4, the reference voltage V _ref with a gradually rising waveform reaching the raised its voltage threshold voltage V _R from 0 volt state Applied to the reference voltage supply line RL.

When the enable signal CE transits to the logic level 1 state, the transistor Q3 of the high-speed startup drive circuit 5 transits to the on state, and the voltage VCC is applied to the reference voltage supply line RL via the transistors Q3 and Q4. The Therefore, the voltage on the reference voltage supply line RL rises sharply from the 0 volt state as shown by the solid line in FIG. Then, as shown in FIG. 4, when the voltage on the reference voltage supply line RL exceeds the gate threshold voltage value V _N1 of the transistor Q2 of the high-speed startup drive circuit 5, the transistor Q2 transitions to the on state. As a result, the ground potential VSS is applied to the reference voltage supply line RL, so that the potential on the line EN gradually decreases as shown in FIG. At this time, when the potential difference V _Q between the potential on the line EN as shown in FIG. 4 and the potential on the reference voltage supply line RL becomes equal to or lower than the threshold voltage value of the transistor Q4, the transistor Q4 transitions to the off state, The voltage rise on the reference voltage supply line RL stops. In a period ts until the voltage on the reference voltage supply line RL rises from the 0 volt state and stops, a voltage rising portion of the reference voltage V _ref is generated.

As described above, in the high-speed start-up drive circuit 5 shown in FIG. 3, immediately after the enable signal transitions from the logic level 0 to 1, both the transistors Q3 and Q4 are turned on for the period ts to force the voltage VCC. By applying the voltage to the reference voltage supply line RL, a voltage rising portion of the reference voltage V _ref is generated. As a result, the reference amplifier steeply compared with the case where the voltage on the reference voltage supply line RL is increased by the reference amplifier 4 alone without using the high-speed start-up drive circuit 5 (indicated by a one-dot chain line in FIG. 4). The voltage on the voltage supply line RL increases. In such a voltage rising portion, as shown in FIG. 4, temporarily overshoot that becomes a voltage value higher than the threshold voltage V _R occurs. Thereafter, the voltage on the reference voltage supply line RL gradually decreases, but when the sense amplifier 3 starts operating immediately after that, as shown in FIG. 4, due to the influence of switching noise at the start of the operation, the reference voltage supply line RL The upper voltage rises again and the overshoot condition continues. Thereafter, the voltage on the reference voltage supply line RL is gradually decreased, converges to the threshold voltage value V _R as a target.

Therefore, after the convergence period TQ from when the logic level of the enable signal is switched from 0 to 1 as shown in FIG. 4, until the voltage on the reference voltage supply line RL is reaches the threshold voltage V _R, the sense amplifier 3, it is possible to perform a logical level determination of the read data based on the reference voltage V _ref with the threshold voltage V _R. That is, information data stored in the memory cell array 2 can be read after the convergence period TQ has elapsed since the logic level of the enable signal was switched from 0 to 1.

Therefore, according to the high speed start-up drive circuit 5, as shown in FIG. 4, when the generation of the reference voltage V _ref is started by the reference amplifier 4 alone without using the high-speed start-up drive circuit 5 (one point in FIG. 4). The voltage value of the reference voltage V _ref can be quickly reached from the 0 volt state to the target threshold voltage value V _R as compared to the case indicated by a chain line).

  Therefore, information data can be read immediately after the sense amplifier 3 and the reference amplifier 4 are changed from the inactive state to the active state.

  At this time, as shown in FIG. 3, the high-speed start-up drive circuit 5 includes only four transistors Q1, Q3, Q2, and Q4 and one inverter IV1. Accordingly, high-speed data reading can be performed with low power consumption without significantly increasing the circuit scale.

  In the high-speed start-up drive circuit 5, it is possible to perform a higher-speed read access by eliminating the overshoot at the voltage rising portion as shown in FIG.

  FIG. 5 is a diagram showing another internal configuration of the high-speed startup drive circuit 5 made in view of such points.

  In the high-speed start-up drive circuit 5 shown in FIG. 5, other configurations are the same except that the transistor Q5, which is an n-channel MOS type FET, is added between the transistor Q4 shown in FIG. 3 and the reference voltage supply line RL. This is the same as shown in FIG.

  In FIG. 5, the source terminal of the transistor Q5 is connected to the reference voltage supply line RL, and the drain terminal thereof is connected to the source terminal of the transistor Q4. A predetermined positive voltage value Vdd is supplied to the gate terminal of the transistor Q5.

Hereinafter, the generation operation of the voltage rising portion of the reference voltage V _ref by the high-speed startup drive circuit 5 having the configuration shown in FIG. 5 will be described with reference to FIG.

First, as long as the logic level 0 enable signal CE is supplied, the transistors Q1 and Q4 of the high-speed start-up drive circuit 5 are in the on state and Q3 and Q2 are in the same state as when the configuration shown in FIG. 3 is adopted. Since it is in the off state, the high-speed startup drive circuit 5 does not apply a voltage to the reference voltage supply line RL. Further, since the reference amplifier 4 is not operated while the enable signal CE is in the logic level 0, no voltage is applied to the reference voltage supply line RL. Therefore, during this period, the reference voltage V _ref on the reference voltage supply line RL is 0 volt as shown in FIG.

Thereafter, when the read signal RD is supplied, the memory control unit 1 supplies the enable signal CE of the logic level 1 for activating each module to each of the sense amplifier 3, the reference amplifier 4, and the high-speed start-up drive circuit 5. To do. When the enable signal CE shifts to the state of the logic level 1, the reference amplifier 4 starts the generation of the reference voltage V _ref with a predetermined threshold voltage V _R on the power supply voltage, the voltage reference voltage supply line RL Apply on top. In this case, the reference amplifier 4 alone, in the form shown in dashed line in FIG. 6, the reference voltage V _ref with a gradually rising waveform reaching the raised its voltage threshold voltage V _R from 0 volt state Applied to the reference voltage supply line RL.

When the enable signal CE transitions to the logic level 1 state, the transistor Q3 of the high-speed startup drive circuit 5 transitions to the on state, and the voltage VCC is applied to the reference voltage supply line RL via the transistors Q3 and Q4. The Therefore, the voltage on the reference voltage supply line RL rises steeply from the 0 volt state as shown by the solid line in FIG. 6, and the source-drain voltage of the transistor Q5 decreases as the voltage rises. As a result, the transistor Q5 operates in a linear region, and the drain current flowing into the transistor Q5 decreases rapidly. Therefore, the voltage increase with the lapse of time at the voltage rising portion of the reference voltage V _ref becomes gradual after time t shown in FIG. Then, as shown in FIG. 6, when the voltage on the reference voltage supply line RL exceeds the gate threshold voltage value V _N1 of the transistor Q2 of the high-speed startup drive circuit 5, the transistor Q2 transitions to the on state. As a result, the ground potential VSS is applied to the reference voltage supply line RL, so that the potential on the line EN gradually decreases as shown in FIG. At this time, when the potential difference V _Q between the potential on the line EN and the potential on the reference voltage supply line RL as shown in FIG. 6 becomes equal to or lower than the threshold voltage of the transistor Q4, the transistor Q4 transitions to the off state. The voltage rise on the voltage supply line RL stops. In a period ts until the voltage on the reference voltage supply line RL rises from the 0 volt state and stops, a voltage rising portion of the reference voltage V _ref is generated.

According to the driving, such as described above, the voltage rise of the reference voltage V _ref, as shown in FIG. 4, the overshoot that would significantly increases the threshold voltage value V _R as a target can be avoided. Further, since the voltage rise with the lapse of time at the voltage rising portion becomes gentle after time t, even if the sense amplifier 3 starts operation thereafter, the voltage rise caused by switching noise at the start of the operation is avoided. It becomes possible. Therefore, although the voltage rise with the lapse of time at the voltage rising portion becomes gradual after time t, the voltage value is rapidly changed to the threshold voltage value V as shown in FIG. Converges to _R. As a result, from the time the logical level of the enable signal is switched from 0 to 1, the convergence period TQ of the voltage on the reference voltage supply line RL is down to the threshold voltage value V _R is overshoot as shown in FIG. 4 It is shorter than when it occurs.

  That is, when the configuration shown in FIG. 5 is adopted as the high-speed start-up drive circuit 5, information data can be read at a higher speed than when the configuration shown in FIG. 3 is adopted. .

  Note that a depletion type FET may be adopted as the transistor Q5 shown in FIG. 5 instead of the enhancement type FET.

  FIG. 7 is a diagram showing another example of the internal configuration of the high-speed startup drive circuit 5 made in view of such points.

  The high-speed start-up drive circuit 5 shown in FIG. 7 has the same configuration as that shown in FIG. 5 except that the transistor Q6 as a depletion type n-channel MOSFET is employed instead of the enhancement type transistor Q5 shown in FIG. Are the same.

  In FIG. 7, the source terminal of the transistor Q6 is connected to the reference voltage supply line RL, and the drain terminal thereof is connected to the source terminal of the transistor Q4. The ground potential VSS is fixedly supplied to the gate terminal of the transistor Q6.

Hereinafter, the generation operation of the voltage rising portion of the reference voltage V _ref by the high-speed startup drive circuit 5 having the configuration shown in FIG. 7 will be described with reference to FIG.

First, as long as the logic level 0 enable signal CE is supplied, the transistors Q1 and Q4 of the high-speed start-up drive circuit 5 are in the on state and Q3 and Q2 are in the same state as when the configuration shown in FIG. 5 is adopted. Since it is in the off state, the high-speed startup drive circuit 5 does not apply a voltage to the reference voltage supply line RL. Further, since the operation of the reference amplifier 4 is not performed while the enable signal CE is in the logic level 0, no voltage is applied to the reference voltage supply line RL. Therefore, during this period, the reference voltage V _ref on the reference voltage supply line RL is 0 volt as shown in FIG.

Thereafter, when the read signal RD is supplied, the memory control unit 1 supplies the enable signal CE of the logic level 1 for activating each module to each of the sense amplifier 3, the reference amplifier 4, and the high-speed start-up drive circuit 5. To do. When the enable signal CE shifts to the state of the logic level 1, the reference amplifier 4 starts the generation of the reference voltage V _ref with a threshold voltage V _R on the power supply voltage, the voltage on the reference voltage supply line RL Apply. In this case, the reference amplifier 4 alone, the reference voltage V _ref is a reference having a gradually rising waveform leading the voltage thereof rises threshold voltage V _R in the form shown in dashed line from 0 volts in the state of FIG. 8 Applied on the voltage supply line RL.

When the enable signal CE transitions to the logic level 1 state, the transistor Q3 of the high-speed startup drive circuit 5 transitions to the on state, and the voltage VCC is applied to the reference voltage supply line RL via the transistors Q3 and Q4. The Therefore, the voltage on the reference voltage supply line RL rises sharply from the 0 volt state as shown by the solid line in FIG. As the voltage between the source and drain of the transistor Q6 decreases as the voltage increases, the transistor Q6 operates in a linear region, and the drain current flowing into the Q6 rapidly decreases. Therefore, the voltage increase with the lapse of time at the voltage rising portion of the reference voltage V _ref becomes gradual after time t shown in FIG. Then, as shown in FIG. 8, when the voltage on the reference voltage supply line RL exceeds the gate threshold voltage value V _N1 of the transistor Q2 of the high-speed startup drive circuit 5, the transistor Q2 transitions to the on state. As a result, the ground potential VSS is applied to the reference voltage supply line RL, so that the potential on the line EN gradually decreases as shown in FIG. At this time, when the potential difference V _Q between the potential on the line EN and the potential on the reference voltage supply line RL as shown in FIG. 8 becomes equal to or lower than the threshold voltage of the transistor Q4, the transistor Q4 transits to the off state. The voltage rise on the voltage supply line RL stops. In a period ts until the voltage on the reference voltage supply line RL rises from the 0 volt state and stops, a voltage rising portion of the reference voltage V _ref is generated.

According to the driving, such as described above, the voltage rise of the reference voltage V _ref, the overshoot that would significantly increases the threshold voltage value V _R as a target, as shown in FIG. 4 is avoided. Further, since the voltage rise with the lapse of time at the voltage rising portion becomes gentle after time t, even if the sense amplifier 3 starts operation thereafter, the voltage rise caused by switching noise at the start of the operation is avoided. It becomes possible. Therefore, although the voltage rise with the lapse of time at the voltage rising portion becomes gradual after the time t, the voltage value is rapidly changed to the threshold voltage value V as shown in FIG. Converges to _R. As a result, from the time the logical level of the enable signal is switched from 0 to 1, the convergence period TQ of the voltage on the reference voltage supply lines RL is up to the threshold voltage V _R is overshoot as shown in FIG. 4 It is shorter than when it occurs.

  That is, even when the configuration shown in FIG. 7 is adopted as the high-speed start-up drive circuit 5, information data can be read at a higher speed than when the configuration shown in FIG. 3 is adopted. In the configuration shown in FIG. 7, the transistor Q6, which is a depletion type n-channel MOSFET, is used instead of the transistor Q5, which is an enhancement type n-channel MOSFET shown in FIG. 5, so that the voltage applied to the gate terminal is grounded. Even with the potential VSS, the operation in the linear region as described above can be performed.

  Therefore, it is possible to obtain a stable convergence period TQ as compared with the case where the enhancement type transistor Q5 capable of operating in the linear region by fixing and supplying the positive voltage value Vdd to the gate terminal. .

  In the above-described embodiment, the high-speed start-up drive circuit 5 is used in order to quickly start up the reference voltage serving as a threshold when the sense amplifier 3 determines the logic level. As shown in FIG. 9, the circuit 5 may be used to raise the output voltage of the constant voltage power supply device at high speed.

  In FIG. 9, when the power switch 91 is switched from the OFF state to the ON state and the supply of the power supply voltage is started, the constant voltage power supply device 90 generates the output voltage VG having a predetermined constant voltage value based on the power supply voltage. It is generated and applied to the power supply line GL. The power switch 91 supplies an enable signal having a logic level 0 while the power switch 91 is in an off state and a logic level 1 to the high-speed startup drive circuit 5 while the power switch 91 is in an on state. The high-speed start-up drive circuit 5 shown in FIG. 9 has the internal configuration shown in FIG. 3, FIG. 5, or FIG. 7, and performs the drive as described above for the power supply line GL in response to the enable signal of logic level 1. As a result, the voltage rise with the passage of time at the voltage rising portion of the output power supply voltage VG applied to the power supply line GL is made steep. As a result, the voltage value of the output voltage VG is raised to the target constant voltage value at a high speed from the time when the power is turned on.

1 Memory Control Unit 3 Sense Amplifier 4 Reference Amplifier 5 High-Speed Startup Drive Circuit

Claims (11)

A semiconductor device having a voltage supply line,
A first transistor having a first terminal for receiving a first potential, a second terminal connected to the first line, and a control terminal for receiving a control signal;
A second transistor having a first terminal connected to the first line, a second terminal receiving a second potential, and a control terminal connected to the voltage supply line;
A third transistor having a first terminal for receiving the first potential and a control terminal for receiving a signal obtained by inverting the logic level of the control signal;
A fourth terminal having a first terminal connected to the second terminal of the third transistor, a second terminal connected to the voltage supply line, and a control terminal connected to the first line; A semiconductor device comprising: a transistor; A control unit for generating the control signal indicating an enable instruction or a disable instruction;
A voltage generation unit configured to generate a predetermined voltage and apply the voltage to the voltage supply line when the control signal indicates the enable instruction;
The first transistor is turned on when the control signal indicates the disable instruction, while the first transistor is turned off when the control signal indicates the enable instruction,
2. The third transistor according to claim 1, wherein the third transistor is turned on when the control signal indicates the enable instruction, and is turned off when the control signal indicates the disable instruction. Semiconductor device.   The control unit includes a power switch that receives a power supply voltage to supply or cut off the power supply voltage to the voltage generation unit, and when the power switch is in an ON state, the control signal indicating the enable instruction 3. The semiconductor device according to claim 2, wherein the control signal indicating the disable instruction is generated when the power switch is in an off state.   4. The method according to claim 1, wherein the first and third transistors are p-channel MOS transistors, and the second and fourth transistors are n-channel MOS transistors. The semiconductor device described.   5. The semiconductor device according to claim 4, wherein the first potential is a power supply potential and the second potential is a ground potential. A semiconductor device having a voltage supply line,
A first transistor having a first terminal for receiving a first potential, a second terminal connected to the first line, and a control terminal for receiving a control signal;
A second transistor having a first terminal connected to the first line, a second terminal receiving a second potential, and a control terminal connected to the voltage supply line;
A third transistor having a first terminal for receiving the first potential and a control terminal for receiving a signal obtained by inverting the logic level of the control signal;
A fourth transistor having a first terminal connected to the second terminal of the third transistor and a control terminal connected to the first line;
A fourth transistor having a first terminal connected to the second terminal of the third transistor and a control terminal connected to the first line;
A fifth transistor having a first terminal connected to the second terminal of the fourth transistor, a second terminal connected to the voltage supply line, and a control terminal for receiving a predetermined fixed potential; A semiconductor device comprising: A control unit for generating the control signal indicating an enable instruction or a disable instruction;
A voltage generation unit configured to generate a predetermined voltage and apply the voltage to the voltage supply line when the control signal indicates the enable instruction;
The first transistor is turned on when the control signal indicates the disable instruction, while the first transistor is turned off when the control signal indicates the enable instruction,
7. The third transistor is turned on when the control signal indicates the enable instruction, and is turned off when the control signal indicates the disable instruction. Semiconductor device.   The control unit includes a power switch that receives a power supply voltage to supply or cut off the power supply voltage to the voltage generation unit, and when the power switch is in an ON state, the control signal indicating the enable instruction 8. The semiconductor device according to claim 7, wherein the control signal indicating the disable instruction is generated when the power switch is in an off state.   9. The method according to claim 6, wherein the first and third transistors are p-channel MOS transistors, and the second, fourth, and fifth transistors are n-channel MOS transistors. The semiconductor device according to claim 1.   The semiconductor device according to claim 9, wherein the first potential is a power supply potential, and the second potential is a ground potential. The first to fourth transistors are enhancement type, and the fifth transistor is depletion type.
The semiconductor device according to claim 10, wherein the fixed potential is a ground potential.

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