KR20090027378A - Internal voltage generating circuit - Google Patents

Abstract

An internal voltage generating circuit is provided to prevent a DRAM fault generation by generating a sufficient pumping voltage by a pumping circuit. An internal voltage generating circuit comprises a voltage detection circuit(31), a first oscillation part(32), a first pumping circuit(34), a temperature information output device(36), a second oscillation part(37), and a second pumping circuit(33). The voltage detection circuit detects a voltage level of a pumping voltage by comparing a reference voltage with the pumping voltage. The firs oscillation part generates a first clock signal based on an output signal of the detection circuit. The first pumping circuit generates the pumping voltage based on the first clock signal. The temperature information output device outputs different temperature information according to a temperature change. The second oscillation part generates a second clock signal based on the temperature information outputted from the temperature information output device. The second pumping circuit generates the pumping voltage based on the second clock signal.

Description

Internal voltage generating circuit {INTERNAL VOLTAGE GENERATING CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor design technology, and more particularly, to an internal voltage generation circuit for stably generating an internal voltage used in a semiconductor memory device regardless of temperature change.

The semiconductor memory device is used in various fields, but one of them is used to store various kinds of data. Since such semiconductor memory devices are used in various portable devices, including desktop computers and notebook computers, large capacity, high speed, small size, and low power are required.

As a method for designing a semiconductor memory device according to the low power, a technology for minimizing current consumption in a core area of a memory has been proposed. The core region is composed of a memory cell, a bit line, and a word line, and is designed according to an extremely fine design rule. Therefore, in order to design a semiconductor memory device having extremely fine and high frequency operation, the power supply voltage is inevitably very low, and a power supply voltage of 1.5 volts or less is currently applied.

Meanwhile, the semiconductor memory device generates and uses a power having a required size inside the device using the external power supply voltage of 1.5 volts or less, and one of the methods is higher than the external power supply potential or grounded using a charge pump. This method produces an internal potential lower than the potential.

Among the internal power sources generated by the charge pumping, the internal power sources most commonly used in the DRAM, which is a semiconductor memory device, include a pumping voltage VPP and a back bias voltage VBB. The pumping voltage VPP is used to prevent the cell data from being lost by applying a pumping voltage VPP, which is a potential higher than the external power supply voltage VCC or VDD, to the gate and the gate of the cell transistor to access the cell. . In order to prevent the loss of data stored in the cell, the back bias voltage VBB is applied to the bulk of the cell transistor lower than the ground voltage VSS, which is an external potential.

1 is a block diagram illustrating an internal voltage generation circuit for generating a pumping voltage in a semiconductor memory device according to the related art.

As illustrated, a high voltage generation circuit of a conventional semiconductor memory device may compare the reference voltage generator 10 generating a stable reference voltage VREF, the reference voltage VREF, and the feedback pumping voltage VPP to pump the same. The voltage detection circuit 11 which detects the voltage level so as to maintain a constant voltage level, and the clock signal OSC for generating the pumping voltage VPP based on the output signal VPPE of the voltage detection circuit. An oscillator 12, a pump circuit 14 for generating a pumping voltage VPP that boosts an external voltage VDD in response to a clock signal of the oscillator 12, and a pumping voltage generated by the pump circuit 14 The cell transistor 15 is supplied with a VPP.

In the conventional internal voltage generation circuit for generating the pumping voltage as configured above, the reference voltage VREF generated from the reference voltage generator 10 is compared with the feedback pumping voltage VPP, and the feedback pumping voltage is the reference voltage. When lower, the voltage detection circuit 11 outputs the voltage level detection signal VPPE. The voltage level detection signal VPPE drives the oscillator 12, and the clock signal OSC generated by the oscillator 12 is supplied as a driving signal of the pump circuit 14. The pump circuit 14 is driven by a clock signal that is periodically applied from the oscillator 12 to generate a pumping voltage VPP that boosts the external power supply voltage VDD and supplies it to the cell transistor 15.

That is, the pump circuit 14 is driven by the clock signal of the oscillator 12 when the feedback pumping voltage VPP is lower than the reference voltage and boosts the external power supply voltage VDD. ) Is supplied to the cell transistor 15. In order to operate the pump circuit 14 as described above, the pump circuit 14 is based on a detection value of the voltage detection circuit 11 that detects a voltage level in comparison with the feedback pumping voltage and the reference voltage.

However, there is a problem in that a comparison value between the pumping voltage fed back from the voltage detecting circuit 11 and the reference voltage changes with temperature. This is because the supply capacity of the transistors that make the pumping voltage causes a difference depending on the temperature, so that the supply capacity of the transistor at a low temperature becomes smaller than that at a high temperature. Therefore, the internal voltage generation circuit for generating the conventional pumping voltage, as shown in Figure 2, the pumping voltage generated in a low temperature environment is relatively lower than the pumping voltage generated in a high temperature environment. As such, the conventional internal voltage generation circuit has a problem of causing a failure of the semiconductor memory device due to a weakening of the ability to turn on the cell transistor due to the pumping voltage level falling in a low temperature environment.

This problem also occurs in the internal voltage generation circuit that generates the back bias voltage. 3 is a block diagram of a back bias voltage generation circuit according to the prior art.

The conventional back bias voltage generation circuit compares the internal voltage generator 20 generating the stable reference voltage VINT, the internal voltage VINT with the feedback back bias voltage VBB, and when the back bias voltage is high. The oscillator 22 and the oscillator 22 which generate a clock signal OSC to lower the back bias voltage VBB level based on the voltage detection circuit 21 for sensing and the output signal VBBE of the voltage detection circuit. The pump circuit 24 operated to lower the back bias voltage VBB level by using the external voltage VSS in response to the clock signal of the < RTI ID = 0.0 >), and the back bias voltage VBB < / RTI > It is comprised including the cell transistor 25 supplied. The back bias voltage is also referred to as a substrate voltage and has a negative voltage value.

Also in the internal voltage generation circuit according to the conventional back bias voltage according to the above configuration, the pump circuit 24 is the clock signal of the oscillator 22 when the feedback back bias voltage VBB is higher than the internal voltage VINT. Is driven to generate the back bias voltage VBB using the external power supply voltage VSS and to supply it to the cell transistor 25. In order to operate the pump circuit 24 as described above, it is based on the detection value of the voltage detection circuit 21 for detecting the voltage level by comparing the feedback back bias voltage and the internal voltage.

Therefore, even in the internal voltage generation circuit according to the back bias voltage, a problem arises in that the comparison value between the fed back back bias voltage and the internal voltage changes with temperature. This problem will be described in more detail with reference to the detailed configuration of the voltage detection circuit.

4 shows a detailed configuration diagram of a voltage detection circuit of a conventional internal voltage generation circuit.

As shown, the back bias voltage VBB is applied to the gate terminal of the PMOS transistor M1, and the PMOS transistor M0 is connected in series with the transistor M1. The transistor M0 connects a drain-source terminal between the internal voltage VINT output from the internal voltage generator 20 and the transistor M1 and gates an external power supply voltage VSS that is a ground voltage. It is applied to the terminal.

The gate terminals of the PMOS transistor M2 and the NMOS transistor M3 are connected in parallel to a node N1 connected between the two transistors MO and M1. The transistor M2 connects a drain-source terminal between an internal voltage VINT and a node N2, and the transistor M3 connects a drain-source terminal between the node N2 and a ground voltage VSS. Connect. An inverter IN0 is connected to the node N2, and an output signal of the inverter IN0 becomes an output signal VBBE of the voltage detection circuit.

In the conventional voltage detection circuit configured as described above, when the level of the back bias voltage VBB generated in the pump circuit 24 is high, a high level back bias voltage is applied to the gate terminal of the PMOS transistor M1. Therefore, transistor M1 is weakly turned on. At this time, since the PMOS transistor M0 turned on by the ground voltage is strongly turned on, a high level signal is applied to the node N1.

The high level signal applied to the node N1 causes the PMOS transistor N2 to have a weakly turned on state, and at the same time, the NMOS transistor N3 has a strongly turned on state. A low level signal is applied. The low level signal is inverted while passing through the inverter IN0, so that the output signal VBBE of the voltage detection circuit 21 becomes a high level. The oscillator 22 outputs a periodic clock signal by the high level voltage detection signal, and the pump circuit 24 operates to further lower the level of the back bias voltage VBB.

When the level of the back bias voltage VBB is lowered and lower than the internal voltage VINT output from the internal voltage generator 20, a low level back bias voltage is applied to the gate terminal of the PMOS transistor M1. M1 is strongly turned on. At the same time, the PMOS transistor M0, which receives the ground voltage as the gate terminal, is also turned on. However, since the turn-on capability of the transistor M1 is designed to be stronger than that of the transistor M0, the node N1 is turned on. ), A low level signal is applied.

The low level signal applied to the node N1 causes the PMOS transistor N2 to have a strongly turned on state, and at the same time, the NMOS transistor N3 has a weakly turned on state. The high level signal is applied. This high level signal is inverted while passing through the inverter IN0, so that the output signal VBBE of the voltage detection circuit 21 becomes low level. The oscillator 22 stops operating by the low-level voltage detection signal thus output, and the pump circuit 24 no longer lowers the level of the back bias voltage VBB.

The voltage detection circuit operating as described above detects a constant voltage level regardless of temperature change. That is, the back bias voltage level compared to the internal voltage is configured to be constant even in an environment where the temperature is high or the temperature is low.

However, the threshold voltage of a cell transistor changes with temperature. In other words, as the threshold voltage of the cell transistor decreases as the temperature increases, the off current flows very much.

5 shows a state of change of the threshold voltage of the cell transistor according to the temperature change. For example, it can be seen that the threshold voltage of the cell transistor is 0.95V at low temperature, but the threshold voltage of the cell transistor rapidly drops to 0.66V at high temperature. As a result of the change in the threshold voltage of the cell transistor according to the temperature change, the off capability of the cell transistor is weakened, causing a problem that the off current flows very much.

As a result, the conventional internal voltage generation circuit for generating the back bias voltage has a problem that the threshold voltage of the cell transistor is lowered in a relatively high temperature environment compared to the temperature at which the cell transistor is normally operated, so that the off current flows very much. Similarly, the conventional internal voltage generation circuit that generates the pumping voltage has a problem in that the supply capacity of the transistor is weak in a relatively low temperature environment as compared with the temperature at which the transistor normally operates, so that a sufficient high voltage cannot be applied to the cell transistor.

Accordingly, an object of the present invention is to provide an internal voltage generation circuit capable of stably supplying an internal voltage to a cell transistor by generating an internal voltage corresponding to a temperature change.

The internal voltage generation circuit according to the present invention for achieving the above object comprises a detection means for detecting the voltage level of the pumping voltage by comparing the reference voltage and the feedback pumping voltage; First oscillating means for generating a first clock signal based on an output signal of said detecting means; First pumping means for generating a pumping voltage based on the first clock signal; Temperature information output means for outputting different temperature information according to the temperature change; Second oscillating means for generating a second clock signal based on temperature information output from said temperature information output means; And second pumping means for generating a pumping voltage based on the second clock signal.

The second oscillation means of the present invention, the NAND gate having the temperature information as a first input; A first delay circuit for delaying an output of the NAND gate by a first time; A second delay circuit delaying an output of the first delay circuit by a second time and providing the second delay circuit to a second input of the NAND gate; And an output terminal unit for outputting the output of the second delay circuit as a second clock signal.

The first and second delay circuits of the present invention comprise an inverter.

In addition, the internal voltage generation circuit according to another embodiment of the present invention, the temperature information output means for outputting different temperature information according to the temperature change; Detection means for comparing a pumping voltage fed back based on an internal voltage and the temperature information and detecting a level of the pumping voltage; Oscillating means for generating a clock signal based on an output signal of the detecting means; And pumping means for generating a pumping voltage based on the clock signal.

The detection means of the present invention, the sink unit is operated by the feedback pumping voltage; First switching means which is turned on based on the temperature information to adjust a turn-on resistance of the sink unit; A first driver configured to input the internal voltage and adjust and output a voltage level by a turn-on resistance of the sink; And outputting a detection signal to reduce the back bias voltage when the first driver outputs the high level signal.

The sink portion of the present invention is characterized in that two PMOS transistors are connected in series.

The first switching means of the present invention is connected between the drain-source of the first transistor of the two transistors forming the sink, the turn-on resistance of the sink is formed only by the second transistor during the turn-on operation, turn-off operation And turn-on resistance of the sink part is formed by the first and second transistors.

The first switching means of the present invention is characterized in that the NMOS transistor for inputting temperature information to the gate terminal.

The first driver of the present invention is a PMOS transistor which inputs a ground voltage to a gate terminal and supplies an internal voltage.

The second driver of the present invention is configured to output an internal voltage by connecting a PMOS transistor and an NMOS transistor which input the output of the first driver to a gate terminal in series, and are output by the operation of the two transistors. And an inverter for inverting the signal.

The internal voltage generation circuit according to the present invention as described above is characterized in that it is possible to actively respond to temperature information that changes the generated internal voltage in consideration of the characteristics of the semiconductor memory device sensitive to temperature changes. . Therefore, the present invention operates the pumping circuit more so that a sufficient pumping voltage is generated in a low temperature environment so as not to run out of high voltage supply capacity. In this way, the present invention obtains the effect of suppressing DRAM defects caused by cell transistors whose turn-on capability becomes weak due to low temperature environment. In addition, the present invention further controls the back bias voltage in a high temperature environment, thereby increasing the threshold voltage of the cell transistor so that the off current does not flow much, resulting in the effect of reducing power consumption.

Hereinafter, an internal voltage generation circuit according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

6 is a block diagram illustrating an internal voltage generation circuit according to an exemplary embodiment of the present invention. The internal voltage generation circuit shown is a circuit configuration according to the generation of the pumping voltage used in the semiconductor memory device.

As illustrated, the internal voltage generation circuit of the present invention compares the reference voltage generator 30 generating a stable reference voltage VREF, the reference voltage VREF and the feedback pumping voltage VPP to the pumping voltage. A voltage detection circuit 31 for detecting a voltage level so as to maintain the constant voltage level, and a clock signal OSC1 for generating a pumping voltage VPP based on an output signal VPPE of the voltage detection circuit. A first pump circuit 34 generating a pumping voltage VPP using an external voltage VDD in response to a first oscillator 32 and a clock signal OSC1 of the first oscillator 32, and the first pump circuit 34. The cell transistor 35 receives the pumping voltage VPP generated in the pump circuit 34.

In addition, the internal voltage generation circuit of the present invention generates a pumping voltage in a low temperature environment by using the temperature information output device 36 for detecting the temperature inside the semiconductor memory device and the output signal of the temperature information output device 36. And a second oscillator 37 for generating a clock signal. In this case, the temperature information output device is a temperature information output device (ODTS: On Die Thermal Sensor) used in the RAM (DDR3) prescribed by the JEDEC. Therefore, since the temperature information output device uses a known technique, a description thereof will be omitted.

As shown in FIG. 7, the second oscillator 37 uses the output signal C1 of the temperature information output device 36 as the first input of the NAND gate NAND1, The output is configured to be input back to the second input of the NAND gate NAND1 via four inverters IV1 to IV4. The node N3 connected between the inverter IV1 and the inverter IV2 becomes an output terminal of the clock signal OSC2 output from the control circuit 37.

Next, an operation process of the internal voltage generation circuit according to the present invention having the above configuration will be described.

The reference voltage generator 30 generates a stable reference voltage VREF. The reference voltage VREF generated by the reference voltage generator 30 is input to the first input terminal of the voltage detection circuit 31, and the voltage detection circuit 31 is the pumping voltage VPP fed back from the pump circuit. Is input to the second input terminal. The voltage detection circuit 31 compares the feedback pumping voltage VPP and the reference voltage VREF and outputs a low level signal VPPE when the pumping voltage is higher than the reference voltage. The low level signal VPPE output from the voltage detection circuit 31 controls the first oscillator 32 in a stopped state, and thus the first pump circuit 34 is not operated.

However, when the feedback pumping voltage VPP input to the voltage detection circuit 31 is compared with the reference voltage VREF, a high level signal VPPE is output when the pumping voltage is lower than the reference voltage. The high level signal VPPE output from the voltage detection circuit 31 is input to the oscillator 32. In this case, the oscillator 32 outputs the clock signal OSC1 having a predetermined period, and the first pump circuit 34 operates by the generated clock signal OSC1 to generate the pumping voltage VPP.

The above operation is an operation process performed when the environmental temperature affected by the semiconductor memory device is in a relatively high first temperature section than when the temperature information output device outputs a high level signal. Accordingly, the temperature information output device 36 generates an output signal having a low level state in the temperature range of the first temperature section. Here, the first temperature section is a temperature section in which the transistor can operate normally.

The low level signal C1 output from the temperature information output device 36 is input to the NAND gate NAND1 of the second oscillator 37, and based on this signal, the low level signal C1 is high regardless of other input signals of the NAND gate. A level signal is generated. The inverter IV1 is inverted to output a low level signal, and thus the second oscillator 37 always outputs a low level signal. That is, the second oscillator 37 maintains the low level while the temperature information output device 36 outputs the low level signal C1. Therefore, the second pump circuit 33 does not operate.

On the other hand, when the temperature environment affected in the semiconductor memory device is in the second temperature section relatively lower than the first temperature section, the temperature information output device 36 outputs the high level signal C1. Here, the second temperature section is a section that is relatively lower than the first temperature section, and a temperature section in which the supply capacity of the transistor becomes weak and a sufficient high voltage cannot be generated.

The high level signal output from the temperature information output device 36 is input to the NAND gate NAND1. In this case, the value inverting the output signal of the NAND gate NAND1 is the clock signal of the second oscillator 37. Is output.

That is, assuming that the first input signal C1 of the NAND gate is high level and the initial value of the second input signal is high level, the NAND gate has a low level output. The low level output is inverted to a high level through the inverter IV1 and output as the clock signal OSC2 of the second oscillator 37 through the node N3.

The high level signal inverted by the inverter IV1 is sequentially converted to a low level signal while passing through the three inverters IV2 to IV4 and input as a second input signal of the NAND gate NAND1. The NAND gate outputs a high level signal, which is converted into a low level signal while being inverted by the inverter IV1, so that the output of the second oscillator 37 previously transitions from a high level signal to a low level signal. As a result, a clock signal having a certain period is formed.

As described above, while the second oscillator 37 outputs the clock signal OSC2, the second pump circuit 33 performs the pumping voltage generation operation. Accordingly, the cell transistor 35 performs the second pump circuit 33. The pumping voltage generated from is supplied.

In addition, when the pumping voltage VPP fed back from the first pump circuit 34 is lower than the reference voltage, the pumping voltage is driven by the clock signal of the first oscillator 32 and boosts the external power voltage VDD. VPP is generated and supplied to the cell transistor 35.

8 is a graph illustrating a change in pumping voltage according to an operation of the present invention. That is, since sufficient pumping voltage is generated only by the operation of the first pump circuit in the first temperature section, the operation of the second pump circuit is interrupted, and in the second temperature section relatively lower than the first temperature section, the first and second pump circuits It is controlled to generate sufficient pumping voltage by operating.

In the embodiment of the present invention described above, the pumping voltage is described as an example of the case of the high voltage (VPP). However, the pumping voltage is not limited to only a high voltage, but may be sufficiently described with other voltages such as a back bias voltage used in a semiconductor memory device.

Next, FIG. 9 shows a configuration diagram for generating an internal voltage according to another embodiment of the present invention. The illustrated embodiment is described taking the back bias voltage as an example of the pumping voltage.

The internal voltage generator circuit of the present invention compares the internal voltage generator 40 generating a stable reference voltage VINT, the internal voltage VINT with a feedback back bias voltage VBB, and when the back bias voltage is high. The oscillator 42 and the oscillator generating the clock signal OSC to lower the back bias voltage VBB level based on the voltage detection circuit 41 detecting the voltage and the output signal VBBE of the voltage detection circuit. A pump circuit 44 which is operated to lower the back bias voltage VBB level using an external voltage VSS in response to the clock signal of 42, and a back bias voltage VBB generated by the pump circuit 44. It is configured to include a cell transistor (45) supplied with. The back bias voltage is also referred to as a substrate voltage and has a negative voltage value.

The present invention further comprises a temperature information output device 46 for detecting the temperature inside the semiconductor memory device and applying it to the voltage detection arc 41. In this case, the temperature information output device is a temperature information output device (ODTS: On Die Thermal Sensor) used in the RAM (DDR3) prescribed by the JEDEC. Therefore, since the temperature information output device uses a known technology, its configuration and detailed operation will be omitted.

As shown in FIG. 10, the voltage detection circuit 41 is applied to the gate terminals of the PMOS transistors M11 and M14 to which the back bias voltage VBB is connected in series, and is in series with the transistor M14. Another PMOS transistor M10 is connected. The transistor M10 connects a drain-source terminal between the internal voltage VINT output from the internal voltage generator 40 and the transistor M14, and gates an external power supply voltage VSS, which is a ground voltage. It is applied to the terminal.

A node N13 is connected between the transistor M14 and a transistor M11, a node N11 is connected between the transistor M10 and a transistor M14, and between the two nodes N11 and N13. The drain-source terminal of the NMOS transistor M15 is connected to the gate terminal of the transistor M15, and the output signal C1 of the temperature information output device 46 is input.

The gate terminals of the PMOS transistor M13 and the NMOS transistor M12 are connected in parallel to the node N11 connected between the two transistors M10 and M14. The transistor M13 connects a drain-source terminal between an internal voltage VINT and a node N12, and the transistor M12 connects a drain-source terminal between the node N12 and a ground voltage VSS. Connect. An inverter IN5 is connected to the node N12, and an output signal of the inverter IN5 becomes an output signal VBBE of the voltage detection circuit 41.

Next, an operation process of an internal voltage generation circuit according to an embodiment of the present invention having the above configuration will be described.

The internal voltage generator 40 generates a stable internal voltage VINT, and the voltage detection circuit 41 compares the internal voltage with the feedback back bias voltage VBB.

The internal voltage VINT input to the voltage detection circuit 41 is applied to the source terminal of the transistor M10. The transistor M10 is turned on by receiving a ground voltage VSS as a gate terminal. The back bias voltage VBB input to the voltage detection circuit 41 is applied to the gate terminals of the transistors M11 and M14.

First, the process of operation when the ambient temperature is low will be described.

When the temperature is low, the signal C1 output from the temperature information output device 46 has a high level. When the output signal C1 has a high level, the transistor M15 is turned on. That is, a current path is formed between the node N11 and the node N13 via the transistor M15. In this case, the transistor M14 has no effect. Therefore, when the transistor M15 is turned on, the sink formed by the two transistors M14 and M11 is operated only by the transistor M11. Therefore, the turn-on resistance becomes small. In the state where the turn-on resistance of the sink is small, even if the back bias voltage VBB is slightly lowered, the voltage level of the node N11 may be transitioned to a low level. Here, it is assumed that the back bias voltage is designed to be about -0.8 volts and will be described later. In the case where the ambient temperature environment is low, that is, the section in which the high temperature signal C1 is outputted is a relative value compared with the case where the ambient temperature environment is described later, and the threshold voltage of the cell transistor is about 0.95 volts. This is the section that operates with normal off capability in.

As described above, when the back bias voltage VBB is higher than -0.8 volts while the transistor M15 is turned on based on the high-level temperature information C1 detected in the low temperature environment, the transistor M11 is turned on. Since the input voltage level is high, the transistor M11 is weakly turned on and has a high resistance value. At this time, since the transistor M10 is strongly turned on by the ground voltage VSS, a high level signal is applied to the node N11.

The high level signal applied to the node N11 causes a low level signal to be applied to the node N12 while the transistor M12 is turned on, and the low level signal is inverted by the inverter IV5, resulting in voltage detection. The output of the circuit 41 becomes a high level signal.

The high level signal output from the voltage detection circuit 41 is controlled to operate the oscillator 42 so that the pump circuit 44 performs the pumping operation, that is, lower the level of the back bias voltage further.

As the above operation continues, when the back bias voltage VBB is lower than the target value, that is, lower than −0.8 volts, the transistor M11 is strongly turned on because the voltage level input to the transistor M11 is low. It will have a low resistance value. At this time, since the transistor M10 is strongly turned on by the ground voltage VSS, a low level signal is applied to the node N11.

The low level signal applied to the node N11 turns on the transistor M13, turns off the transistor M12, and applies a high level signal to the node N12, and the high level signal is applied to the inverter ( Inverted at IV5) and as a result, the output of the voltage detection circuit 41 becomes a low level signal. The low level signal output from the voltage detection circuit 41 stops the operation of the oscillator 42 and the pump circuit 44.

Next, let's take a look at the operation process when the ambient temperature is high.

When the temperature is high, the signal C1 output from the temperature information output device 46 has a low level. When the output signal C1 has a low level, the transistor M15 is turned off. Therefore, when the transistor M15 is turned off, the sink formed by the two transistors M14 and M11 is operated with both transistors M14 and M11. Therefore, the turn-on resistance becomes large. In the state where the turn-on resistance of the sink is large, the voltage of the node N11 may be transitioned to the low level only when the back bias voltage VBB is lowered much. Here, the section in which the temperature is high, that is, the section in which the temperature information C1 has a low level is a section in which the cell transistor threshold voltage may drop sharply as compared with the section in which the above-described temperature is low. It is a section.

As described above, when the back bias voltage VBB is high in the state where the transistor M15 is turned off based on the low-level temperature information C1 detected in a high temperature environment, the gate terminals of the transistors M11 and M14 are provided. Since the input voltage level is high, the two transistors M14 and M11 are weakly turned on and have high resistance. At this time, since the transistor M10 is strongly turned on by the ground voltage VSS, a high level signal is applied to the node N11.

The high level signal applied to the node N11 causes a low level signal to be applied to the node N12 while turning on the transistor M12, and the low level signal is inverted by the inverter IV5, resulting in voltage detection. The output of the circuit 41 becomes a high level signal.

The high level signal output from the voltage detection circuit 41 is controlled to operate the oscillator 42 so that the pump circuit 44 performs the pumping operation, that is, lower the level of the back bias voltage further.

As described above, the operation process when the back bias voltage VBB is slightly lower than the target value (-0.8V) will be described.

In this case, unlike the low temperature environment described above, in the high temperature environment, the sink is operated by two transistors M14 and M11. Therefore, when the back bias voltage level input to the gate terminals of the two transistors M14 and M11 is slightly lower than −0.8 volts, the sink portion in which the two transistors M14 and M11 are connected in series is not yet strongly turned on. Transistor M11 has a turn-on transistor state that has not yet had a low resistance value.

Therefore, at this time, since the transistor M10 is strongly turned on by the ground voltage VSS, a high level signal is applied to the node N11.

The high level signal applied to the node N11 causes the low level signal to be applied to the node N12 while turning on the transistor M12, and the low level signal is inverted by the inverter IV5, resulting in a voltage. The output of the detection circuit 41 becomes a high level signal. The high level signal output from the voltage detection circuit 41 continues to operate the oscillator 42 and continues the pumping operation of the pump circuit 44 to further control the back bias voltage.

Subsequently, the operation process when the back bias voltage VBB is lower than the target value (−0.8V) while the above operation is continued will be described.

In this case, unlike the low temperature environment described above, in the high temperature environment, the sink is operated by two transistors M14 and M11. However, when the back bias voltage level input to the gate terminals of the two transistors M14 and M11 is much lower than -0.8 volts, the two transistors M14 and M11 are strongly turned on.

Therefore, since the turn-on capability of the two transistors M14 and M11 in the sink is stronger than the transistor M10 turned on by the ground voltage VSS, the node N11 is in a low level state.

The low level signal applied to the node N11 turns off the transistor M12 and turns on the transistor M13 to apply a high level signal to the node N12, and the high level signal is applied to the inverter IV5. Inverted at), and as a result, the output of the voltage detection circuit 41 becomes a low level signal. The low level signal output from the voltage detection circuit 41 stops the operation of the oscillator 42 and the pump circuit 44 so that the back bias voltage level is no longer lowered.

That is, in the internal voltage generation circuit of the present invention, a lower pumping voltage is generated in a high temperature environment and controlled to be supplied to the cell transistor. As shown in FIG. 11, when the pumping voltage lowered in the high temperature environment is supplied to the cell transistor, a threshold voltage change of the cell transistor according to temperature is shown in FIG. 11. As shown, according to the exemplary embodiment of the present invention, the threshold voltage of the conventional cell transistor drops sharply at a high temperature, whereas the threshold voltage of the cell transistor in the present invention is much lower. As a result, the threshold voltage of the cell transistor is increased at high temperature, thereby reducing off current.

In the above embodiment, the pumping voltage is described with an example of the back bias voltage, but the pumping voltage is not limited to the back bias voltage. That is, the pumping voltage may be a high voltage (VPP).

Preferred embodiments of the present invention described above are disclosed for the purpose of illustration, and may be applied when generating an internal voltage in response to a temperature change. Therefore, those skilled in the art will be able to improve, change, substitute or add other embodiments within the technical spirit and scope of the present invention disclosed in the appended claims.

1 is a block diagram of a pumping voltage generation circuit according to the prior art.

Figure 2 is a graph of the change in pumping voltage according to the conventional temperature change.

Figure 3 is a block diagram of a back bias voltage generation circuit according to the prior art.

4 is a detailed configuration diagram of a voltage detection circuit according to the prior art.

5 is a graph of the back bias voltage change according to the conventional temperature change.

6 is a block diagram of an internal voltage generation circuit according to an embodiment of the present invention.

FIG. 7 is a detailed configuration diagram of the pumping voltage regulating circuit shown in FIG. 6.

8 is a graph showing a change in pumping voltage according to temperature change in the present invention.

9 is a block diagram of an internal voltage generation circuit according to another embodiment of the present invention.

10 is a detailed configuration diagram of a voltage detection circuit according to the present invention.

11 is a graph of the back bias voltage according to the temperature change in the present invention.

Explanation of symbols on the main parts of the drawings

30: reference voltage generator 31, 41: voltage detection circuit

32,37,42: Oscillator 33,34,44: Pump circuit

35,45: Cell transistor 36,46: Temperature information output device

40: internal voltage generator

Claims (10)

Detection means for detecting a voltage level of the pumping voltage by comparing the reference voltage with the feedback pumping voltage; First oscillating means for generating a first clock signal based on an output signal of said detecting means; First pumping means for generating a pumping voltage based on the first clock signal; Temperature information output means for outputting different temperature information according to the temperature change; Second oscillating means for generating a second clock signal based on temperature information output from said temperature information output means; And Second pumping means for generating a pumping voltage based on the second clock signal; Internal voltage generation circuit having a. The method of claim 1, The second oscillation means, A NAND gate having the temperature information as a first input; A first delay circuit for delaying an output of the NAND gate by a first time; A second delay circuit delaying an output of the first delay circuit by a second time and providing the second delay circuit to a second input of the NAND gate; And an output terminal unit for outputting the output of the second delay circuit as a second clock signal. The method of claim 2, The first and second delay circuits are internal voltage generation circuits, characterized in that each consisting of a plurality of inverters. Temperature information output means for outputting different temperature information according to the temperature change; Detection means for comparing a pumping voltage fed back based on an internal voltage and the temperature information and detecting a level of the pumping voltage; Oscillating means for generating a clock signal based on an output signal of the detecting means; And pumping means for generating a pumping voltage based on the clock signal. The method of claim 4, wherein The detection means, A sink operated by the feedback pumping voltage; First switching means which is turned on based on the temperature information to adjust a turn-on resistance of the sink unit; A first driver configured to input the internal voltage and adjust and output a voltage level by a turn-on resistance of the sink; And a second driver for outputting a detection signal to lower a pumping voltage when the first driver outputs a high level signal. The method of claim 5, wherein And said sink portion connects two PMOS transistors in series. The method of claim 6, The first switching means, One of the two transistors forming the sink is connected between the drain and the source of the first transistor, and the turn-on resistance of the sink is formed only by the second transistor during the turn-on operation, and is formed by the first and second transistors in the turn-off operation. An internal voltage generation circuit, operative to form a turn-on resistance. The method of claim 7, wherein And the first switching means is an NMOS transistor for inputting temperature information to a gate terminal. The method of claim 5, wherein And the first driving unit is a PMOS transistor which inputs a ground voltage to a gate terminal and supplies an internal voltage. The method of claim 5, wherein The second driver is configured to output an internal voltage by connecting a PMOS transistor and an NMOS transistor which input an output of the first driver to a gate terminal in series, and receives a signal output by the operation of the two transistors. An internal voltage generation circuit comprising a butting inverter.

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