KR100825021B1 - Inner-voltage generator - Google Patents

Abstract

The present invention relates to an internal voltage generation circuit for generating an internal voltage that maintains a stable potential level even at a low power supply having a relatively low potential level, and generates a first reference voltage and a second reference voltage by receiving an external power supply voltage. A reference voltage generating means, a pumping voltage generating means for generating a pumping voltage, and a power source for detecting a potential level of the external power supply voltage in response to a first reference voltage and supplying the pumping voltage or the external power supply voltage according to a detection result And a supply means, an internal voltage generation means for generating an internal voltage in response to the second reference voltage and using the voltage provided from the power supply means as a power source, and an internal circuit for receiving the internal voltage and performing a set operation.

Low Power, Internal Power Generator, Pumping Voltage

Description

Internal Voltage Generator {INNER-VOLTAGE GENERATOR}

1 is a block diagram of a power supply of a DRAM according to the related art.

FIG. 2 is a circuit diagram showing in detail the internal voltage generator 20 shown in FIG. 1.

FIG. 3 is a simulation graph showing potential levels of a changing internal voltage when an internal voltage generated by receiving a normal power source and a low power source is used in an internal circuit according to the related art.

4 is a power supply block diagram of a DRAM according to an embodiment of the present invention.

5 is a circuit diagram illustrating in detail the internal voltage generation unit 200 and the power supply unit 400 shown in FIG. 4 according to an embodiment of the present invention.

6 is a simulation showing the potential level of the internal voltage that changes when each internal voltage generated by using a low power supply in the circuit according to the embodiment of the present invention and the circuit according to the prior art is used in the internal circuit ( simulation) Graph.

* Explanation of symbols for the main parts of the drawings.

100: reference voltage generator.

200: internal voltage generation unit.

300: internal circuit part.

400: power supply.

500: pumping voltage generator.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for generating an internal voltage for use in an internal circuit, and more particularly to an internal voltage generation circuit for generating an internal voltage maintaining a stable potential level even at a low power supply having a relatively low potential level.

Due to the high speed, high density, and low power of semiconductor memory devices, internal voltages have been used in DRAMs. In order to generate the internal voltage, a reference voltage having a reference potential is made, and the generated reference voltage is used by charge pumping or down converting.

Typical internal power sources using charge pumping include boost voltage (VPP) and back bias voltage (VBB). In addition, a representative internal power source using down converting is a core voltage VCORE.

In general, the boosted voltage VPP is made to apply a potential higher than the external power supply voltage VDD so that there is no loss of cell data to the gate (or word line) of the cell transistor to access the cell.

In addition, the back bias voltage VBB is made to apply a potential lower than the external ground voltage VSS to the bulk of the cell transistor in order to prevent loss of data stored in the cell.

In addition, the core voltage VCORE is down converted from the external power supply voltage VDD to reduce power loss and stabilize the operation of the core. The core voltage VCORE is lower than the external power supply voltage VDD. It is made by using an op-amp to maintain a constant potential against the fluctuation of.

1 is a block diagram of a power supply of a DRAM according to the related art.

Referring to FIG. 1, a power supply process of a DRAM in the related art is as follows.

First, the reference voltage generator 10 generates a reference voltage VREF for generating an internal voltage.

Second, the internal voltage generator 20 generates an internal voltage IN_VOL such as a boosted voltage VPP, a back bias voltage VBB, and a core voltage VCORE in response to the generated reference voltage VREF.

Third, the internal circuit unit 30 operates the circuit inside the semiconductor device by using the generated internal voltage IN_VOL.

FIG. 2 is a circuit diagram showing in detail the internal voltage generator 20 shown in FIG. 1.

Referring to FIG. 2, the internal voltage generator 20 may include a comparator configured to generate an internal voltage IN_VOL when the enable signal IN is logic 'high' and the reference voltage VREF is input. Include.

That is, when the enable signal IN is logic 'high', the PMOS transistors P2, P5 and P7 are turned off, and the NMOS transistor N3 is turned on to be internal. The voltage generator 20 starts to operate.

When the operation of the internal voltage generator 20 starts, it operates in two states according to the potential level of the half voltage HALF.

Here, the half voltage HALF means a voltage obtained by dividing the internal voltage IN_VOL output from the internal voltage generator 20 according to the resistance values of R1 and R2 as resistance elements. The rear side has a potential level equal to half the potential level of the internal voltage IN_VOL.

First, since the internal voltage generator 20 is in an initial state, the case where the potential level of the half voltage HALF is lower than the potential level of the reference voltage VREF will be described. Of course, it is assumed that the potential level of the half voltage HALF is higher than the threshold voltage Vt of N2 which is an NMOS transistor. In addition, it is assumed that the two input terminals of the comparator and the NMOS transistors N1 and N2 are transistors of the same size.

Since the potential level of the half voltage HALF is lower than that of the reference voltage VREF, the gate-source voltage VGS applied to N1 as the NMOS transistor has a potential level higher than the gate-source voltage VGS applied to N2. . That is, the voltage drop of the A node is greater than the voltage drop of the C node. The voltage drop of node A turns on the PMOS transistor P1, and the external voltage VDD supplied through P1 turns on the NMOS transistor N5 via B node. Similarly, the voltage drop of node C turns on P6, which is a PMOS transistor, but turns on less than N5, which is turned on by the voltage drop of node A. Is less than

Due to the above-described series of operations, the driving node ON_NODE becomes logic 'low', which causes the PMOS transistor P8 to be turned on to raise the potential level of the internal voltage IN_VOL. The internal voltage IN_VOL in which the potential level rises is continued until the potential level of the half voltage HALF becomes higher than the potential level of the reference voltage VREF.

The case where the potential level of the half voltage HALF is higher than the potential level of the reference voltage VREF is as follows.

Since the potential level of the half voltage HALF is higher than the potential level of the reference voltage VREF, the gate-source voltage VGS applied to N1 as the NMOS transistor has a potential level lower than the gate-source voltage VGS applied to N2. . That is, the voltage drop of the A node occurs smaller than the voltage drop of the C node. The voltage drop of node C turns on the PMOS transistor P6. Similarly, the voltage drop of node A turns on P1, a PMOS transistor, and the external voltage (VDD) supplied through P1 turns on N5, NMOS transistor, via node B, but C The charge supply force of N5 is smaller than P6 since it is turned on less than P6 which is turned on by the voltage drop of the node.

Due to the above-described series of operations, the driving node ON_NODE becomes logic 'high'. As a result, the PMOS transistor P8 is turned off and the external voltage VDD is turned off by the internal voltage generator 20. Do not supply to the output terminal of OUT. The above operation is continued until the potential level of the half voltage HALF is lower than the potential level of the reference voltage VREF.

FIG. 3 is a simulation graph showing potential levels of a changing internal voltage when an internal voltage generated by receiving a normal power source and a low power source is used in an internal circuit according to the related art.

Referring to FIG. 3, the internal voltage generator 20 receives a low power supply (VDD 1.6V low voltage) as compared with the normal power supply VDD 1.8V to generate the internal voltage IN_VOL. It can be seen that a problem occurs in generating the internal voltage IN_VOL.

First, the internal voltage IN_VOL generated by receiving the normal power supply (VDD 1.8V) and the internal voltage IN_VOL generated by receiving the low power supply (VDD 1.6V) may be used in the internal circuit 30 having the same operation. When the internal voltage IN_VOL generated using the low power supply (VDD 1.6V) falls to a lower potential level than the internal voltage IN_VOL generated using the normal power supply (VDD 1.8V). This is because the amount of charge supplied to the driver for driving the internal voltage inside the internal voltage generator 20-PMOS transistor P8-in FIG. 2 is higher when the normal power supply (VDD 1.8V) is lower than the low power supply (VDD 1.6V). to be.

Then, the internal voltage (IN_VOL) generated by receiving the normal power supply (VDD 1.8V) and the low power supply (VDD 1.6V) are used in the internal circuit 30 performing the same operation. The rate of recovery back to the original potential level is higher than the internal voltage (IN_VOL) generated using the low power supply (VDD 1.6V) compared to the internal voltage (IN_VOL) generated using the normal power supply (VDD 1.8V). slow. This is also because the charge supply capability of the driver for driving the internal voltage IN_VOL in the internal voltage generation unit 20-FIG. 2 is insufficient in the PMOS transistor P8.

Due to the above-described problem, the internal circuit 30 using the internal voltage IN_VOL may be defective.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide an internal voltage generation circuit for generating an internal voltage maintaining a stable potential level even at a low power supply having a relatively low potential level. .

According to an aspect of the present invention for achieving the above technical problem, the power supply means for detecting the potential level of the external power supply voltage, supplying a pumping voltage or the external power supply voltage according to the detection result; And an internal voltage generation means using the voltage provided from the power supply means as a power source.

According to another aspect of the present invention for achieving the above technical problem, a reference voltage generating means for generating a first reference voltage and a second reference voltage by receiving an external power supply voltage; Pumping voltage generating means for generating a pumping voltage; Power supply means for detecting a potential level of the external power supply voltage in response to the first reference voltage and supplying the pumping voltage or the external power supply voltage according to a detection result; Internal voltage generating means for generating an internal voltage in response to the second reference voltage and using the voltage provided from the power supply means as a power source; And an internal circuit configured to receive the internal voltage and perform a set operation.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention. However, the present invention is not limited to the embodiments disclosed below, but may be configured in various different forms, only this embodiment is intended to complete the disclosure of the present invention and to those skilled in the art the scope of the present invention It is provided to inform you completely.

4 is a power supply block diagram of a DRAM according to an embodiment of the present invention.

Referring to FIG. 4, a power supply process of a DRAM according to an embodiment of the present invention is as follows.

First, the reference voltage generator 100 generates a first reference voltage VREF1 for generating an internal voltage and a second reference voltage VREF2 for detecting an external power supply voltage VDDext.

Here, the first reference voltage VREF1 and the second reference voltage VREF2 may have the same potential level or may not be the same potential level.

Second, the pumping voltage generator 500 generates a pumping voltage VPP having a potential level higher than that of the external power supply voltage VDDext.

Here, the pumping voltage VPP is a power supply for reading and writing data to the cell transistor, and generally has a potential level higher than the external voltage VDDext supplied to operate the DRAM.

Third, the power supply unit 400 detects the potential level of the external power supply voltage VDDext in response to the second reference voltage VREF2, and when the potential level of the external power supply voltage VDDext is normal, that is, the normal power supply. In one case, the external power supply voltage VDDext is supplied to the power of the internal voltage generator 200. However, as a result of detection, when the potential level of the external power supply voltage VDDext is low, that is, when the power supply is low, the pumping voltage VPP generated by the pumping voltage generator 500 inside the semiconductor device is converted into the internal voltage generator 200. Supply by power.

Here, the determination of the case where the potential level of the external power supply voltage VDDext is a normal power supply or a low power supply can be changed by adjusting the second reference voltage VREF2 according to the type of semiconductor device. That is, it must be predetermined by the designer, and the result is variable.

Fourth, the internal voltage generator 200 generates an internal voltage IN_VOL such as a back bias voltage VBB and a core voltage VCORE in response to the first reference voltage VREF1.

Fifth, the internal circuit unit 300 receives the generated internal voltage IN_VOL and performs a set operation. That is, all the circuits of the memory device using the internal voltage IN_VOL.

5 is a circuit diagram illustrating in detail the internal voltage generation unit 200 and the power supply unit 400 shown in FIG. 4 according to an embodiment of the present invention.

5, the power supply unit 400 according to an embodiment of the present invention detects the potential level of the external power supply voltage (VDDext), and the pumping voltage (VPP) or the external power supply voltage (VDDext) according to the detection result Supply. The internal voltage generator 200 uses a voltage provided from the power supply unit 400-a pumping voltage VPP or an external power supply voltage VDDext-as a power source.

Here, the power supply unit 400 supplies the pumping voltage VPP to the power of the internal voltage generator 200 when the potential level of the external power supply voltage VDDext is a relatively low potential level. Similarly, when the potential level of the external power supply voltage VDDext is a relatively high potential level, the external power supply voltage VDDext is supplied to the power of the internal voltage generator 200.

In addition, the power supply unit 400 is connected in series between the external power supply voltage VDDext and the ground voltage VSS to generate a distribution voltage VDD_REF, a distribution voltage VDD_REF, and a second voltage distribution unit. A comparator 440 for comparing the reference voltage VREF2 and a driving unit 460 for driving the pumping voltage VPP or the external power supply voltage VDDext in response to the output voltage of the comparator 440.

Among the components of the power supply unit 400 described above, the voltage divider 420 may include the first resistor R1 and the second resistor R2 connected in series between the external power supply voltage VDDext and the ground voltage VSS. In addition, the division voltage VDD_REF is output from the connection node d_node of the first resistor R1 and the second resistor R2.

In addition, the comparator 440 of the components of the power supply unit 400 includes a current mirror in which an operation is controlled on / off in response to the enable signal EN.

Here, the current mirror includes an enable control unit 442 for enabling or disabling the current mirror in response to the enable signal EN, and a set resistance value. And a first resistance element 444 for outputting a voltage reduced by a voltage lowered by its resistance value from the distribution voltage VDD_REF to the output node out_node, and having a set resistance value and a second reference voltage. The second resistor element 446 outputting a voltage reduced by the voltage lowered by its resistance value from VREF2 to the control node con_node, and an output node out_node in response to the voltage applied to the control node con_node. And a mirror circuit 440 for adjusting the potential level of the voltage across the circuit.

In the current mirror, when the distribution voltage VDD_REF decreases, the voltage applied to the control node con_node decreases, and the voltage applied to the output node out_node increases.

In addition, in the current mirror, when the distribution voltage VDD_REF increases, the voltage applied to the control node con_node increases and the voltage applied to the output node out_node decreases.

Here, the enable control unit 442 of the components of the current mirror is a current source of the current mirror, and is a current mirror in response to the enable signal EN. Includes a first NMOS transistor (NMOS1) for controlling the connection with the ground voltage terminal VSS.

In addition, among the components of the current mirror, the first resistive element 444 may be a drain-source connected output node (out_node) in response to the division voltage VDD_REF input to the gate. ) And a second NMOS transistor (NMOS2) for controlling the connection of the current source (current source).

In addition, the second resistive element 446 among the components of the current mirror is a control node connected to a drain-source in response to the second reference voltage VREF2 input to the gate. and a third NMOS transistor NMOS3 for controlling the connection of the (con_node) and the current source.

Among the components of the power supply unit 400, the driving unit 460 drives the first driver to drive logic 'high' or logic 'low' in response to the output voltage of the comparator 440. 462, a second driver 464 driving the external power supply voltage VDDext in response to the output signal of the first driver 462, and a signal inverting the output signal of the first driver 462. And a third driver 466 for driving the pumping voltage VPP.

Here, the first driver 462 of the components of the driving unit 460 includes a plurality of inverters having a chain shape.

In addition, the second driver 464 of the components of the driving unit 460 is connected to a drain-source external power supply voltage in response to an output signal of the first driver 462 input to the gate. A first PMOS transistor PMOS1 is configured to control the connection between the VDDext and the power input node vol_input.

In addition, among the components of the driving unit 460, the third driver 466 may include a first inverter INV1 for inverting and outputting an output signal of the first driver 462, and a first inverter input to a gate. A second PMOS transistor PMOS2 is configured to control the connection of the drain-source connected pumping voltage VPP and the power input node vol_input in response to the output signal of INV1.

The internal voltage generation unit 200 generally has the same structure except for using a voltage provided from the power supply unit 400, such as a pumping voltage VPP or an external power supply voltage VDDext, as a power source in preparation for the prior art. I will not explain it here.

6 is a simulation showing the potential level of the internal voltage that changes when each internal voltage generated by using a low power supply in the circuit according to the embodiment of the present invention and the circuit according to the prior art is used in the internal circuit ( simulation) Graph.

Referring to FIG. 6, in the circuit according to the embodiment of the present invention and the circuit according to the related art shown in FIG. 1, each internal voltage IN_VOL generated by inputting a low power source (VDD 1.6V) is inputted to an internal circuit ( It can be seen that the potential levels of the internal voltage IN_VOL fluctuate differently when used at 30 and 300).

First, when the internal voltage 300 generated by inputting a low power supply (VDD 1.6V) to the circuit according to an embodiment of the present invention is used in the internal circuit 300, the circuit according to the related art shown in FIG. The internal voltage IN_VOL maintains a relatively higher potential level than the internal voltage IN_VOL generated by inputting the low power supply VDD 1.6V in the internal circuit 30.

Similarly, after the low voltage (VDD 1.6V) is input to the circuit according to the embodiment of the present invention and the internal voltage IN_VOL generated in the internal circuit 300 is used, the speed of returning to the original potential level is again shown in FIG. 1. After the low voltage (VDD 1.6V) is input to the circuit according to the related art illustrated in FIG. 6, the generated internal voltage IN_VOL is used in the internal circuit 30, and is faster than the speed of returning to the original potential level.

That is, the circuit according to the embodiment of the present invention is more stable operation than the prior art shown in FIG.

As described above, when the embodiment of the present invention is applied, the potential level of the internal voltage used in the internal circuit can be stably maintained even when a low power source is input because the potential level of the external power voltage is lowered. This enables stable operation of the semiconductor device.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill.

For example, the logic gate and the transistor illustrated in the above-described embodiment should be implemented differently in position and type depending on the polarity of the input signal.

According to the present invention described above, even when a low power source is input because the potential level of the external power supply voltage is lowered, the potential level of the internal voltage used in the internal circuit can be stably maintained. This enables stable operation of the semiconductor device.

Claims (19)

Power supply means for detecting a potential level of an external power supply voltage and supplying a pumping voltage or the external power supply voltage according to a detection result; And Internal voltage generating means using a voltage provided from said power supply means as a power source Internal voltage generation circuit comprising a. The method of claim 1, The power supply means, And the pumping voltage is supplied to the power of the internal voltage generating means when the potential level of the external power supply voltage is a relatively low potential level. The method of claim 1, The power supply means, And when the potential level of the external power supply voltage is a relatively high potential level, supplying the external power supply voltage to a power source of the internal voltage generation means. The method of claim 1, The power supply means, A voltage distribution unit connected in series between the external power supply voltage and a ground voltage to generate a distribution voltage; A comparison unit comparing the divided voltage and a reference voltage; And A driving unit driving the pumping voltage or the external power supply voltage in response to an output voltage of the comparator Internal voltage generation circuit comprising: a. The method of claim 4, wherein The voltage division unit, And a first resistor and a second resistor connected in series between the external power supply voltage and the ground voltage, to output the divided voltage at a connection node of the first and second resistors. The method of claim 4, wherein The comparison unit, And a current mirror, the operation of which is controlled on / off in response to the enable signal. The method of claim 6, The current mirror, An enable controller for enabling or disabling the current mirror in response to the enable signal; A first resistance element having a set resistance value and outputting a voltage reduced by a voltage lowered by its resistance value from the distribution voltage to an output node; A second resistance element having the set resistance value and outputting a voltage reduced by a voltage lowered by its resistance value from the reference voltage to a control node; And A mirror circuit for adjusting the potential level of the voltage applied to the output node in response to the voltage applied to the control node Internal voltage generation circuit comprising: a. The method of claim 7, wherein The current mirror, And when the distribution voltage decreases, the voltage applied to the control node drops, and the voltage applied to the output node rises. The method of claim 7, wherein The current mirror, And the voltage applied to the control node increases and the voltage applied to the output node decreases when the distribution voltage increases. The method of claim 7, wherein The enable control unit, And a first NMOS transistor as a current source of the current mirror, the first NMOS transistor controlling the current mirror to be connected to a ground voltage terminal in response to the enable signal. The method of claim 7, wherein The first resistance element, And a second NMOS transistor configured to control a current source connected to the output node connected to the drain source in response to the division voltage input to the gate. The method of claim 7, wherein The second resistance element, And a third NMOS transistor configured to control a current source connected to the control node connected to the drain source in response to the reference voltage input to the gate. The method of claim 4, wherein The driving unit, A first driver driving a logic 'high' or a logic 'low' in response to an output voltage of the comparator; A second driver driving the external power supply voltage in response to an output signal of the first driver; A third driver driving the pumping voltage in response to a signal inverting the output signal of the first driver Internal voltage generation circuit comprising: a. The method of claim 13, The first driver, An internal voltage generation circuit comprising a plurality of inverters having a chain shape. The method of claim 13, The second driver, And a first PMOS transistor configured to control the connection between the drain-source connected external power voltage and a power input node in response to an output signal of the first driver input to the gate. The method of claim 13, The third driver, A first inverter for inverting and outputting the output signal of the first driver; And And a second PMOS transistor configured to control the connection of the drain-source connected pumping voltage and a power input node in response to the output signal of the first inverter input to the gate. Reference voltage generating means for receiving an external power supply voltage and generating a first reference voltage and a second reference voltage; Pumping voltage generating means for generating a pumping voltage; Power supply means for detecting a potential level of the external power supply voltage in response to the first reference voltage and supplying the pumping voltage or the external power supply voltage according to a detection result; Internal voltage generating means for generating an internal voltage in response to the second reference voltage and using the voltage provided from the power supply means as a power source; And An internal circuit that receives the internal voltage and performs a set operation Internal voltage generation circuit comprising a. The method of claim 17, The power supply means, And the pumping voltage is supplied to the power of the internal voltage generating means when the potential level of the external power supply voltage is a relatively low potential level. The method of claim 17, The power supply means, And when the potential level of the external power supply voltage is a relatively high potential level, supplying the external power supply voltage to a power source of the internal voltage generation means.

Images