KR20140019942A - Voltage supply circuit - Google Patents

Voltage supply circuit Download PDF

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Publication number
KR20140019942A
KR20140019942A KR1020120086072A KR20120086072A KR20140019942A KR 20140019942 A KR20140019942 A KR 20140019942A KR 1020120086072 A KR1020120086072 A KR 1020120086072A KR 20120086072 A KR20120086072 A KR 20120086072A KR 20140019942 A KR20140019942 A KR 20140019942A
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KR
South Korea
Prior art keywords
voltage
external
driving
control signal
level
Prior art date
Application number
KR1020120086072A
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Korean (ko)
Inventor
이성준
Original Assignee
에스케이하이닉스 주식회사
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Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020120086072A priority Critical patent/KR20140019942A/en
Publication of KR20140019942A publication Critical patent/KR20140019942A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The voltage supply circuit according to the present technology includes a driving voltage generator for boosting an internal voltage and outputting a driving voltage, and comparing the voltage level of the driving voltage with an external voltage and selectively outputting the voltage as a power supply voltage of a DLL circuit.

Description

Voltage Supply Circuit

The present invention relates to a semiconductor device, and more particularly to a voltage supply circuit of a delay locked loop circuit.

In general, a semiconductor memory device outputs data synchronized with an external clock signal to an external device during a read operation. That is, an internal clock signal, not an external clock signal, is used to output data in the semiconductor memory device. Therefore, in the read operation, the read command synchronized with the external clock signal must be synchronized with the internal clock signal. From the standpoint of the read command, the synchronized clock signal is changed from an external clock signal to an internal clock signal. The change of the signal to be synchronized from one clock signal to another is called "domain crossing".

Meanwhile, skew may occur between the external clock signal and the internal clock signal due to a delay element in the semiconductor memory device, and an internal clock signal generation circuit is provided in the semiconductor memory device to compensate for this. Representative examples of the internal clock signal generation circuit include a phase locked loop and a delay locked loop (DLL). In an embodiment of the present invention, a DLL clock signal generated in a delay locked loop is used as an internal clock signal as an example.

1 is a general DLL circuit 10.

The DLL circuit 10 includes a DLL delay line 11, a DLL replica model unit 13, and a phase detector 12.

The DLL delay line 11 outputs the DLL clock signal DLLCLK by delaying the external clock signal EXTCLK for a predetermined time. The DLL replica model unit 13 models the degree of delay until the DLL clock signal DLLCLK is output to the outside of the semiconductor memory device. The DLL replica model unit 13 delays the DLL clock signal DLLCLK by a predetermined time to feed back the feedback clock signal FBCLK. ) Therefore, the feedback clock signal FBCLK includes information about the delay amount of the DLL delay line 11 and the delay amount until output to the outside of the semiconductor memory device.

The phase detector 12 outputs a control signal CNT_DLY for adjusting the delay amount of the DLL delay line 11 by comparing the clock phase of the external clock signal EXTCLK and the feedback clock signal FBCLK. The phase detector 12 compares the clock phases of the external clock signal EXTCLK and the feedback clock signal FBCLK and controls the delay amount of the DLL delay line 11 until the phase becomes the same.

The DLL circuit 10 uses an external voltage as the power supply voltage VDDL.

Recently, an external voltage level applied to a semiconductor memory device is decreasing. Therefore, the voltage level applied to the DLL replica model unit 13 is lowered, so that skew occurs and the signal delay time is long. In addition, since skew occurs in the DLL replica model unit 13, there is a problem in that a jitter phenomenon occurs in which the DLL clock signal DLLCLK fluctuates irregularly.

The present invention has been made to solve the above problems, and provides a voltage supply circuit for stably supplying a voltage to a delay locked loop (DLL) circuit.

The voltage supply circuit according to the embodiment of the present invention includes a driving voltage generation unit for outputting a driving voltage by boosting an internal voltage, and compares the voltage level of the driving voltage with an external voltage and selectively outputs the power voltage of a DLL circuit. .

The voltage supply circuit according to another embodiment of the present invention compares the driving voltage generated by boosting the internal voltage and the voltage level of the external voltage, and compares the driving voltage if the voltage level of the driving voltage is higher than the voltage level of the external voltage. And outputs the power supply voltage of the circuit, and outputs the external voltage to the power supply voltage of the DLL circuit when the voltage level of the driving voltage is lower than the voltage level of the external voltage.

 The semiconductor device according to the present invention can secure a correct output timing of the DLL clock signal by supplying a stable voltage to the delay locked loop circuit.

1 is a typical DLL circuit,
2 is a schematic block diagram of a voltage supply circuit according to an embodiment of the present invention;
3 is a circuit diagram of a reference voltage generator of FIG. 2;
4 is a circuit diagram of a voltage sensing unit of FIG. 2;
5 is a circuit diagram of the voltage selector of FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

2 is a schematic block diagram of a voltage supply circuit 100 according to an embodiment of the present invention.

Referring to FIG. 2, the voltage supply circuit 100 will be described below. The voltage supply circuit 100 includes a driving voltage generator 111, a voltage detector 130, and a voltage selector 140.

The driving voltage generator 111 includes a reference voltage generator 110 and a voltage pump 120.

The voltage supply circuit 100 generates the driving voltage VCLK using the internal voltage VIN having a constant voltage level, and outputs the external voltage VDD or the driving voltage VCLK as the power supply voltage VDDL.

Since the internal voltage VIN has a constant voltage level compared to the external voltage VDD, the voltage supply circuit 100 generates the driving voltage VCLK using the internal voltage VIN. In addition, the voltage supply circuit 100 outputs the external voltage VDD as the power supply voltage VDDL when the external voltage VDD is equal to or higher than the voltage level of the driving voltage VCLK.

That is, in order to prevent jitter from occurring in the DLL circuit because the voltage level of the external voltage VDD is lower than the driving voltage VCLK, the voltage supply circuit 100 has a voltage level of the external voltage VDD. When it is lower than VCLK, the driving voltage VCLK is output as the power supply voltage VDDL of the DLL circuit. On the contrary, when the voltage level of the external voltage VDD is higher than the driving voltage VCLK, the external voltage VDD is output as the power supply voltage VDDL of the DLL circuit.

Here, the internal voltage VIN may be a voltage used in the semiconductor memory device having a constant voltage level such as the pumping voltage VPP, the core voltage VCORE, or the bit line precharge voltage VBLP.

The driving voltage generator 111 generates the driving voltage VCLK using the internal voltage VIN.

The reference voltage generator 110 divides the internal voltage VIN to generate a reference voltage VREF. The voltage pump unit 120 boosts the voltage level of the reference voltage VREF to output the driving voltage VCLK. The voltage detector 130 compares the external voltage VDD with the driving voltage VCLK and generates a control signal CNT that is disabled when the driving voltage VCLK is higher than the external voltage VDD.

The voltage selector 140 outputs the driving voltage VCLK or the external voltage VDD as the power supply voltage VDDL in response to the control signal CNT.

The reference voltage generator 110 divides the internal voltage VIN to output a reference voltage VREF having a predetermined voltage level. At this time, the voltage level of the reference voltage VREF does not cause jitter in the DLL circuit. Not enough voltage levels are justified.

The voltage pump unit 120 boosts the voltage level of the reference voltage VREF to a predetermined voltage and outputs a driving voltage VCLK.

The voltage detector 130 compares the external voltage VDD and the driving voltage VCLK to generate a control signal CNT that is enabled when the driving voltage VCLK is lower than the voltage level of the external voltage VDD. When the driving voltage VCLK is higher than the voltage level of the external voltage VDD, the control signal CNT is disabled. At this time, the control signal CNT has a logic low in the disable state and has a logic high in the enable state.

The voltage selector 140 outputs the driving voltage VCLK as the power supply voltage VDDL in response to the control signal CNT in the disabled state, and outputs an external voltage VDD in response to the control signal CNT in the enabled state. ) Is outputted to the power supply voltage (VDDL).

3 is a reference voltage generator 110 of FIG. 2.

The reference voltage generator 110 is connected between the internal voltage VIN and the first node n1 and receives the internal voltage VIN and the first NMOS transistor N1 and the first node n1 and the ground voltage. And a second NMOS transistor N2 connected between the VSSs and receiving an output signal of the first node n1. The reference voltage VREF is output from the first node n1. In the exemplary embodiment of the present invention, the reference voltage VREF is generated by connecting a plurality of transistors in series, but the reference voltage VREF may be generated using a resistor connected in series. At this time, the reference voltage generator 110 outputs the internal voltage VIN as the reference voltage VREF by arranging a plurality of transistors or a plurality of resistors such that the reference voltage VREF does not cause jitter in the DLL circuit. .

4 is the voltage detector 140 of FIG. 2.

The voltage sensing unit 140 may be configured as an amplifier for generating a control signal CNT by comparing the voltage of the external voltage VDD and the power supply voltage VDDL.

The voltage detector 130 compares the external voltage VDD and the driving voltage VCLK to generate a control signal CNT that is enabled when the driving voltage VCLK is lower than the voltage level of the external voltage VDD. When the driving voltage VCLK is higher than the voltage level of the external voltage VDD, the control signal CNT is disabled.

5 is the voltage selector 140 of FIG. 2.

The voltage selector 140 is configured to determine whether to output the driving voltage VCLK in response to the inverter IV inverting and outputting the control signal CNT and the output signals of the control signal CNT and the inverter IV. The second pass gate PG2 determines whether to output the external voltage VDD in response to the first pass gate PG1 and the control signal CNT and the output signal of the inverter IV.

Referring to FIGS. 2 to 5, the power supply voltage VDDL of the prior art and the power supply voltage VDDL according to the embodiment of the present invention are compared.

In the power supply circuit 100 according to the embodiment of the present invention, the DLL circuit uses the internal voltage VIN having a voltage level such that jitter does not occur and converts the driving voltage VCLK into the DLL circuit as the power supply voltage VDDL. Supply. However, when the external voltage VDD is higher than the driving voltage VCLK such that the DLL circuit does not cause jitter, the external voltage VDD is compared with the driving voltage VCLK and the external voltage VDD. Output by the power supply voltage (VDDL). Therefore, in the related art, since the power supply voltage VDDL supplied to the DLL circuit is dependent on the external voltage VDD, even if the external voltage VDD is low enough to cause jitter in the DLL circuit, the external voltage VDD is applied to the DLL circuit. It was supplied at the power supply voltage (VDDL) of.

However, the power supply circuit 100 according to the embodiment of the present invention supplies the power supply voltage VDDL of the DLL circuit by using the internal voltage VIN having a constant voltage level, and the external voltage VDD is supplied to the DLL circuit. If the voltage level is maintained enough to supply a stable voltage, the external voltage VDD is output as the power supply voltage VDDL of the DLL circuit.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims and their equivalents. Only. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

10: DLL circuit 11: DLL delay line
12: phase detection unit 13: DLL replica model unit
100: voltage supply circuit 110: reference voltage generator
111: driving voltage generator 120: voltage pump unit
130: voltage detector 140: voltage selector

Claims (10)

And a driving voltage generator for boosting an internal voltage to output a driving voltage, and comparing the voltage level between the driving voltage and an external voltage and selectively outputting the voltage as a power supply voltage of a DLL circuit.
The method of claim 1,
The voltage supply circuit
A voltage detector configured to generate a control signal by comparing the driving voltage and the external voltage; And
And a voltage selector configured to output the driving voltage or the external voltage as the power voltage in response to the control signal.
3. The method of claim 2,
The driving voltage generator
A reference voltage generator configured to divide the internal voltages to generate a reference voltage; And
And a voltage pump unit configured to boost the reference voltage to output the driving voltage.
The method of claim 3, wherein
The voltage sensing unit
The control signal is disabled when the voltage level of the driving voltage is higher than the voltage level of the external voltage by comparing the driving voltage with the external voltage, and the voltage level of the driving voltage is lower than the voltage level of the external voltage. And a voltage supply circuit for outputting the control signal that is enabled.
5. The method of claim 4,
The voltage selector
And a voltage supply circuit outputting the driving voltage as the power supply voltage in response to the disabled control signal, and outputting the external voltage as the power supply voltage in response to the enabled control signal.
When the voltage level of the driving voltage is higher than the voltage level of the external voltage by comparing the driving voltage generated by boosting the internal voltage and the voltage level of the external voltage, the driving voltage is output as the power supply voltage of the DLL circuit, and the driving voltage And outputting the external voltage as a power supply voltage of the DLL circuit when the voltage level is lower than the voltage level of the external voltage.
The method according to claim 6,
The voltage supply circuit
A driving voltage generator for boosting the internal voltage to output the driving voltage;
A voltage detector configured to generate a control signal by comparing the driving voltage and the external voltage; And
And a voltage selector configured to output the driving voltage or the external voltage as the power voltage in response to the control signal.
8. The method of claim 7,
The driving voltage generator
A reference voltage generator configured to divide the internal voltages to generate a reference voltage; And
And a voltage pump unit configured to boost the reference voltage to output the driving voltage.
The method of claim 8,
The voltage sensing unit
The control signal is disabled when the voltage level of the driving voltage is higher than the voltage level of the external voltage by comparing the driving voltage with the external voltage, and the voltage level of the driving voltage is lower than the voltage level of the external voltage. And a voltage supply circuit for outputting the control signal that is enabled.
The method of claim 9,
The voltage selector
And a voltage supply circuit outputting the driving voltage as the power supply voltage in response to the disabled control signal, and outputting the external voltage as the power supply voltage in response to the enabled control signal.
KR1020120086072A 2012-08-07 2012-08-07 Voltage supply circuit KR20140019942A (en)

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KR1020120086072A KR20140019942A (en) 2012-08-07 2012-08-07 Voltage supply circuit

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Application Number Priority Date Filing Date Title
KR1020120086072A KR20140019942A (en) 2012-08-07 2012-08-07 Voltage supply circuit

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040083809A (en) * 2003-03-25 2004-10-06 주식회사 하이닉스반도체 The Driving Circuit of Pseudo SRAM
KR20050041197A (en) * 2003-10-30 2005-05-04 주식회사 하이닉스반도체 Power supply apparatus for delay locked loop and its method
KR20080001280A (en) * 2006-06-29 2008-01-03 주식회사 하이닉스반도체 Inner-voltage generator
KR20080061955A (en) * 2006-12-28 2008-07-03 주식회사 하이닉스반도체 Inner voltage generation circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20040083809A (en) * 2003-03-25 2004-10-06 주식회사 하이닉스반도체 The Driving Circuit of Pseudo SRAM
KR20050041197A (en) * 2003-10-30 2005-05-04 주식회사 하이닉스반도체 Power supply apparatus for delay locked loop and its method
KR20080001280A (en) * 2006-06-29 2008-01-03 주식회사 하이닉스반도체 Inner-voltage generator
KR20080061955A (en) * 2006-12-28 2008-07-03 주식회사 하이닉스반도체 Inner voltage generation circuit

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