JP2008219946A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enable a delay time to be adjusted with high precision. <P>SOLUTION: A semiconductor device includes a plurality of inverted-output logic gates being cascaded, and a load capacitance circuit which uses oxide film capacitance of an MOS transistor as load capacitance to vary a load capacitance value in response to a control signal. By connecting the load capacitance circuit to an output terminal of the inverted-output logic gates, the delay time can be more finely controlled, such that the delay time can be adjusted with high precision. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and is particularly suitable for use in a DLL (Delay Locked Loop) circuit.

  A DLL (Delay Locked Loop) circuit is used as an interface of a memory capable of reading and writing data in synchronization with a clock signal such as a DDR (Double Data Rate) memory. The DLL circuit uses a PLL (Phase Locked Loop) function to adjust a delay time (output delay) until an input signal is output. That is, the DLL circuit compares the reference clock signal from the outside with the clock signal generated by the internal voltage controlled oscillation circuit to control the oscillation frequency of the clock signal, and uses this control signal to set the delay time. adjust.

  However, normally, a semiconductor device such as a DLL circuit has one voltage controlled oscillation circuit. Therefore, conventionally, the range of the oscillation frequency of the clock signal that can be generated internally is limited, and the range of the reference clock signal that can be handled by the DLL circuit is also limited.

  As one method for solving such a problem, a voltage-controlled oscillator circuit in which a selector is provided in a ring oscillator circuit (an inverter chain in which inverter circuits are cascade-connected) included in the voltage-controlled oscillator circuit to enable switching control of the number of stages. (For example, see Patent Document 1).

  Also, in the conventional voltage controlled oscillator circuit, the output of the inverter circuit in the ring oscillator circuit can be appropriately connected to a capacitor with one end grounded to increase the load capacitance at the output of the inverter circuit. There is one that can adjust the frequency (for example, see Patent Document 2).

  However, the voltage controlled oscillation circuit described in Patent Document 1 has a selector for controlling the number of stages in the loop of the ring oscillation circuit. Therefore, as shown in FIGS. 9A and 9B, the duty ratio of the generated clock signal that should be 5: 5 collapses as shown in FIGS. 9C and 9D. There was a problem of fear. Since the duty ratio of the clock signal to be generated is lost, there is a possibility that a great trouble is caused at the time of high-speed operation particularly as shown in FIG. For example, when used in a DLL circuit, there is a possibility that the delay time cannot be controlled in high-speed operation.

  Further, in a voltage controlled oscillation circuit in which the oscillation frequency can be adjusted by appropriately connecting a capacitor having one end grounded to the output of the inverter circuit in the ring oscillation circuit, see FIGS. 10A and 10B below. There was a problem as explained.

  In FIG. 10A, the inverter circuit I101 connected to the power supply line Vdd and the ground line Vss inverts the input signal Vin that is input and outputs it to the output node Va. The output of the inverter circuit I101 is connected to the other end of the capacitor C2 whose one end is grounded via a transistor T101 to which the control signal VCont is supplied to the gate. The transistor T101 is turned on / off by the control signal VCont to control the load capacitance at the output of the inverter circuit I101. Here, in the transistor T101, parasitic capacitances Ca and Cb exist as shown in FIG. 10B. Since these capacitances are bulk capacitances, the capacitance is basically large. In FIG. 10B, 102 is a drain, 103 is a source, and 104 is a gate.

  Therefore, in a voltage controlled oscillation circuit in which a capacitor having one end grounded can be appropriately connected to the output of the inverter circuit in the ring oscillation circuit, when the transistor T101 is in an off state, the bulk is connected to the output of the inverter circuit I101. When the capacitor Ca is added and the transistor T101 is in the on state, bulk capacitors Ca and Cb are added in addition to the capacitor C2. As described above, since the bulk capacitors Ca and Cb are basically large in capacity, it is difficult to control the minute oscillation frequency, that is, the delay time.

Japanese Patent Laid-Open No. 5-343956 JP-A-8-102643

  It is an object of the present invention to adjust the delay time with high accuracy.

  The semiconductor device according to the present invention is connected to the output gates of the plurality of inverted output logic gates and the inverted output logic gates, and uses the oxide film capacitance of the MOS transistor as the load capacitance according to the control signal. A load capacitance circuit that varies the capacitance value. According to the configuration, the delay time can be controlled more minutely, and the delay time can be adjusted with high accuracy.

  According to the present invention, a load that is connected to a plurality of cascade-connected logic gates of inverted outputs and an output terminal of the logic gates of inverted outputs and uses the oxide film capacitance of a MOS transistor as a load capacitance to vary the load capacitance value. By including the capacitor circuit, the delay time can be controlled more minutely than before, and the delay time can be adjusted with high accuracy.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration example of a DLL (delay locked loop) circuit to which a semiconductor device according to an embodiment of the present invention is applied. The DLL circuit in this embodiment includes a phase comparison circuit 11, a filter circuit (Low Pass Filter) 14, a voltage controlled oscillation circuit (VCO) 15, and a delay circuit (Delay module) 16.

  The phase comparison circuit 11 receives a reference clock signal FIN as a reference clock signal and a delayed clock signal FB as a feedback clock signal. Here, the reference clock signal FIN is a signal supplied from the outside, and the delayed clock signal FB is a signal supplied from the voltage controlled oscillation circuit 15. The phase comparison circuit 11 compares the phases of the two clock signals FIN and FB and outputs a voltage signal CPO corresponding to the comparison result to the filter circuit 14.

  Specifically, the phase comparison circuit 11 includes a phase comparison unit (Phase Comparator) 12 and a charge pump 13. The phase comparator 12 receives the reference clock signal FIN and the delayed clock signal FB, and compares the phases of the input clock signals FIN and FB. Further, the phase comparison unit 12 outputs an up signal UP and a down signal DOWN to the charge pump 13 according to the comparison result. The charge pump 13 changes and outputs the output voltage of the voltage signal CPO according to the up signal UP and the down signal DOWN.

  The filter circuit 14 performs a filtering process on the input voltage signal CPO and outputs the filter output to the voltage controlled oscillation circuit 15 as the voltage signal VCI. The filter circuit 14 is usually composed of a low-pass filter.

  The voltage controlled oscillation circuit 15 outputs a delay clock signal FB having an oscillation frequency corresponding to the voltage of the input voltage signal VCI, that is, a comparison result in the phase comparison circuit 11, and delay control corresponding to the voltage of the voltage signal VCI. Signals PC and NC are output. The voltage control oscillation circuit 15 receives the selection signal SEL and the capacitance control signal CO. The details of the voltage controlled oscillation circuit 15 will be described later.

  The delay circuit 16 receives an input signal DLLI from the outside, and receives delay control signals PC and NC from the voltage controlled oscillation circuit 15. The delay circuit 16 delays the input signal DLLI for a predetermined time according to the delay control signals PC and NC, and then outputs it as the output signal DLLO. Details of the delay circuit 16 will be described later.

FIG. 2 is a block diagram illustrating a configuration example of the voltage controlled oscillation circuit 15.
The voltage controlled oscillation circuit 15 includes one current mirror circuit 21, a plurality of ring oscillation circuits configured by inverter circuits I1, I2, I3,.

  The current mirror circuit 21 receives a voltage signal VCI and outputs delay control signals PC and NC having a voltage corresponding to the voltage signal VCI, and is configured as shown in FIG. 3A, for example. The delay control signals PC and NC are supplied to the inverter circuits I1, I2, I3,... And also to the delay circuit 16 shown in FIG.

  FIG. 3A is a diagram illustrating a circuit configuration of the current mirror circuit 21. In FIG. 3A, T31 and T33 are P-channel MOS transistors, and T32 and T34 are N-channel MOS transistors. The sources of the transistors T31 and T33 are connected to the power supply VDD, and the sources of the transistors T32 and T34 are connected to the ground level (grounded). The voltage signal VCI is supplied to the gate of the transistor T32.

  The drain of the transistor T31 is connected to the drain of the transistor T32, and the gates of the transistors T31 and T33 are connected to the interconnection point of the drains of the transistors T31 and T32. Further, an output signal line of the delay control signal PC is connected to an interconnection point between the drains of the transistors T31 and T32.

  Similarly, the drain of the transistor T33 is connected to the drain of the transistor T34, and the gate of the transistor T34 is connected to the interconnection point of the drains of the transistors T33 and T34. Further, an output signal line of the delay control signal NC is connected to an interconnection point between the drains of the transistors T33 and T34.

  Returning to FIG. 2, the plurality of ring oscillation circuits included in the voltage controlled oscillation circuit 15 have different numbers of stages and are independent of each other. As shown in FIG. 2, one inverter circuit I1 forms a one-stage ring oscillation circuit by feeding back an output to its input, and three inverter circuits I2, I3, and I4 connected in cascade are the final stage. The output of the inverter circuit I4 is fed back to the input of the first-stage inverter circuit I2, thereby forming a three-stage ring oscillation circuit.

  Similarly, the five cascaded inverter circuits I5, I6, I7, I8, and I9 return a 5-stage ring oscillation by feeding back the output of the final-stage inverter circuit I9 to the input of the first-stage inverter circuit I5. Configure the circuit.

  That is, in the voltage-controlled oscillation circuit 15, (2m-1) (m is a natural number and is different for each ring oscillation circuit), that is, in an inverter chain in which an odd number of inverter circuits are subordinate, Ring oscillation circuits with different numbers of stages are configured by feeding back the output of the inverter circuit of the stage to the inverter circuit of the first stage.

  Here, the delay control signals PC and NC are supplied to the inverter circuits I1, I2, I3,... Constituting the ring oscillation circuit, respectively.

  FIG. 3B is a diagram illustrating a circuit configuration of an inverter circuit included in the ring oscillation circuit. In FIG. 3B, T35 and T36 are P-channel MOS transistors, and T37 and T38 are N-channel MOS transistors.

  The source of the transistor T35 is connected to the power supply VDD, and the drain is connected to the source of the transistor T36. The source of the transistor T38 is connected to the ground level (grounded), and the drain is connected to the source of the transistor T37. The drain of the transistor T36 and the drain of the transistor T37 are connected, and the interconnection point is the output node OUT.

  Further, the delay control signal PC is supplied to the gate of the transistor T35, and the delay control signal NC is supplied to the gate of the transistor T38. An input signal IN is supplied to the gates of the transistors T36 and T37.

  By configuring the inverter circuits I1, I2, I3,... As described above, the transistors T35 and T38 act like variable resistors controlled by the delay control signals PC and NC, and the voltages of the delay control signals PC and NC. Accordingly, the amount of current in the transistors T35 and T38 is controlled. As a result, the voltage applied to the transistors T36 and T37 changes, and the delay time of the inverter circuit changes. That is, the delay time of the inverter circuit is controlled by the voltages of the delay control signals PC and NC. Therefore, the oscillation frequency of the ring oscillation circuit can be controlled by the delay control signals PC and NC based on the voltage signal VCI indicating the comparison result in the phase comparison circuit 11.

  The selector (selection circuit) 22 receives the outputs of the inverter circuits I1, I4, and I9 at the final stage in the ring oscillation circuit, that is, the oscillation outputs of a plurality of ring oscillation circuits independent from each other. The selector 22 selects one oscillation output from the inputted oscillation outputs according to the selection signal SEL supplied from the outside, and selectively outputs it as a delayed clock signal FB.

  In FIG. 2, one-stage, three-stage, and five-stage ring oscillation circuits are shown as an example. However, the present invention is not limited to this, and the voltage-controlled oscillation circuit 15 further includes any odd-numbered stages (for example, , 7 stages, 9 stages,...)).

FIG. 4 is a block diagram illustrating a configuration example of the delay circuit 16.
The delay circuit 16 includes an even number of subordinate inverter circuits I41 to I46 (inverter chain).

  The delay circuit 16 is supplied with an input signal DLLI as an input of the first-stage inverter circuit I41, and supplies this output as an input of the next-stage inverter circuit I42. Similarly, the output of each inverter circuit is supplied as the input of the next-stage inverter circuit. Then, the output of the final stage inverter circuit I46 is output as the output signal DLLO.

  Further, each of the inverter circuits I41 to I46 is supplied with delay control signals PC and NC, and is configured in the same manner as the inverter circuit shown in FIG. 3B. Therefore, the delay time of the entire delay circuit 16 can be controlled by controlling the delay times of the inverter circuits I41 to I46 by the voltages of the delay control signals PC and NC.

Next, the operation will be described.
First, the phase comparison unit 12 in the phase comparison circuit 11 compares the phases of the input reference clock signal FIN and the delayed clock signal FB, and supplies the comparison result to the charge pump 13 by the up signal UP and the down signal DOWN. The charge pump 13 changes the output voltage of the voltage signal CPO according to the up signal UP and the down signal DOWN. When the phase comparison unit 12 compares the phases of the clock signals FIN and FB, if they match, the up signal UP and the down signal DOWN are not output (not activated) and output from the charge pump 13. The output voltage of the applied voltage signal CPO does not change.

  Next, the filter circuit 14 performs a filtering process on the voltage signal CPO and outputs it to the voltage control supply circuit 15 as a voltage signal VCI. The current mirror circuit 21 in the voltage control supply circuit 15 generates delay control signals PC and NC corresponding to the voltage of the voltage signal VCI, and includes inverter circuits I1, I2, I3,. 16 is supplied.

  As a result, an oscillation signal having an oscillation frequency corresponding to the delay control signals PC and NC is output from each of the plurality of ring oscillation circuits in the voltage control oscillation circuit 15. The selector 22 selects any one of the oscillation signals output from the plurality of ring oscillation circuits according to the selection signal SEL, and outputs the selected oscillation signal as the delayed clock signal FB.

  By repeating the above operation, a delayed clock signal FB that matches the reference clock signal FIN is obtained. That is, when the reference clock signal FIN and the delayed clock signal FB do not match, the voltage signal VCI changes according to the difference between the reference clock signal FIN and the delayed clock signal FB, and the delay control signals PC and NC change accordingly. To do. As a result, the delay times of the inverter circuits I1, I2, I3,... Constituting the plurality of ring oscillation circuits change, and the oscillation frequency of the oscillation signal output as the delayed clock signal FB changes so that the deviation becomes small. .

  On the other hand, when the reference clock signal FIN and the delayed clock signal FB match, the voltage signal VCI and the delay control signals PC and NC do not change. Therefore, the delay times of the inverter circuits I1, I2, I3,... Constituting the plurality of ring oscillation circuits do not change, and the delayed clock signal FB that matches the reference clock signal FIN is output.

  In the DLL circuit according to this embodiment, the selector 22 can selectively output one oscillation signal from oscillation signals output from a plurality of independent ring oscillation circuits having different numbers of stages. Therefore, even when high speed operation is required, the number of stages of the ring oscillation circuit (inverter chain) can be controlled by the selector 22 and the lock timing in the phase comparison circuit 11 can be adjusted. Also, the frequency range of the reference clock signal that can be locked is widened.

  Here, the delay time in the delay circuit 16 is controlled by the delay control signals PC and NC as in the case of the plurality of ring oscillation circuits in the voltage controlled oscillation circuit 15. Therefore, by controlling the number of stages of the ring oscillation circuit (inverter chain) and adjusting the lock timing in the phase comparison circuit 11, the delay time in the entire delay circuit 16 can also be controlled.

  Further, by providing load capacitance circuits 51 and 52 for a plurality of ring oscillation circuits (inverter chains) in the voltage controlled oscillation circuit 15 as shown in FIG. It becomes possible to finely adjust the delay time of the entire circuit 16.

  FIG. 5A is a diagram showing a circuit configuration in the case where the delay time in the inverter chain constituting the ring oscillation circuit is controlled by the load capacity.

  In FIG. 5A, each of the inverter circuits I51 to I59 is supplied with delay control signals PC and NC, and is configured in the same manner as the inverter circuit shown in FIG. The inverter circuits I51 to I59 are cascade connected.

  Reference numerals 51 and 52 denote load capacitance circuits. The load capacitance circuit 51 includes a plurality of logic gates (NAND circuits) NA0, NA1, NA2,. One input of NAND circuits NA0, NA1, NA2,... Is supplied with capacitance control signals Co0, Co1, Co2,..., And the other input is an odd-numbered inverter circuit in the inverter chain (inverter circuits I51, I53 in FIG. 5A). ) And the interconnection point of the input terminal of the inverter circuit in the next stage.

Here, the load capacitance circuit 51 includes 1 (= 2 ⁰ ) NAND circuits NA0 to which the capacitance control signal Co0 is supplied, and 2 (= 2 ¹ ) NAND circuits NA1 to which the capacitance control signal Co1 is supplied. There are 4 (= 2 ² ) NAND circuits NA2 to which the control signal Co2 is supplied. Therefore, when the delay time is changed by the load capacitance circuit 51, it can be changed linearly by binary control.

  In the load capacitance circuit 52, the other input of the plurality of NAND circuits NB0, NB1, NB2,... Is the output terminal of the even-numbered inverter circuit (inverter circuits I56, I58 in FIG. 5A) and the next stage. Since it is the same as the load capacity circuit 51 except that it is connected to the interconnection point at the input end of the inverter circuit of FIG.

  FIG. 5B is a diagram schematically illustrating a configuration of a NAND circuit included in the load capacitance circuits 51 and 52.

  In FIG. 5B, reference numerals 55 and 56 denote inverter circuits configured in the same manner as in FIG. 3B. A NAND circuit 57 includes two P-channel transistors T51 and T52 and two N-channel transistors T53 and T54.

  The sources of the transistors T51 and T52 are connected to the power supply VDD, and the drains are commonly connected to the drain of the transistor T53. The source of the transistor T53 is connected to the drain of the transistor T54, and the source of the transistor T54 is connected to the ground level (grounded). The gates of the transistors T51 and T53 are connected to an interconnection point between the output terminal of the inverter circuit 55 and the input terminal of the inverter circuit 56, and the capacitance control signal CO is supplied to the gates of the transistors T52 and T54.

  C1 and C2 are oxide film capacitances formed between the gate and the drain in the transistors T51 and T53, respectively. In the load capacitance circuit in the present embodiment, the load capacitance is controlled using the oxide film capacitances C1 and C2. As a result, it is possible to control a minute capacitance as compared with a conventional load capacitance control using a bulk capacitance (parasitic capacitance).

Next, the principle will be described with reference to FIGS. 6 (A) to (C) and FIGS. 7 (A) to (C).
6A and 6B and FIGS. 7A and 7B, the signal SIG is a signal supplied from an inverter circuit (ring oscillation circuit).

  FIGS. 6A and 6B are diagrams for explaining changes in load capacitance when the capacitance control signal CO is at the low level (L).

  When the capacitance control signal CO is L and the signal SIG is at a high level (H), the transistors T52 and T53 are turned on and the transistors T51 and T54 are turned off as shown in FIG. At this time, the level of the node N61 is H.

  On the other hand, when the capacitance control signal CO is L and the signal SIG is L, the transistors T51 and T52 are turned on and the transistors T53 and T54 are turned off as shown in FIG. 6B. At this time, the level of the node N61 is H.

  Here, Q = CV, and V = 1 (V) for further simplifying the description. When the signal SIG changes from H to L while the capacitance control signal CO is L, a load is applied to the inverter circuit due to a potential difference between both ends of the capacitors C1 and C2 (C = −Q). On the other hand, when the signal SIG changes from L to H, no potential difference occurs between both ends of the capacitors C1 and C2, so that no load is applied.

  Therefore, when the capacity control signal CO is L, as shown in FIG. 6C, the clock signal RCLK is delayed by the delay time D61 only when it changes from H to L, that is, at the time of falling. In FIG. 6C, MCLK is a clock signal when an ideal state is assumed (when there is no influence on the signal), and RCLK is a NAND circuit as a load capacitor circuit. This is a clock signal when provided.

  FIGS. 7A and 7B are diagrams for explaining a change in load capacitance when the capacitance control signal CO is H. FIG.

  When the capacitance control signal CO is H and the signal SIG is H, the transistors T53 and T54 are turned on and the transistors T51 and T52 are turned off as shown in FIG. At this time, the level of the node N61 is L.

  On the other hand, when the capacitance control signal CO is H and the signal SIG is L, the transistors T51 and T54 are turned on and the transistors T52 and T53 are turned off as shown in FIG. 7B. At this time, the level of the node N61 is H.

  6A to 6C, when the signal SIG changes from H to L while the capacity control signal CO is H, a potential difference is generated between both ends of the capacitors C1 and C2, thereby causing an inverter circuit. Is loaded (C = −Q). Also, when the signal SIG changes from L to H, a load is applied due to a potential difference between both ends of the capacitors C1 and C2 (C = + Q).

  Therefore, when the capacity control signal CO is H, the clock signal RCLK is delayed by the delay time D62 when changing from H to L (at the time of falling) as shown in FIG. When it changes to H (at the time of rising), it is delayed by the delay time D63.

  As can be seen from the above description, when the capacitance control signal CO is L, a delay is added only to one edge (at the time of falling), and when the capacitance control signal CO is H, both edges (at the time of falling). And a delay). In order to eliminate this inconvenience, in the present embodiment, two load capacitance circuits 51 and 52 are provided, and nodes in which the output of the inverter circuit is in a reverse phase relationship at the same time, that is, odd-numbered and even-numbered inverter circuits. Load capacitance circuits 51 and 52 are connected to each output. Thereby, an equivalent delay can be added to both edges.

  The load capacitance circuits 51 and 52 shown in FIG. 5A described above are provided in each of the plurality of ring oscillation circuits included in the voltage controlled oscillation circuit 15, and the phase comparison circuit 11 is controlled by controlling the load capacitance in the ring oscillation circuit by the capacitance control signal CO. Thus, the lock timing can be finely adjusted, and the delay time of the entire delay circuit 16 can be further finely adjusted.

  For example, with respect to delay time values DT1, DT2, DT3,... That can be controlled by controlling the number of stages of the ring oscillation circuit (inverter chain) in the selector 22, the intervals between the values DT1, DT2, DT3,. When the divided delay time value can be controlled by the capacity control of the load capacity circuits 51 and 52 based on the capacity control signal CO, the lock timing in the phase comparison circuit 11 can be linearly adjusted.

  For example, as shown in FIG. 8, when the delay time is set to DT1, DT2, and DT3, the delay time is controlled only by control of the number of stages in the selector 22, that is, control based on the selection signal SEL, and the delay times DT1, DT2 When the delay time between DT3 and DT3 is set, the delay time can be controlled by binary control of the capacity based on the capacity control signal CO in addition to the stage number control by the selector 22. In FIG. 8, the vertical axis represents delay time, and the horizontal axis represents control information (control value).

  In this embodiment, a plurality of independent ring oscillation circuits having different numbers of stages are provided in the voltage controlled oscillation circuit 15, and the output of any one of the ring oscillation circuits is set as a feedback clock signal FB by the selector 22 in accordance with the selection signal SEL. Selectively output. As a result, the output of the independent ring oscillation circuit is always output as a feedback clock signal, so that it is possible to output a feedback clock signal whose duty ratio is not lost even when the operation speed is high, and the input signal DLLI Can be arbitrarily adjusted until a signal is output as the output signal DLLO.

  In addition, by providing a plurality of independent ring oscillation circuits with different numbers of stages in the voltage controlled oscillation circuit 15, and controlling the number of stages of the ring oscillation circuit with the selection signal SEL, the frequency range of the clock signal output as the feedback clock signal And the frequency range of the reference clock signal that can be supported (lockable) increases. For example, it can be easily used as an interface for various DDR memories having different reference clock signal frequencies.

  In this embodiment, the number of stages of the ring oscillation circuit is controlled by selectively outputting the outputs of the plurality of ring oscillation circuits in the voltage controlled oscillation circuit 15 by the selector 22. A selector is provided between the mirror circuit 21 and the ring oscillation circuit, and the delay control signals PC and NC are supplied to only one of the plurality of ring oscillation circuits (the delay control signals PC and NC are activated). The ring oscillation circuit may be stopped (the delay control signals PC and NC are deactivated).

  In the present embodiment, the plurality of ring oscillation circuits in the voltage controlled oscillation circuit 15 are configured using inverter circuits. However, the present invention is not limited to this, and an inverted output logic that inverts and outputs an input signal. For example, a NAND circuit or a NOR circuit in which one input is fixed may be used.

  In this embodiment, the load capacitance circuits 51 and 52 are provided only in the plurality of ring oscillation circuits in the voltage controlled oscillation circuit 15, but a similar load capacitance circuit is provided in the inverter chain in the delay circuit 16. You may do it.

In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Regarding the above-described embodiment, the following additional notes are disclosed.

(Appendix 1) A semiconductor device for adjusting a delay time from when an input signal is input to when the input signal is output,
A phase comparison circuit that compares the phases of the reference clock signal and the feedback clock signal;
An oscillation circuit that outputs a delay control signal for controlling the delay time based on the feedback clock signal and a comparison result in the phase comparison circuit;
The oscillation circuit is capable of controlling an oscillation frequency based on a comparison result in the phase comparison circuit, and a plurality of independent internal oscillation circuits having different oscillation frequencies,
A semiconductor device comprising: a selection circuit for selectively outputting one of the outputs of the plurality of internal oscillation circuits as the feedback clock signal.
(Supplementary note 2) The semiconductor device according to supplementary note 1, wherein the plurality of internal oscillation circuits are a plurality of ring oscillation circuits in which odd number of different inverted output logic gates are cascade-connected.
(Supplementary note 3) The semiconductor device according to supplementary note 2, wherein the logic gate of the inverted output is an inverter circuit.
(Additional remark 4) The semiconductor device of Additional remark 3 characterized by controlling the power supply voltage supplied to the said inverter circuit based on the comparison result in the said phase comparison circuit.
(Additional remark 5) The said oscillation circuit further has a signal generation circuit which produces | generates the said delay control signal based on the comparison result in the said phase comparison circuit,
The semiconductor device according to claim 4, wherein a power supply voltage supplied to the inverter circuit is controlled by the delay control signal generated by the signal generation circuit.
(Supplementary Note 6) The selection circuit receives all the output of the internal oscillation circuit and a selection signal related to the selection of the output, and selectively uses the output of the internal oscillation circuit as the feedback clock signal according to the selection signal. The semiconductor device according to appendix 1, wherein
(Appendix 7) The internal oscillation circuit includes a load capacitance circuit that is connected to an output terminal of the logic gate of the inverted output and varies a load capacitance value according to a control signal.
The semiconductor device according to claim 2, wherein the load capacitance in the load capacitance circuit is an oxide film capacitance of a MOS transistor.
(Supplementary Note 8) The internal oscillation circuit includes a first load capacitance circuit connected to an output terminal of an odd-numbered inverted output logic gate and an even-numbered inverted logic gate in the cascade-connected inverted output logic gate The semiconductor device according to appendix 7, further comprising a second load capacitance circuit connected to an output terminal of an output logic gate.
(Supplementary note 9) The load capacitance circuit includes a plurality of NAND circuits in which one input is connected to the output terminal of the logic gate of the inverted output and the control signal is supplied to the other input. 8. The semiconductor device according to 7.
(Supplementary Note 10) The control signal is n bits (n is an arbitrary natural number),
The load capacitance circuit is composed of (2 ⁿ -1) NAND circuits, and 2 ^m-1 (m is a natural number equal to or less than n) NAND circuits are supplied with the control signal of the lower m-th bit to the other input. 10. The semiconductor device according to appendix 9, wherein
(Supplementary note 11) The semiconductor device according to Supplementary note 1, further comprising a delay circuit that delays and outputs the input signal by the delay time according to the delay control signal.
(Supplementary note 12) The semiconductor device according to Supplementary note 11, wherein the delay circuit comprises an even number of inverted output logic gates connected in cascade.
(Supplementary Note 13) A plurality of inverted output logic gates connected in cascade,
A load capacitance circuit that is connected to an output terminal of the logic gate of the inverted output and varies a load capacitance value according to a control signal;
A load capacitance in the load capacitance circuit is an oxide film capacitance of a MOS transistor.
(Supplementary Note 14) The load capacitance circuit includes a plurality of NAND circuits in which one input is connected to an output terminal of the logic gate of the inverted output and the control signal is supplied to the other input. 13. The semiconductor device according to 13.
(Supplementary Note 15) The first load capacitance circuit connected to the output terminal of the odd-numbered inverted output logic gate in the cascade-connected inverted output logic gate and the output of the even-numbered inverted output logic gate 14. The semiconductor device according to appendix 13, further comprising a second load capacitance circuit connected to an end.
(Supplementary Note 16) A plurality of independent internal oscillation circuits having different oscillation frequencies, the oscillation frequency being controllable according to the voltage of the voltage signal from the outside,
A voltage control comprising: a selection circuit which receives outputs of the plurality of internal oscillation circuits and selectively outputs any one of the outputs as a clock signal in accordance with a selection signal related to selection of the output Oscillator circuit.
(Supplementary note 17) The voltage controlled oscillation circuit according to supplementary note 16, wherein the plurality of internal oscillation circuits are a plurality of ring oscillation circuits in which odd number of different inverted output logic gates are cascade-connected.
(Supplementary note 18) The voltage controlled oscillation circuit according to supplementary note 17, wherein the logic gate of the inverted output is an inverter circuit in which a power supply voltage supplied based on a voltage of the voltage signal is controlled.

It is a block diagram which shows one structural example of the DLL circuit to which the semiconductor device by embodiment of this invention is applied. It is a block diagram which shows the structural example of the voltage controlled oscillation circuit in this embodiment. It is a figure which shows the circuit structure of a current mirror circuit. It is a figure which shows the circuit structure of an inverter circuit. It is a figure which shows the structural example of a delay circuit. It is a figure which shows the example of a circuit structure at the time of controlling delay time by load capacity. It is a figure which shows the structure of the NAND circuit as a load capacity. It is a figure for demonstrating the change of the load capacity when a capacity | capacitance control signal is L. FIG. It is a figure for demonstrating the change of the load capacity when a capacity | capacitance control signal is H. FIG. It is a figure which shows an example of delay time control in this embodiment. It is a figure for demonstrating the problem in the conventional voltage controlled oscillation circuit. It is a figure which shows the circuit which controls delay time using the conventional capacity | capacitance. It is a figure which shows the circuit which controls delay time using the conventional capacity | capacitance.

Claims (3)

A plurality of inverting output logic gates connected in cascade;
A load capacitance circuit connected to the output terminal of the logic gate of the inverted output and varying a load capacitance value according to a control signal;
A load capacitance in the load capacitance circuit is an oxide film capacitance of a MOS transistor.   2. The load capacitance circuit includes a plurality of NAND circuits each having one input connected to an output terminal of the logic gate of the inverted output and the control signal supplied to the other input. Semiconductor device. A first load capacitance circuit connected to an output terminal of an odd-numbered inverted output logic gate at the cascade-connected inverted output logic gate;
2. The semiconductor device according to claim 1, further comprising: a second load capacitor circuit connected to an output terminal of an even-numbered inverted output logic gate.

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