JPH0582741A - Mos capacitor - Google Patents

Abstract

PURPOSE:To eliminate the voltage dependency of the capacitance of a MOS capacitor and improve the accuracy and stability of a circuit to which the MOS capacitance is applied. CONSTITUTION:The source terminal S1 and the drain terminal D1 of a first MOS transistor T1 are connected in common. The source terminal S2 and the drain terminal D2 of a second MOS transistor T2 are connected in common. The identical conductivity type, i.e., p-type or n-type, is given to both the first and second MOS transistors T1 and T2. Further, the gate terminal and the seurce/drain terminal of the one MOS transistor are conneeted to the source/ drain terminal and the gate terminal of the other respectively.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to a MOS capacitor. The MOS capacitor is a field effect transistor (F
M, which is a type of ET (field effect transistor) element
It is a capacitive device using an OS (metal oxide semiconductor) transistor, and is often used in, for example, a switched capacitor filter or an A / D conversion circuit.

[0002]

2. Description of the Related Art FIG. 5 shows a conventional MOS capacitor. The source terminal S and the drain terminal D of the MOS transistors in common, the voltage V _GS applied across the source-drain terminal SD and the gate terminal G, utilizing capacitance C _T generated between these terminals.

[0003]

However, in such a conventional MOS capacitor, there is a correlation between V _GS and C _T , and C _T also changes as V _GS changes. was there. Here, the size of the gate-source (or drain) capacitance C _T of the MOS transistor is given by a value (series sum) obtained by adding the gate oxide film capacitance C _O and the depletion layer capacitance C _D. Although C _O is proportional to the film thickness but does not depend on voltage and is fixed for each type, C _D has a property that depends on the channel formation depth (depth into the substrate). Therefore, since the channel depth corresponds to the gate-source (or drain) voltage, C _T also changes as V _GS changes.

This has the disadvantage of impairing the accuracy and stability of the circuit to which the MOS capacitor is one of the constituent parts. Therefore, an object of the present invention is to provide a MOS capacitor that can eliminate the voltage dependence of capacitance and improve the accuracy and stability of the application circuit.

[0005]

In order to achieve the above object, the present invention has a first MOS transistor T ₁ having a common source terminal S ₁ and drain terminal D ₁ as shown in the principle diagram of FIG. Similarly, source terminal S ₂ and drain terminal D ₂
And a second MOS transistor T ₂ in common with the first MOS transistor T ₁ and the second MOS transistor T 2.
The OS transistor T ₂ is unified into a p-channel type or an n-channel type, and the respective gate terminals G ₁ and G ₂ and the source / drain terminals S ₁ , G ₁ , S ₂ and D ₂ are connected in a crossed manner. Is characterized by.

[0006]

In the present invention, two MOS transistors T ₁ ,
The formation depth of the channel of T ₂ changes according to the _two voltages V ₁ and V ₂ . Here, T ₁ gate - in source voltage (V _GS2) of the "V ₂ -V _1" - source voltage (V _{G S1)} is given by "V ₁ -V ₂ ', also the gate of T ₂ Given. Considering the case where V ₁ changes from a negative voltage to a positive voltage with V ₂ as a reference, the capacitance curves of T ₁ and T _{2 in} this case are as shown in FIGS. 2A and 2B, respectively ( However,
(When T ₁ and T ₂ are depletion type).

FIG. 2A is a capacitance curve of T ₁ . V _GS1
Is in the negative voltage region (V ₁ >> 0), the capacitance C _{T1 of} T ₁
Varies with the gate oxide film capacitance C _O , but V
_{When GS1} reaches a predetermined negative potential point (P _OFF ) close to zero potential, C _T1 turns to an increasing trend with this potential point P _OFF as a boundary. This tendency is due to an increase in the depletion layer capacitance C _D , and T ₁
This is because the formation depth of the channel is increased. In addition,
P _OFF is a potential corresponding to the off bias of the depletion type transistor.

FIG. 2B is a change curve of T ₂ . V _GS2
= V ₂ -V _1, i.e. V _GS2 because is given by the opposite polarity V _GS1, V _GS2 when V _GS1 is in the negative voltage region is in the positive voltage region. When V _GS1 changes in the positive potential direction (in-phase with the change in V ₁ ), V _GS2 changes in the negative voltage direction opposite to the change in V ₁ . The capacitance C _{T2 of} T ₂ first gradually decreases with a change in V _GS2 , and finally changes with the same value as the gate oxide film capacitance C _O.

Therefore, the two MOS transistors T
The respective capacitance curves of ₁ and T ₂ have opposite shapes so as to complement each other, and the two can be additively combined to form a substantially flat capacitance change curve (see FIG. 2C). As a result, it is possible to realize a MOS capacitor having a substantially constant value without voltage dependence.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. 3 and 4 are diagrams showing an embodiment of a MOS capacitor according to the present invention, which is an example of application to a 1-bit A / D conversion circuit. In FIG. 3, 10 is a MOS capacitor. MOS capacitor 10 includes a first MOS transistor T ₁₁ in which the source terminal S ₁₁ and the drain terminal D ₁₁ in common, also a second MOS transistor T ₁₂ in which the source terminal S ₁₂ and the drain terminal D ₁₂ to a common Prepared, first
For the MOS transistor T ₁₁ and the second MOS transistor T ₁₂ , for example, n-channel depletion mode MOS transistors are used. It may be a p-channel type or an enhancement mode MOS transistor. In short, it is important to make the electrical characteristics of the two MOS transistors T ₁₁ and T ₁₂ uniform.
This is the second point.

The second point is to connect T ₁₁ and T ₁₂ in a cross. That is to connect the gate terminal G ₁₁ of the T ₁₁ to a source-drain terminal SD ₁₂ of T _12, and connects the gate terminal G ₁₂ of the T ₁₂ to a source-drain terminal SD ₁₁ of T _11. On the other hand, 11 is the first
, 12 is a second switch, 13 is a third switch, and 14 is an inverter gate, and these elements together with the MOS capacitor 10 constitute a main part of the A / D conversion circuit. Note that V _i1 is the first input voltage, V _i2 is the second input voltage, and V _O is the output voltage.

The three switches 11 to 13 are turned on / off in the order shown in the following table according to a signal from a control circuit (not shown).
Repeat off. When only the third switch 13 is turned on in step 2,
The input and output of the inverter gate 14 are connected to each other, and the input and output potentials are fixed at a potential equivalent to the threshold value of the inverter gate 14 (for example, 2.5 V). Here, the input potential of the inverter gate 14, in other words, the MOS capacitor 10
When the output terminal potential of the above is represented by Vb, this Vb is set to 2.5V in step 2.

Next, when the first switch 11 is turned on in step 3, the first input voltage V _i1 becomes the input end potential Va of the MOS capacitor 10 and the potential difference ΔV (ΔV = Va− across the MOS capacitor 10). Vb) is given, and the charge corresponding to this ΔV is accumulated in the capacitance of the MOS capacitor 10. In step 6, only the second switch 12 is turned on, and Va has a reference potential (for example, a potential corresponding to a high level or a low level of TTL that represents the MSB or LSB of the 1-bit A / D converter). Given. For example, when 0 V (low level) is applied, a potential of 0 V-ΔV appears in Vb, and if this potential exceeds the threshold value (2.5 V) of the inverter, V _O becomes low level. Alternatively, if the threshold is not exceeded, V _O
Becomes a high level.

That is, the A / D conversion circuit of this embodiment is
The difference voltage ΔV between the first input voltage V _i1 accumulated in the capacitance of the MOS capacitor 10 and the threshold value is calculated by the inverter gate 1
The level is determined by 4 and converted into a 1-bit digital signal. The capacitance of the MOS capacitor 10 is
Although it is a parallel combined capacitance of the capacitance C _{T11 of} the first MOS transistor T ₁₁ and the capacitance C _{T12 of} the second MOS transistor T ₁₂ , the combination of T _{1 1} and T ₁₂ causes
The capacitances C _{T 11} and C _T12 change in a complementary manner as the ΔV increases and decreases.

FIG. 4 (a) is a capacitance change curve of C _T11 , FIG.
(B) is a capacitance change curve of C _T12 , in which C _T11 and C _T12 change with opposite characteristics as ΔV changes. When viewed by C _T11 alone, a capacitance variation of ΔC _T11 is observed between the high level V _H and the low level V _L. Similarly, when viewing C _T12 alone, ΔC is between the high level V _H and the low level V _L.
The capacity fluctuation of _T12 is recognized, and the two fluctuations complement each other. Such capacity fluctuation is mainly due to T ₁₁
This is a phenomenon caused because the depletion layer capacitance C _D of each transistor fluctuates with the change of the gate-source voltage of T ₁₂ and T ₁₂ , but in the case of only one fluctuation (corresponding to the above-mentioned conventional example). This is a problem because it makes the threshold value judgment in the inverter gate 14 erroneous and makes the A / D conversion operation inaccurate.

In this embodiment, the MOS capacitor 10 is supplemented by compensating one fluctuation with the other fluctuation.
It has realized the flattening of the capacity of. That is, FIG. 4 (a)
By synthesizing the capacitance change curve (C _T11 ) of FIG. 4 and the capacitance change curve (C _T12 ) of FIG. 4B, flattening between the low level V _L and the high level V _H can be achieved, and The stability of the threshold value judgment in the gate 14 can be improved, and the accuracy of the A / D conversion operation can be improved.

As described above, in this embodiment, the capacitance can be kept constant even when the voltage applied between the two terminals changes, and an excellent MOS capacitor having no voltage dependence can be provided. Therefore, when it is applied to, for example, an A / D converter, it is possible to obtain a unique effect that its accuracy and operation stability can be improved. Although the depletion mode n-channel type MOS transistor is used in the embodiment, it is not limited to this, and it is needless to say that it may be an enhancement mode or a p-channel type. is there.

[0018]

According to the present invention, the voltage dependence of capacitance can be eliminated, and the precision and stability of the circuit to which it is applied can be improved.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of the present invention.

FIG. 2 is a capacitance change curve diagram of FIG.

FIG. 3 is a configuration diagram of an embodiment.

FIG. 4 is a capacitance change curve diagram of an example.

FIG. 5 is a configuration diagram of a conventional example.

[Explanation of symbols]

S _1, S _2: the source terminal D _1, D _2: the drain terminal G _1, G _2: the gate terminal T _1: first MOS transistor T _2: second MOS transistor T _11: a first MOS transistor T ₁₂ : Second MOS transistor

Claims (1)

[Claims] 1. A source terminal (S ₁ ) and a drain terminal (D ₁ )
A first MOS transistor (T ₁ ) having a common source and a second MOS transistor (T ₂ ) having a common source terminal (S ₂ ) and drain terminal (D ₂ ) are also provided. MOS transistor (T ₁ ) and the second M
The OS transistor (T ₂ ) is unified into a p-channel type or an n-channel type, and each gate terminal (G ₁ , G ₂ ) and source / drain terminal (S ₁ , G ₁ , S ₂ , D ₂ ) are connected. A MOS capacitor characterized by being connected in a cross.