JPH09199999A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital PLL circuit operated at a high speed even when lots of load capacitance circuits are provided to a delay circuit by making the area shared by the load capacitance circuits small. SOLUTION: A capacitor C of a load capacitor circuit LC connecting to an inverter of a variable delay circuit of the digital PLL circuit is made cup of a MOS capacitor provided with a switch function. Furthermore, the load capacitor circuit LC is connected in cascade with an output terminal of the inverter to suppress a capacitive component connecting to the inverter low at all times, then the fundamental oscillating frequency of the PLL circuit is designed high. Thus, the capacitor of the load capacitor circuit requires a pattern area nearly a half or below that of a conventional circuit and the required area of the variable delay circuit is reduced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital PLL (phase locked loop) circuit, and more particularly to a digital P (Phase Locked Loop) circuit for finely adjusting a signal delay time for accurate phase locking.
The present invention relates to improvement of the LL circuit.

[0002]

2. Description of the Related Art An example of a conventional digital PLL circuit is shown in FIG.
This will be described with reference to FIG. The digital PLL circuit is composed of a ring oscillator 1, a phase comparator 2, and a delay control circuit 3. The ring oscillator 1 includes a variable delay circuit 100 and an inverter 200 that are connected in a ring,
The oscillation frequency is determined by the open loop transfer function.

The output signal of the ring oscillator 1 is supplied to the phase comparator 2 and compared in phase with a reference clock signal supplied from the outside. The phase comparator 2 supplies a difference signal corresponding to the difference between the two signals to the delay control circuit 3. Delay control circuit 3
Sets the signal delay amount of the variable delay circuit so as to eliminate the phase difference, and controls the phase of the output signal of the ring oscillator 1. The phase-adjusted output signal is supplied again to the phase comparator 2, and the phase locked loop operates until the output signal matches the phase of the reference clock signal.

The variable delay circuit 100 is usually composed of a plurality of unit delay circuits connected in series, and the delay time is set stepwise by changing the number of stages of the unit delay circuits according to the output of the delay control circuit 3. To do. However, only by changing the number of stages of the unit delay circuit, the step of the delay time is intermittent and rough. In order to achieve more accurate phase synchronization, the rising and falling characteristics of the signal are adjusted by changing the capacitor at the output end of the unit delay circuit, and the time axis of the transmission signal is finely adjusted to adjust the output signal. A digital PLL circuit with less jitter (fluctuation of signal time axis) is obtained.

FIG. 8 shows such an example, and shows a delay circuit D1 which is one of a plurality of unit delay circuits in the variable delay circuit 100. The delay circuit D1 is composed of two (or even) inverters. A transmission gate TG (analog switch) forming a variable load capacitance circuit and a capacitor are connected in series between the output terminal A of the inverter and the ground. The transmission gate TG is opened / closed by the enable signal EN supplied from the delay control circuit 3 and its inverted signal / EN passed through the inverter.

When the enable signal EN is supplied to the transmission gate TG, as shown in FIG.
The capacitor C is connected to the output terminal of the inverter via the transmission gate TG. Further, when the enable signal EN is not supplied, the transmission gate TG is in an open state and the capacitor C is not connected to the output terminal of the inverter as shown in FIG.

In order to make the value of the capacitor connected to the output terminal of the inverter constituting the delay circuit more variable,
As shown in FIG. 10, a plurality of load capacitance circuits LC11 to L each composed of a transmission gate TG and a capacitor C.
Cnn is connected to the output terminal A of the inverter as a variable load capacitance circuit. The delay control circuit 3 controls the enable signals EN11 to ENnn provided to the transmission gates TG of the individual load capacitance circuits to connect the required number of capacitors to the output terminal A of the inverter, and the ring oscillator 1 to the phase of the reference clock signal. Match the phase of the output signal of.

[0008]

As described above, in the conventional digital PLL circuit, in order to finely adjust the time axis of the output signal of the ring oscillator, the transmission gate TG and the capacitor C connected to the output end of the inverter are connected.
Are provided.

However, in order to construct a digital PLL circuit with less jitter, it is usually necessary to add 100 or more load capacitance circuits each including a transmission gate TG and a capacitor C. Therefore, an area on the semiconductor chip is required, which leads to an increase in size of the chip and an increase in cost.

Further, since the diffusion capacitance of the transmission gate TG and the wiring capacitance connecting the output end A of the inverter and the plurality of transmission gates TG are fixedly applied to the output end of the inverter, the fundamental oscillation frequency of the ring oscillator is high. There is also a problem that it becomes difficult to set the frequency.

Therefore, a first object of the present invention is to provide a digital PLL circuit in which the area occupied by the load capacitance circuit on the semiconductor substrate is reduced.

A second object of the present invention is to provide a digital PLL circuit which is provided with a plurality of load capacitance circuits and which can ensure precise phase adjustment and guarantee high-speed operation.

[0013]

To achieve the above object, a digital PLL circuit of the present invention includes an oscillator including a variable delay circuit that delays the phase of an output signal by passing the output signal through a plurality of unit delay circuits. A variable load capacitance circuit connected to the output terminal of the unit delay circuit, a phase comparator that outputs a phase difference between the output signal and a reference clock signal, and the unit through which the output signal passes according to the phase difference. A delay control circuit for controlling the number of delay circuits and the capacitance of the variable load capacitance circuit, wherein the variable load capacitance circuit is composed of a MOS transistor capacitor whose conduction is controlled by the delay control circuit. Characterize.

Further, the digital PLL circuit of the present invention is
An oscillator including a variable delay circuit that delays the phase of the output signal by passing the output signal through a plurality of unit delay circuits, and a variable load capacitance circuit connected to the output terminal of the unit delay circuit,
A phase comparator that outputs a phase difference between the output signal and the reference clock signal, and a delay control that controls the number of the unit delay circuits through which the output signal passes and the connection of the variable load capacitance circuit according to the phase difference. A variable load capacitance circuit, wherein the variable load capacitance circuit comprises a plurality of switch elements connected in series with each other, and a plurality of capacitors connected between each of the connection points of the switch elements and a predetermined power source. Becomes
It is characterized in that each switch element is controlled to be conductive by the delay control circuit in the order of series connection.

[0015]

According to the above structure, the variable load capacitance circuit for finely adjusting the delay time of the output signal in the digital PLL circuit is formed by the MOS transistor capacitor in which the transmission gate and the MOS capacitor are integrated. This reduces the size of the load capacitance circuit.

Further, by reducing (to one) the load capacitance circuit directly connected to the output terminal of the unit delay circuit, the diffusion capacity and the diffusion capacitance of the transmission gate (switch element) directly connected to the output terminal of the unit delay circuit are reduced. The wiring capacity etc. is reduced.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment of the present invention. The parts corresponding to those of the circuit shown in FIG. 10 are designated by the same reference numerals, and the description of those parts will be omitted.

In the figure, the load capacitance circuits LC11 to LC1n forming the variable load capacitance circuit are load capacitance circuits LC11.
, A P-MOS transistor, N
-It is composed of a MOS transistor and an inverter. The sources and drains of the P-MOS transistor and the N-MOS transistor are connected to the node A at the output end of the inverter. Load capacitance circuit LC11
An enable signal is supplied from the delay control circuit 3. An enable signal EN11 is applied to the gate of the N-MOS transistor, and an enable signal / EN11 inverted via an inverter is applied to the gate of the P-MOS transistor. The same applies to the load capacitance circuits LC21 to LCnn. The number of load circuits forming the variable load capacitance circuit may be one.

As shown in FIG. 2 (a), when the "H" level enable signal EN11 is supplied to the load capacitance circuit,
Both the P-MOS transistor and the N-MOS transistor form a channel under the gate and are turned on. Since the gate oxide film is very thin, the channel and the gate electrode function as a capacitor (MOS transistor capacitor). Therefore, the N-MOS transistor is equivalent to the capacitor Cn connected between the gate bias power supply (for example, 5 volts) and the node A. P-MOS
The transistor is equivalent to the capacitor Cp connected between the gate bias power supply (eg, ground potential) and the node A.

As shown in FIG. 2B, when the load capacitance circuit is supplied with the enable signal / EN11 of "L" level, both the N-MOS transistor and the P-MOS transistor do not form a channel. , Turns off. Both transistors do not function as capacitors.

The operation of the load capacitance circuit shown in FIG. 1 is shown in FIG.
Although it is the same as the load capacitance circuit shown in (1), since the transmission gate and the capacitor are integrally configured, the number of elements is half.

The load capacitance circuit shown in FIG.
Although the C-MOS transistor configuration is configured by -MOS and N-MOS transistors, only one of the transistors may be used. Further, a configuration may be used in which a plurality of transistors of one polarity are used as capacitors.

An embodiment of the second invention will be described with reference to FIG. In the figure, the portions corresponding to those in FIG. 10 are designated by the same reference numerals, and the description of those portions will be omitted.

In this embodiment, only the first load capacitance circuit LC11 is connected to the output node A of the inverter.
The second load capacitance circuit LC12 is the load capacitance circuit LC11.
It is connected to the connection point between the transmission gate TG and the capacitor C inside. The third load capacitance circuit LC13 is
Transmission gate TG in load capacitance circuit LC12
And capacitor C are connected to each other. Similarly, the fourth to nth load capacitance circuits are connected in cascade.

Next, the operation will be described. For example, in the initial state, the enable signal EN11 to
When EN1n is supplied from the delay control circuit 3 by the "L" level signal, the transmission gates of the load capacitance circuits are turned off. At this time, the capacitance loaded on the output end of the inverter is the gate capacitance of the next-stage inverter, the wiring capacitance of the wiring connected to the first load capacitance circuit, the first capacitance
Only the diffusion capacitance of the transmission gate of the second load capacitance circuit.

When the output signal of the ring oscillator is earlier than the phase of the reference clock, the delay control circuit 3 selects the number of inverter stages in the variable delay circuit 100 according to the phase difference, and further it is necessary to perform fine adjustment. , Enable signal EN
Set 11 to "H" level. As a result, the capacitor C of the first load capacitance circuit LC11 is provided at the output terminal of the inverter.
Then, the wiring capacitance of the wiring connecting the first and second load capacitance circuits and the diffusion capacitance of the second load capacitance circuit transmission gate are added, and the signal transmitted through the inverter is delayed.

If the phase of the output signal of the ring oscillator 1 is earlier than that of the reference clock signal, the delay control circuit 3
Enable signal E in addition to enable signal EN11.
N12 is set to "H" level. As a result, the output capacity of the inverter is further increased, and the output signal of the ring oscillator 1 is further delayed. Such enable signals EN11 to E
The operation of sequentially setting N1n to the "H" level in the order of cascade connection is performed until the phase of the reference clock signal and the phase of the output signal of the ring oscillator are synchronized.

Next, the case where the reference clock signal is earlier than the phase of the digital PLL circuit will be described. When the output signal of the ring oscillator is earlier than the phase of the reference clock, the delay control circuit 3 selects the number of inverter stages in the variable delay circuit 100 according to the phase difference, and if the fine adjustment is necessary, "H "Level enable signal EN
Set to "L" level in order from 1n to EN11. For example, when the enable signals EN11 to EN1n are all at the “H” level, the delay control circuit 3 sets the enable signal EN1n to the “L” level signal to accelerate the phase of the output signal of the ring oscillator 1, and the load capacitance circuit LC1n. Cut off the capacitor connection. When it is still necessary to advance the phase of the output signal of the ring oscillator 1, the enable signal EN1n-1 is set to the "L" level signal and the load capacitance circuit L
The connection of the C1n-1 capacitor is cut off. The operation of disconnecting the capacitor C and the related wiring capacitance is repeated until the phase of the output signal of the ring oscillator matches the phase of the reference clock signal.

In this way, the load capacitance connected to the node A at the output end of the inverter is adjusted, and a digital PLL circuit with less jitter can be obtained. In the conventional configuration, the diffusion capacitance of n transmission gates and the wiring capacitance of n wiring lines (n
In the configuration of this embodiment, the minimum capacitance directly connected to the output end of the inverter of the variable delay circuit is 1 The diffusion capacity of the two transmission gates,
There is only one wiring for connecting the load capacitance circuit and one load capacitance circuit. From this state, each time the plurality of enable signals sequentially become "H" level, the diffusion capacitance, the wiring capacitance, and the capacitance of one transmission gate are added. Therefore, precise phase synchronization and P
Both high speed operation of the LL circuit can be ensured.

FIG. 4 shows another embodiment of the second invention. In this embodiment, a plurality of load capacitance circuits connected in series as described above are connected in parallel to the output terminal of the inverter. With such a configuration, a larger capacity can be obtained.

FIG. 5 shows an example in which the first invention in which a transmission gate and a capacitor are integrally formed is applied to a second invention in which load capacitance circuits are connected in cascade. Enable signals En, / En, En1, / En1, En2, / En2, ..., Which are sequentially supplied to the load capacitance circuits LC11 to LC1n,
A MOS capacitor is added one by one each time Enn, / Enn is activated one by one.

FIG. 6 shows an LS of the C-MOS capacitors having the switching function connected in the cascade shown in FIG.
The example of I pattern is shown. In the figure, in the P-well 61 formed on the semiconductor substrate, the N ⁺ diffusion layer 6 serving as the drain, channel, and source of the N-MOS transistor is formed.
2 are formed. In this region, a plurality of gates 6311 to 631n of the N-MOS transistor made of polysilicon are formed via an insulating layer (not shown). Enable signals EN11 to EN1n are supplied to the respective gates. Also,
A P-MOS is formed in the P-well 65 formed on the semiconductor substrate.
P ⁺ that becomes the drain, channel and source of the transistor
The diffusion layer 66 is formed. In this region, a plurality of gates 6711 to 671n of the P-MOS transistor made of polysilicon are formed through an insulating layer (not shown). Each gate has an inverted enable signal / EN11 to / ENnn
Is supplied. The N ⁺ diffusion layer and the P ⁺ diffusion layer are connected to the aluminum wiring 81 of the output terminal node A of the inverter (not shown) through the contact holes 71 and 72.

A load capacitance circuit composed of a series of CMOS capacitor transistors formed in such an LSI pattern is more than a conventional load capacitance circuit formed of a plurality of transmission gates and capacitors.
It is possible to reduce the pattern area to about 1/5.

Further, the master slice type LSI system such as a gate array can be easily realized. Therefore, even if a large number of capacitors are mounted, the consumption pattern area is small, so the chip size is small, and a relatively inexpensive digital PLL circuit with little jitter can be obtained.

[0035]

As described above, in the digital PLL circuit of the present invention, the capacitor of the load capacitance circuit connected to the inverter of the variable delay circuit is composed of the MOS capacitor having the switching function, and therefore the capacitor is not the conventional one. The pattern area is approximately half or less, and the consumption area of the variable delay circuit can be reduced. Moreover, since the load capacitance circuits are connected in series to the output end of the inverter, P
It is possible to design the fundamental oscillation frequency of the LL circuit high.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a load capacitance circuit connected to an inverter of a variable delay circuit in a digital PLL circuit of the present invention.

FIG. 2 is an explanatory diagram illustrating an operation of the load capacitance circuit shown in FIG.

FIG. 3 is a block diagram showing a connection example of a load capacitance circuit connected to the inverter of the variable delay circuit in the digital PLL circuit of the present invention.

FIG. 4 is a block diagram showing an example in which a plurality of load capacitance circuits connected in series are connected in parallel to an output terminal of an inverter.

FIG. 5 is a block diagram showing an example in which load capacitance circuits connected in series are constituted by MOS transistor capacitors.

FIG. 6 is an LSI circuit pattern diagram showing an example in which the load capacitance circuits connected in cascade shown in FIG. 5 are formed by CMOS transistor capacitors.

FIG. 7 is a block diagram showing an example of a conventional digital PLL circuit.

FIG. 8 is a block diagram showing an example of a conventional load capacitance circuit.

9 (a) and 9 (b) are explanatory views for explaining conduction and non-conduction of the transmission gate shown in FIG.

FIG. 10 is a block diagram showing an example in which a plurality of load capacitance circuits are connected to an inverter of a variable delay circuit.

[Explanation of symbols]

 1 ring oscillator circuit 2 phase comparator 3 delay control circuit TG transmission gate C capacitor LC load capacitance circuit EN enable signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H03L 7/099 H03L 7/08 F

Claims (7)

[Claims] 1. An oscillator including a variable delay circuit for delaying the phase of an output signal by passing an output signal through a plurality of unit delay circuits, a variable load capacitance circuit connected to an output terminal of the unit delay circuit, A phase comparator that outputs a phase difference between an output signal and a reference clock signal, and a delay control circuit that controls the number of the unit delay circuits through which the output signal passes and the capacitance of the variable load capacitance circuit according to the phase difference. The digital PLL circuit is characterized in that the variable load capacitance circuit is configured by a MOS transistor capacitor whose conduction is controlled by the delay control circuit. 2. The variable load capacitance circuit is configured by a plurality of MOS transistor capacitors, each of which is connected in series with each other and whose conduction is controlled by the delay control circuit in the order of series connection. The digital PLL circuit according to claim 1. 3. The variable load capacitance circuit has a plurality of series circuits, each of which is connected in series with each other and which is composed of a plurality of MOS transistor capacitors whose conduction is controlled according to the order of series connection by the delay control circuit. The digital PL according to claim 1 or 2, characterized in that
L circuit. 4. The digital PLL circuit according to claim 1, wherein the variable load capacitance circuit includes a C-MOS transistor capacitor. 5. A plurality of MOS transistor capacitors connected in series, which constitute the variable load capacitance circuit, are formed by using a common impurity diffusion layer on a semiconductor substrate as a source or a drain. The digital PLL circuit according to claim 2. 6. An oscillator including a variable delay circuit that delays a phase of an output signal by passing an output signal through a plurality of unit delay circuits, a variable load capacitance circuit connected to an output terminal of the unit delay circuit, A phase comparator that outputs a phase difference between an output signal and a reference clock signal, and a delay control circuit that controls the number of the unit delay circuits through which the output signal passes and the connection of the variable load capacitance circuit according to the phase difference. The variable load capacitance circuit includes a plurality of switch elements connected in series with each other, and a plurality of capacitors respectively connected between respective connection points of the switch elements and a predetermined power source. A digital PLL circuit, wherein each switch element is conduction controlled by the delay control circuit according to the order of series connection. 7. The switch element and the capacitor are
7. The digital PLL circuit according to claim 6, comprising a MOS transistor capacitor.