JP3480309B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a built-in memory and a step-down circuit for stepping down an externally supplied power supply potential. 2. Description of the Related Art Generally, in a semiconductor memory device having a DRAM (Dynamic Random Access Memory) as a memory cell, a power supply potential supplied from the outside is stepped down by an internal step-down circuit and used. are doing. This step-down power supply system is an indispensable technique from the viewpoints of securing the reliability of the memory, reducing the power consumption, and improving the performance, as described below. In general, in MOS type semiconductor devices, transistors are being miniaturized for higher integration and operating speed. However, with the miniaturization, the withstand voltage of a gate oxide film is reduced. It is necessary to lower the power supply potential in the peripheral portion to reduce the electric field density in the gate insulating film and to ensure reliability. Other advantages of using the step-down circuit method are that the power consumption of the entire chip is reduced, and the instantaneous fluctuations of external power supply and the effects of noise are alleviated in the step-down power supply circuit, thereby stabilizing the memory operation. Can be expected. Conventionally, a circuit shown in FIG. 4 has been used as a configuration of a step-down power supply circuit used for such an application. This circuit comprises a step-down circuit 1 for an active state and a step-down circuit 2 for a standby state, and a step-down circuit 3 for generating a step-down potential of one half of the potential generated by the step-down circuit 1 and the step-down circuit 2. Is done. The potential supplied to each step-down circuit as REFVINT is a potential generated based on the external power supply potential VDD in a reference potential generation circuit (not shown in FIG. 4).
And 2 use this REFVINT as input and
A step-down potential VINT of the same potential as VINT is generated. In FIG. 4, reference numeral 10 denotes an external power supply potential VDD.
Is a power supply line for supplying the voltage step-down circuit, and 11 is a power supply line for similarly supplying the ground potential VSS. Further, the step-down circuit 1 for the active time includes pMOS transistors 12, 1
3. A differential amplifier type comparison circuit composed of nMOS transistors 14 to 16 and a feedback loop for controlling 17 pMOS transistors in accordance with the comparison result. The step-down circuit 1 for the active state is inactive in the standby state for the purpose of suppressing the power consumption of the entire chip. This control is performed by an ACT signal which is an internal signal, and ACT = L is set during standby. Further, the step-down circuit 2 for the standby mode has
To 26 pMOS transistors 22 and 23, nMOS
The circuit is composed of a differential amplifier type comparison circuit composed of transistors 24 to 26, and a feedback loop for controlling 27 pMOS transistors in accordance with the comparison circuit. . Since the step-down circuit 2 for standby is always in the active state, DRA
When the operation of M is in standby mode, only the step-down circuit 2 is activated to supply the step-down potential VINT. However, in the active state where a large supply capability of VINT is required, the step-down circuit 1 for the active state is further activated. To supply a stable step-down potential VINT. For this reason, the size of the transistor forming the step-down circuit 2 for standby is set smaller than the size of the transistor forming the step-down circuit 1 for active. The step-down circuit 3 receives the step-down potential VINT generated by the step-down circuit 1 or step-down circuit 2 and generates a step-down potential VBLP and a step-down potential VCP that are exactly half of the step-down potential VINT. In the above circuit configuration, VINT is supplied as a power supply voltage for driving the sense amplifier,
VCP is the cell plate potential of the memory cell, VCP
BLP is supplied to the memory unit 4 as a potential for precharging the data line pair before the data of the memory cell is read by the sense amplifier. FIG. 6 is a block diagram of the conventional semiconductor memory device described above with reference to FIG. The operation and configuration are the same as those in FIG. 4, and thus the same configuration is denoted by the same reference numeral and description thereof is omitted here. As described above, the first step-down potential VINT generated by the internal step-down circuits 1 and 2 is supplied as a power source of the memory unit 4 and another step-down circuit is provided. By using as an input of
When generating the second step-down potentials VBLP and VCP such as the step-down potential of the first step-down potential, the first step-down potential (VINT)
The second step-down potential (VBLP, VCP) in synchronization with the fluctuation of
Are likely to fluctuate. In the semiconductor device having the step-down circuit shown in FIG.
The power supply potential supplied to the sense amplifier of the RAM,
Generally, in a DRAM, a large number of sense amplifier groups arranged in the same chip are simultaneously activated at the timing of a read operation or a refresh operation, and a large current flows transiently, so that the potential of VINT fluctuates greatly instantaneously. FIG.
Shows an example of the VINT waveform. As shown in the example of FIG.
Generally, the waveform of T fluctuates greatly in synchronization with the operation cycle of the DRAM itself, and in the circuit configuration shown in FIG.
Step-down potential VC created using the INT potential itself as input
P and VBLP are also affected by the fluctuation of VINT and fluctuate at the same time. On the other hand, VBLP is a potential used as a reference for signal detection as a voltage of the data line at the time of precharge.
Fluctuations in LP may degrade the criterion for reading data from a memory cell with a sense amplifier. Also, VCP
Is the potential of the memory cell capacitor electrode,
When the CP fluctuates, there is a possibility that the read operation characteristics may be degraded when the amount of charge stored in the memory cell is small, such as when the DRAM operates at a low voltage or during a pause time. In order to suppress the fluctuation of the step-down potential, the size of the driving transistor for the step-down potential is increased to increase the supply capability of the potential, or the fluctuation of the potential is suppressed by adding a smoothing capacitor to the step-down potential. I have responded. However, the required bit width and page length tend to increase as the capacity of the DRAM increases, and in recent years, custom logic such as a CPU and an ASIC has
Semiconductor devices that integrate AM in one chip have been put into practical use,
That trend is increasing. This is DR
As a result, the number of sense amplifiers that are simultaneously activated inside the AM is increased.
It has become difficult to keep the fluctuation of the NT / 2 potential small. According to the present invention, a first step-down potential obtained by stepping down an external power supply potential is output to a memory unit.
, A second step-down circuit for stepping down an external power supply potential and outputting a second step-down potential having the same potential as the first step-down potential to a third step-down circuit, and stepping down the second step-down potential a third step-down circuit the third down-converted potential output to the memory unit comprising Te, a first step-down voltage, and a circuit directly coupled means directly connecting the second step-down voltage, the circuit directly means according to the operating state of the memory unit , And the second step-down potential is output to the third step-down circuit and is not output to the memory unit. With this configuration, the third step-down potential is a step-down circuit that has generated the first step-down potential (corresponding to the first step-down circuit).
Is generated by another step-down circuit (corresponding to the second and third step-down circuits), so that the third step-down potential output from the third step-down circuit to the memory unit is equal to the first step-down potential. Since there is no influence, the third step-down circuit can always supply a stable third step-down potential to the memory unit. Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) An embodiment of the present invention will be described with reference to FIG. Although not shown in FIG. 1, a VINT step-down circuit 51 for active mode and a VINT step-down circuit 51 for standby mode are provided.
INT step-down circuit 52, VINT1 step-down circuit 53, VIN
T limiter circuit 54, VINT1 limiter circuit 5
5. It is assumed that the external power supply potential VDD and the ground potential VSS are supplied to all of the VINT1 / 2 step-down circuits 56. As shown in FIG. 1, reference numeral 5 denotes a reference voltage generation circuit. The reference voltage generation circuit 5 converts a reference potential REFVINT generated based on the external power supply potential VDD to a VINT step-down circuit 51 for active use and a standby voltage for standby use. To the VINT step-down circuit 52 and the VINT1 step-down circuit 53. Reference numeral 7 denotes a timing generation circuit which outputs an ACT signal to a VINT step-down circuit 51 for active mode, a VINT step-down circuit 52 for standby mode, and a VINT1 step-down circuit 53. In addition, the timing generation circuit 7 supplies the BINT limiter circuit 54 and the VINT1 limiter circuit 55 with BIV
Outputs an INT signal. Reference numeral 51 denotes a step-down circuit which generates a step-down potential VINT obtained by stepping down VDD when active, 52 denotes a step-down circuit which generates a step-down potential VINT obtained by stepping down VDD during standby, and 53 denotes a step-down circuit which steps down VDD. Potential V
A step-down circuit for generating INT1, 54 defines an upper limit of the VINT potential, a VINT limiter circuit for equalizing the VINT potential to the VDD potential during the burn-in test, and 55 defines an upper limit of the VINT1 potential. Sometimes, a VINT1 limiter circuit for equalizing the VINT1 potential to the VDD potential, and 56 is a VINT1
Potential VBLP and reduced potential VCP obtained by stepping down voltage
Are shown, respectively. Reference numeral 6 denotes a potential direct connection means, which is a circuit for directly connecting VINT and VINT1. Next, the step-down circuit 51, step-down circuit 52, step-down circuit 53, limiter circuit 54 for VINT, limiter circuit 55 for VINT1, and step-down circuit 56 for VINT1 / 2 will be described with reference to FIGS. This will be described in more detail. In FIG. 2, the potential direct connection means 6 (constituted by the inverter circuit 89 and the pMOS transistor 90) shown in FIG. 1 is shown inside the VINT1 / 2 step-down circuit 56. As shown in FIG. 2, reference numeral 60 denotes an external power supply potential V
DD is a power supply line for supplying the entire circuit, and 61 is a power supply line for similarly supplying the ground potential VSS. REFVI
The wiring indicated by NT is a reference voltage generation circuit (FIG. 2)
, BIVINT indicate a signal line from a timing generation circuit (not shown in FIG. 2). In the step-down circuit 51 for the active time,
62 and 63 are pMOS transistors forming a current mirror circuit, and 64 and 65 are n transistors forming a driving transistor.
A MOS transistor 66 is an nMOS transistor forming a constant current source, and 67 is a pMOS transistor forming a regulator. The differential amplifier circuit composed of the transistors 62 to 66 functions as a comparison circuit for detecting a potential difference between the input potential REFVINT and the output potential VINT, and a feedback loop for controlling 67 pMOS transistors in accordance with the comparison result. And outputs VINT having the same potential as REFVINT. That is, the step-down potential VINT changes to the input potential RE.
When the voltage of the pMOS transistor 67 starts to become lower than FVINT, the gate potential of the pMOS transistor 67 becomes lower.
Start charging. The output potential VINT rises and REFV
On the other hand, when the voltage starts to become higher than INT, the pMOS transistor 67 is turned off because the gate potential rises.
Charging stops. By such an operation, the reduced potential VI
The fluctuation of NT can be suppressed. In the step-down circuit 52 for standby, 72 and 73 are pMOSs forming a current mirror circuit.
Transistors 74 and 75 are nMOS transistors serving as driving transistors, and 76 is an nM transistor serving as a constant current source.
OS transistor, 77 is a pMOS that forms a regulator
It is a transistor. The differential amplifier circuit composed of the transistors 72 to 76 functions as a comparison circuit for detecting a potential difference between the input potential REFVINT and the output potential VINT, and a feedback loop for controlling the pMOS transistor 77 according to the comparison result. And REFVIN
VINT having the same potential as T is output. The active step-down circuit 51 for performing the above operation is inactive in the standby state for the purpose of suppressing the power consumption of the entire chip. This control is performed by the ACT signal supplied from the timing generation circuit 7, and ACT = L is set during standby. At this time, the nMOS transistor 66 is turned off, and pMO
Since the S transistor 68 is turned on, the pMOS transistor 67 whose gate is supplied with the H level is turned off.
In this case, the differential amplifier circuit becomes inactive and the output potential becomes high impedance. On the other hand, the configuration of the standby VINT step-down circuit 52 is the same as that of the active state VINT step-down circuit 51, and the transistors 72 to 77 have the same functions as the transistors 62 to 67, respectively. The size is designed to be relatively small for the purpose. Also, nMO
Since the gate electrode of S transistor 76 is fixed at power supply potential VDD, step-down circuit 52 for standby is always active. That is, during standby, only the step-down circuit 52 is activated to supply the step-down potential VINT. However, at the time of an active state in which a large supply capability of VINT is required, the step-down circuit unit 51 for the active state is further activated. The supply of the stable step-down potential VINT is compensated. In the VINT1 step-down circuit 53, 82 and 83 are pMOS transistors forming a current mirror circuit, 84 and 85 are nMOS transistors forming a driving transistor, and 86 is an nMO transistor forming a constant current source.
The S transistor 87 indicates a pMOS transistor forming a regulator. Reference numeral 88 denotes a pMOS transistor for setting the output of the step-down circuit to a high impedance state, 89 denotes an inverter circuit for generating an inverted signal of the ACT signal, and 90 denotes a pMOS transistor for directly connecting VINT and VINT1. 82 to 8
The circuit configuration of the differential amplifier circuit composed of six transistors is similar to that of the active-state VINT step-down circuit 51, but the size of each transistor is designed to be relatively small. VINT1 step-down circuit 5
3 has the same function as the active-time VINT step-down circuit 51 in that it outputs the same potential as the input potential REFVINT, and the generated potential VINT1 is set exactly equal to the step-down potential VINT. In addition, the operation of the operation amplifier itself becomes inactive at the time of standby, that is, at the time of ACT = L, has the same function as the step-down circuit 51.
INT1 and VINT are directly connected, and the VINT1 potential is supplied from the step-down circuit 52 for standby.
This step-down potential VINT1 is not supplied to other circuits except that it is supplied as an input potential of the VBLP and VCP step-down circuit 56. In FIG. 2, in the VINT limiter circuit 54, the pMOS transistor 100 and the nMOS transistor 102 have the signal BIVINT supplied from the timing generation circuit at the gate electrode. During normal operation, BIVINT is fixed at the H potential, the pMOS transistor 100 is turned off, and the nMOS transistor 10 is turned off.
2 is turned on, the pMOS transistor 1
The drain potential of 01 is almost the ground potential VSS.
Here, the function of the pMOS transistor 101 is that the source potential VINT is compared with the gate potential REFVINT.
Is the threshold potential VTP of the pMOS transistor 101
Since the current starts to flow when the voltage becomes higher by this amount, this circuit functions as a clamp circuit for preventing the potential of VINT from becoming higher than a certain level. On the other hand, at the time of chip burn-in test, BIVINT = L is set. At this time, the pMOS transistor 100 is turned on and the nMOS
The transistor 102 is turned off, and the transistor 1
Via 00, the VINT potential is set to the same potential as VDD. This circuit means is used because it is necessary to uniformly accelerate the stress condition in the normal operation during the burn-in operation. The 55 VINT1 limiter circuit is also a circuit having a similar configuration for realizing the above-described desired function for the step-down potential VINT1, and the transistors 110 to 112 have the same function as the transistors 100 to 102. Further, the step-down circuit 56 is a step-down circuit which receives the step-down potential VINT1 generated by the step-down circuit 53 as input and generates a step-down potential VBLP or VCP of a half level thereof. The values of the resistors 91 and 94 are sufficiently large and equivalent, and the potential of the node 99 is designed to be VINT1 / 2 based on the resistance ratio. If the threshold value of the transistor in this circuit is uniformly VT, the potentials of the nodes 97 and 98 are (VINT / 2) + VT, (VI) due to the clamping action of the transistor nMOS transistor 92 and the pMOS transistor 93, respectively.
NT / 2) -VT, and the output potential is stabilized at VINT1 / 2. At this time, the nMOS transistor 95 has a function of flowing a current from the power supply line to the output when the output potential falls below the VINT1 / 2 level, thereby increasing the output potential.
Conversely, the output potential of the pMOS transistor 96 is VINT1
When the voltage exceeds the / 2 level, a current flows from the output to the ground line to lower the output. In the semiconductor device having the step-down circuit configured as described above, the step-down potential VINT is a power supply potential supplied to the memory cell array of the DRAM. This VINT
The voltage is mainly consumed as a power supply of a sense amplifier group for reading data from a memory cell. In general, in a DRAM, a plurality of sense amplifier groups in a device are simultaneously activated at timings such as a read operation and a refresh operation, and VI is used.
A large current flows from NT. The current flowing at this time is DRAM
Is a large current that accounts for most of the current consumption of
The level of VINT shows a large fluctuation instantaneously. FIG. 3 is a waveform diagram for explaining the operation of the circuits shown in FIGS. The ACT signal generated by the timing generation circuit 7 is set to ACT = H when the VINT consumption is large, such as during a DRAM read operation or a refresh operation, and the step-down circuit is controlled so as to increase the VINT supply capability. Perform However,
It is difficult to reduce the influence of the large current described above by a circuit method, and the waveform of VINT fluctuates as shown in the figure. On the other hand, V supplied by the step-down circuit 53
Since INT1 is not used except for being used as the input potential of the step-down circuit 56, its level does not fluctuate in synchronization with the internal operation state of the memory.
Always keep a stable level as shown. On the other hand, VBL
Since P and VCP are made using VINT1 as an input, the same stable operation can be expected. As a result, even when a potential fluctuation occurs in the step-down potential VINT, VI
The step-down potentials VBLP and VCP having the NT / 2 potential can be stabilized. This is very effective for setting the cell plate potential VCP of the memory cell requiring high accuracy and supplying a stable bit line precharge level VBLP. In the present embodiment, the activation period of the step-down circuit 53 is limited to only the active period in order to reduce the power consumption at the time of standby, and the VINT1 level is supplied from VINT at the time of standby. Step-down circuit 5
3 may be always activated similarly to the step-down circuit 52. Further, as for VINT, the voltage step-down circuit 51 in the active state and the voltage step-down circuit 52 in the standby state are not properly used. A configuration in which the VINT supply capacity can be changed stepwise may be used. In short, when configuring the second step-down circuit that generates VINT / 2 which is just half the level of the step-down potential VINT generated by the first step-down circuit, VINT is not used directly as the input potential. Then, a step-down potential VINT1 having the same potential as VINT may be generated using the third step-down circuit, and this VINT1 may be used as the input potential of the second step-down circuit. As long as the above essence is not impaired, there is no particular limitation on the circuit system of the circuit blocks of 51 to 56. The semiconductor memory device of the present invention may be configured as a general-purpose DRAM in which a dynamic memory cell and its peripheral circuits are integrated, or may be a dynamic memory cell and its peripheral circuits, a CPU and a custom logic. May be integrated in the same chip. The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above embodiment, and various design changes can be made without departing from the spirit of the present invention. Of course. The limiter circuit 54 for VINT and the limiter circuit 55 for VINT1 are not always necessary to obtain the effect of the present embodiment. According to the present invention, the internal step-down potential VINT and the internal step-down potential VI are obtained by stepping down the external power supply potential VDD.
Internal step-down potentials VBLP and VCP obtained by stepping down NT
Of the step-down circuit for generating the VBLP and VCP potentials as VIN
A step-down potential VINT1 which is the same potential as VINT and is supplied by another step-down circuit without using T is used. This VINT
1 is used only as an input to the step-down circuit for generating the VBLP and VCP potentials, so that even if the level of VINT fluctuates in synchronization with the operation cycle of the DRAM, a stable VBLP does not fluctuate under the influence of the fluctuation. And VCP potential. The VCP and VBLP have the reduced potentials as the potentials of the memory cell capacitor electrodes of the DRAM, respectively.
Alternatively, high potential setting accuracy and stable level supply are required as determination reference potentials when reading data from a memory cell. By applying the present invention, the external power supply potential and other internal step-down potentials are temporarily reduced. It is possible to obtain a semiconductor memory device that performs a stable operation even when it fluctuates.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device of the present invention. FIG. 2 is a circuit diagram showing an embodiment of a semiconductor memory device of the present invention. FIG. 4 is a circuit diagram illustrating a conventional semiconductor memory device. FIG. 5 is a waveform diagram illustrating a conventional semiconductor memory device. FIG. 6 is a waveform diagram illustrating a conventional semiconductor memory device. Block diagram showing storage device [Description of reference numerals] 1 step-down circuit 2 step-down circuit 3 step-down circuit 4 memory unit 5 reference voltage generation circuit 6 potential direct connection means 7 timing generation circuit 10 power supply line (VDD) 11 power supply line (VSS) 12, 22 pMOS transistor 13, 23 pMOS transistor 14, 24 nMOS transistor 15, 25 nMOS transistor 16, 26 nMOS transistor 17, 27 pMOS transistor Transistor 19 pMOS transistor 51 step-down circuit 52 step-down circuit 53 step-down circuit 54 limiter circuit for VINT 55 limiter circuit 56 for VINT1 VINT1 / 2 step-down circuit 60 power supply line (VDD) 61 power supply line (VSS) 62, 72, 82 pMOS transistor 63, 73, 83 pMOS transistors 64, 74, 84 nMOS transistors 65, 75, 85 nMOS transistors 66, 76, 86 nMOS transistors 67, 77, 87 pMOS transistors 68, 88 pMOS transistors 100, 110 pMOS transistors 101, 111 pMOS transistors 102, 112 nMOS transistor 90 transistor 91, 94 resistor 92, 95 nMOS transistor 93, 96 pMOS transistor 97, 98, 991 / Wiring of the step-down circuit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-93977 (JP, A) JP-A-8-55480 (JP, A) JP-A-5-334879 (JP, A) 325569 (JP, A) JP-A-11-250665 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G11C 11/401-11/419

Claims (1)

(57) A semiconductor memory device using a reduced potential obtained by stepping down an external power supply potential supplied from the outside as a power supply of a memory unit, wherein the external power supply potential is stepped down. A first step-down circuit for outputting a first step-down potential to the memory section, and a third step-down circuit for stepping down the external power supply potential and setting a second step-down potential having the same potential as the first step-down potential. Output to the second
A third step-down circuit that outputs a third step-down potential obtained by stepping down the second step-down potential to the memory unit; a first step-down potential; and a second step-down potential And a control means for controlling the circuit direct connection means in accordance with an operation state of the memory unit, wherein the second step-down potential is output to the third step-down circuit , and A semiconductor memory device which is not output to a memory unit.