JP2014007458A - Reception circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a reception circuit that stabilizes signal propagation.SOLUTION: A reception circuit 1 for receiving a differential open drain output, which is fed to a pair of reception terminals 4 as an example of first and second external connection terminals, comprises: an inductor Land a termination resistance Rconnected in series between one of the reception terminals 4 and a supply voltage V; and an inductor Land a termination resistance Rconnected in series between the other of the reception terminals 4 and the supply voltage V.

Description

  The present invention relates to a receiving circuit, and more particularly to a receiving circuit that receives an open drain output.

  Some signal transmissions between large scale integrated circuits (LSIs) connected via a transmission line use an output circuit of an open drain type. The output circuit of the LSI has a transistor, and the drain of this transistor is connected to an external output terminal, and signal transmission is performed to another LSI via a transmission line connected to the external connection terminal.

  In Patent Document 1, as shown in FIG. 4A, an output NMOS transistor 101 is configured to be driven by a pre-buffer circuit 102, and the back gate voltage of the output NMOS transistor 101 is controlled. An open drain output circuit provided with the back gate voltage control circuit 103 is described. The drain of the output NMOS transistor 101 is connected to the output terminal 106 to form an open drain output circuit. A power supply voltage of the external circuit is applied to the output terminal 106 via a pull-up resistor 107 of the external circuit. The back gate voltage control circuit 103 includes a back gate driving NMOS transistor 105 and a constant current source 104. The back gate of the output NMOS transistor 101 is connected to the drain of the back gate driving NMOS transistor 105 to which the constant current source 104 is connected.

  In this open drain output circuit, a positive voltage is applied to the back gate in a region where the input power supply voltage is low where the output NMOS transistor 101 is not yet turned on. Further, when the input power supply voltage rises, the back gate driving NMOS transistor 105 is turned on together with the output NMOS transistor 101, and the back gate of the output NMOS transistor 101 becomes the ground level. As a result, it is described that the threshold voltage of the output NMOS transistor 101 is lowered and the increase of the output voltage is suppressed.

  Patent Document 2 relates to a circuit board on which a coil component such as a common mode filter is mounted and used in a differential transmission device. This will be described with reference to FIG. A terminal electrode 115 of a common mode filter 116 is connected to the electrode pad 113 of the circuit board 111. The planar spiral line 117 is a planar spiral line that is not connected to the terminal electrode 115. The electrode pad 113 is outside the boundary 110 of the projection pattern on the circuit board of this line. The electrode pad 113 is different from the portion of the planar spiral line other than the portion extended for connection with the terminal electrode (the portion of the planar spiral line 118 sandwiched between broken lines in FIG. 4B) in plan view. Arranged so as not to overlap. Further, the electrode pad 113 connected to the planar spiral line 118 does not overlap the other planar spiral line 117 in plan view. Thereby, since the electrode pad 113 and the planar spiral lines 117 and 118 are sufficiently separated from each other, the coupling is weakened and the parasitic capacitance is reduced. Thus, it is described that the common mode impedance is increased and a high common mode noise attenuation effect can be obtained.

JP 2007-104181 A JP 2008-262943 A

  However, a receiving circuit that receives an open drain output has the following problems. That is, there is a parasitic capacitance in the transmission path between LSIs, and the higher the frequency, the more difficult the signal propagation. This is because the waveform bluntness increases and the amplitude decreases in proportion to the frequency in the high frequency region due to the influence of the parasitic capacitance in the transmission path. This problem cannot be solved even if the methods described in Patent Document 1 and Patent Document 2 are used.

  An object of the present invention is to provide a receiving circuit capable of stably performing signal propagation by suppressing attenuation of signal amplitude between LSIs in a system operating at a high frequency.

To achieve the above object, a receiving circuit according to the present invention is a receiving circuit that receives a differential open drain output,
The differential open drain output is applied to first and second external connection terminals,
A first inductor and a first termination resistor connected in series between the first external connection terminal and a power supply voltage, and a series connection between the second external connection terminal and the power supply voltage. And a second inductor and a second termination resistor.

  The present invention can stably transfer high-frequency data.

It is a circuit diagram for demonstrating the receiving circuit by one Embodiment of this invention. (A) is a circuit diagram for demonstrating operation | movement of the receiver circuit by one Embodiment of this invention, (b) is a state transition diagram which shows the state transition of each node. (A) is a graph showing the voltage waveform at the node A, node B and node C, which is a graph showing the (b) is _{i 1} and _i 1 -i ₂ of the current waveform. (A) is a circuit diagram which shows the open drain output circuit of patent document 1, (b) is sectional drawing which shows the circuit board which mounts the coil components of patent document 2. FIG.

  Preferred embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram for explaining a receiving circuit according to an embodiment of the present invention.

  The receiving circuit according to the present embodiment is used in a system in which signal transmission between LSIs is performed on a differential transmission path. The receiving circuit of this embodiment is a receiving circuit 1 of one LSI, and is connected to a transmitting circuit 2 of another LSI by a differential transmission path 3.

The transmission circuit 2 is a differential open drain output circuit, and includes a transistor Tr ₁ in which a source / drain path is inserted between a power supply voltage V _ss and one transmission terminal 5, a power supply voltage V _ss and another one. A transistor Tr ₂ having a source / drain path inserted between the transmission terminal 5 and the transmission terminal 5 is provided. The inverted signal of the input node A is input to the gate of the transistor Tr ₂ , that is, the input node Ab, and an open drain output that is a differential transmission signal is output to the transmission path 3.

As shown in FIG. 1, the receiving circuit according to the present embodiment is a receiving circuit 1 that receives a differential open drain output, and the differential open drain output is an example of first and second external connection terminals. And an inductor L ₁ and a terminating resistor R ₁ connected in series between one receiving terminal 4 and the power supply voltage V _dd , another receiving terminal 4 and the power supply voltage V _The inductor L ₂ and the termination resistor R ₂ are connected in series with _dd . Here, L ₁ = L ₂ , R ₁ = R ₂ , and C ₁ = C ₂ are set.

More specifically, the terminating resistor R ₁ is connected between the node C and the power supply voltage V _dd as an example of the first node, the node Cb and the power supply voltage V _dd as an example of a second node terminating resistor R ₂ is connected between the. Furthermore, the inductor L ₁ is connected between a reception terminal 4 and the node C, the inductor L ₂ is connected between the receiving terminal 4 and the node Cb. In FIG. 1, the node B is connected to one receiving terminal 4, and the node Bb is connected to another receiving terminal 4.

Next, the operation of the receiving circuit of this embodiment will be described. FIG. 2A is a circuit diagram for explaining the operation of the receiving circuit according to the embodiment of the present invention, and FIG. 2B is a state transition diagram showing state transitions of the nodes A, B, and C. FIG. 3A is a graph showing voltage waveforms at node A and node B, where the horizontal axis indicates time (unit: picoseconds) and the vertical axis indicates voltage. FIG. 3B is a graph showing current waveforms of i ₁ and i ₁ -i ₂ , where the horizontal axis represents time (unit: picoseconds) and the vertical axis represents current.

Input node A changes from the low level to the high level, when the condition (1) in FIG. 2 (b), the turned on transistor Tr ₁ is from off, the current i ₁ flows, low level potential of the node B from the high level Lower. That is, as shown in FIG. 3A, the potential of the node B decreases from the high level to the low level as the node A increases from the low level to the high level. The parasitic capacitance C ₁ in the transmission path is discharged, the current i ₂ flows, and the current i ₁ -i ₂ flows in the inductor L ₁ and the resistor R ₁ . Input node Ab, since the inverted signal of the input node A is input, the transistor Tr ₂ is turned from ON to OFF, no current i ₁ flows, increase the potential of the node Bb from the low level to the high level. Flow (reverse current with respect to the arrow direction of the current _{i 2b} in FIG. 2 (a)) the parasitic capacitance _{C 2} is charged current _{-i 2b} in the transmission path, the inductor _{L 2} and the resistor _{R 2} to the current _{i 2b} is Flowing.

The input node A is changed from the high level to the low level, when the condition (2) in FIG. 2 (b), the transistor Tr ₁ is turned from ON to OFF, no current i _1b flowing, high potential of the node B from the low level Raise to level. That is, as shown in FIG. 3A, the potential of the node B rises from the low level to the high level in response to the fall of the node A from the high level to the low level. The parasitic capacitance C ₁ in the transmission line is charged and current −i ₂ (current in the direction opposite to the arrow direction of the current i _{2 in} FIG. 2A) flows, and the current i ₂ flows through the inductor L ₁ and the resistor R _1. Flowing. Input node Ab, since the inverted signal of the input node A is input, the transistor Tr ₂ is turned on from off, the current i _1b flows, reduced to a low level potential of the node Bb from the high level. Parasitic capacitance _{C 2} is discharged currents _{i 2b} in the transmission line flows, current flows _i 1b _{-i 2b} in the inductor _{L 2} and the resistor _{R 2.}

Here the receiving circuit of this embodiment, since the transmission path to the inductor L are connected in series, when the state of (1), the current flowing through the resistor R ₁ with the node B changes from the high level to the low level , I ₂ to i ₁ -i ₂ . Since this current also flows through the inductor L ₁ , the node B has an induced electromotive force L × dI / dt in the inductor L ₁ rather than the node C (dI / dt is an increase / decrease in current per unit time flowing through the inductor). The low level is reached quickly by the voltage difference. If the state of (2), the current flowing through the resistor _{R 1} with the node B changes from the low level to the high level _is reduced from i 1 -i ₂ to _{i 2.} Since this current flows through the inductor L _1, Node B, the partial voltage differential induced electromotive force L × dI / dt of the inductor L ₁ than the node C, reaches quickly high. From the description of the operations of the state (1) and the state (2), the amplitude increases because the low level or the high level is reached faster than when there is no inductor.

  According to the receiving circuit of this embodiment, even when differential transfer data from the open drain output has a high frequency, a sufficient signal amplitude can be secured and data transfer can be performed normally. Furthermore, even if the differential transfer data from the open drain output has a high frequency, restrictions such as the wiring length in the electronic board design can be relaxed. The reason is that the dullness of the data waveform due to the parasitic capacitance existing in the data transmission path can be reduced by the inductor connected in series. As described above, according to the present embodiment, it is possible to provide a receiving circuit capable of stably performing signal propagation by suppressing attenuation of the amplitude of signals between LSIs in a system operating at a high frequency.

  As mentioned above, although this invention was demonstrated about preferable embodiment, this invention is not limited to this.

1 receiving circuit 2 transmits circuit 3 transmission path 4 receiving terminal 5 sends the terminal Tr _1, Tr ₂ transistor R _{1, R 2} terminating resistors L _{1, L 2} inductor C _{1, C 2} parasitic capacitance

Claims (3)

A receiving circuit for receiving a differential open drain output,
The differential open drain output is applied to first and second external connection terminals,
A first inductor and a first termination resistor connected in series between the first external connection terminal and a power supply voltage, and a series connection between the second external connection terminal and the power supply voltage. A receiving circuit comprising: a second inductor; and a second termination resistor. The first termination resistor is connected between a first node and the power supply voltage, and the second termination resistor is connected between a second node and the power supply voltage,
The first inductor is connected between the first external connection terminal and the first node, and the second inductor is connected between the second external connection terminal and the first node. The receiving circuit according to claim 1, wherein: is connected.   The inductance of the first inductor and the inductance of the second inductor are substantially equal, and the resistance value of the first termination resistor and the resistance value of the second termination resistor are substantially equal. The receiving circuit according to claim 1 or 2.

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