JP2015019160A - Driver circuit, differential transmitter using the same, electronic apparatus, and industrial apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the effects of backflow preventing diodes.SOLUTION: A first PMOS transistor MP11 and a second PMOS transistor MP12 are disposed between a power line LVCC and an output terminal OUT, and a first NMOS transistor MN11 and a second NMOS transistor MN12 are disposed between the output terminal OUT and a ground line LGND. A source of a third PMOS transistor MP13 is connected to the output terminal OUT, and a gate thereof is biased by a first bias circuit 20 so as to be turned on when VOUT>VH. A source of a third NMOS transistor MN13 is connected to the output terminal OUT, and a gate thereof is biased by a second bias circuit 30 so as to be turned on when VOUT<VL.

Description

  The present invention relates to a transmitter that outputs a signal to a transmission line.

  As a standard for high-speed serial transmission of a digital signal, a communication method using a differential signal such as RS485 standard, RS422, or LVDS (Low Voltage Differential Signaling) standard has been proposed.

  FIG. 1A is a circuit diagram of a differential transmitter studied by the present invention, and FIG. 1B is a diagram showing voltage-current characteristics of the driver circuit of FIG.

The differential transmission line 4 is connected to the differential output terminal OUTP / OUTN of the differential transmitter 2r. Differential transmitter 2r from the differential output terminal OUTP / OUTN, and outputs a differential signal comprising a positive signal _{S OUTP} and a negative signal _{S OUTN.}

Differential transmitter 2r is provided with a positive signal _S P side of the driver circuit 10P which outputs the _OUTP, driver circuit 10N of N side for outputting a negative signal _{S OUTN.} Since the driver circuits 10P and 10N are configured similarly, only the configuration of the driver circuit 10P is shown in FIG.

The driver circuit 10P receives at its input terminals DIP and DIN control signals S _IN and S _IP from a pre-driver (not shown) provided at the preceding stage, and receives a positive signal S according to the control signals S _IN and S _{IP. OUTP} is output.

  The driver circuit 10P includes a high side transistor MP1 provided between the power supply line LVCC and the output terminal OUT, and a low side transistor MN1 provided between the output terminal OUT and the ground line LGND. When the high side transistor MP1 is on and the low side transistor MN1 is off, the output voltage VOUT of the driver circuit 10 becomes a high level voltage (VCC), and when the high side transistor MP1 is off and the low side transistor MN1 is on, the driver circuit 10 The output voltage VOUT becomes a low level voltage (VGND). Further, when both the high side transistor MP1 and the low side transistor MN1 are turned off, a high impedance (High-Z) state is obtained.

  In half-duplex communication in which transmission and reception are performed on the same transmission line as in the RS485 standard, when the receiver (not shown) side is off, the voltage VOUT of the output OUTP (OUTN) of the driver circuit 10P is the power supply There is a case where the voltage is higher than the voltage VCC (for example, 5V) (for example, 12V) or the voltage is lower than the ground voltage VGND (for example, 0V) (for example, -7V).

  When these voltages are applied between the drain and source of a general MOSFET (Metal Oxide Semiconductor Field Effect Transistor), the MOSFET cannot be kept off, or the MOSFET is formed via its body diode. As a result, a large current flows through the semiconductor substrate, which disturbs the waveform on the transmission line 4 and interferes with communication.

  Therefore, in order to prevent a backflow current from flowing to the high side transistor MP1 when the output voltage VOUT is higher than the power supply voltage VCC, a backflow prevention diode DP12 is inserted between the power supply line LVCC and the output terminal OUTP. . Similarly, when the output voltage VOUT is lower than the ground voltage VGND, a backflow prevention diode DN12 is inserted between the output terminal OUTP and the ground line LGND in order to prevent a backflow current from flowing to the low-side transistor MN1 side. The

FIG. 1B shows voltage-current (VOUT-IOUT) characteristics of the driver circuit 10 shown in FIG. In operation of the differential transmitter 2, across the diode for preventing reverse current DP12, DN12, for the forward voltage V _F is generated, there is a problem that the amplitude of the output voltage VOUT is narrowed. In order to cope with this problem, the power supply voltage VCC must be increased and cannot be used in a system with a low power supply voltage.

  Further, when the driver circuit 10P side is viewed from the output terminal OUTP, the arrangement of the diodes and the MOSFETs on the power supply line LVCC side and the ground line LGND side becomes asymmetric, so that the symmetry of the waveform of the output voltage VOUT is impaired. There is a problem.

  The present invention has been made in view of such a situation, and one of exemplary purposes of an embodiment thereof is to provide a driver circuit capable of suppressing the influence of a diode for preventing backflow.

  An embodiment of the present invention relates to a driver circuit that generates an output voltage at a level corresponding to a first control signal and a second control signal at an output terminal. The driver circuit includes a first PMOS transistor having a drain connected to the output terminal and a gate receiving a first control signal, a second PMOS transistor having a drain connected to the source of the first PMOS transistor, and a source connected to the power supply line. A first NMOS transistor having a drain connected to the output terminal and a gate receiving a second control signal; a second NMOS transistor having a drain connected to the source of the first NMOS transistor and a source connected to the ground line; A third PMOS transistor connected to the output terminal, having a drain connected to the gate of the second PMOS transistor, a third NMOS transistor having a source connected to the output terminal, and a drain connected to the gate of the second NMOS transistor; No. 1 threshold A first bias circuit that biases the gate of the third PMOS transistor so that the third PMOS transistor is turned on when higher, and a third NMOS transistor that is turned on when the output voltage is lower than a predetermined second threshold value. And a second bias circuit for biasing the gate of the third NMOS transistor.

  According to this aspect, when the output voltage is within the range between the first threshold value and the second threshold value, the second PMOS transistor and the second NMOS transistor provided for preventing the reverse current are turned on. Compared with the case where a diode is provided for prevention, a voltage drop corresponding to the forward voltage of the diode can be eliminated. Thereby, the amplitude of the output voltage can be increased under the same power supply voltage condition, or the power supply voltage necessary for obtaining the same amplitude can be reduced. In addition, the symmetry of the circuit viewed from the output terminal can be increased.

  An embodiment of the driver circuit includes a fourth PMOS transistor having a source connected to the power supply line, a drain connected to the back gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, and a gate connected to the drain of the third PMOS transistor. A fourth NMOS transistor having a source connected to the ground line, a drain connected to the back gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor, and a gate connected to the drain of the third NMOS transistor. Good.

  According to this aspect, the back gates of the first to third PMOS transistors are not fixed to the power supply voltage, and the fourth PMOS transistors are inserted between the back gate and the power supply line, so that the back gates are in a floating state. And the leakage current to the power supply line can be suppressed. Similarly, the back gate of the first NMOS transistor to the third NMOS transistor is not fixed to the ground voltage, and the fourth NMOS transistor is inserted between the back gate and the ground line, thereby suppressing the leakage current to the ground line. Can do.

The first bias circuit may include a fifth PMOS transistor having a source connected to the power supply line, a drain and gate connected to the gate of the third PMOS transistor, and a first current source connected to the drain of the fifth PMOS transistor. Good. The second bias circuit may include a fifth NMOS transistor having a source connected to the ground line, a drain and a gate connected to the gate of the third NMOS transistor, and a second current source connected to the drain of the fifth NMOS transistor. Good.
According to this aspect, the gate voltage of the third PMOS transistor becomes the voltage VCC-VTH that is lower than the power supply voltage VCC by the threshold voltage VTH of the MOSFET. Thereby, the first threshold value can be set to the power supply voltage VCC.
Similarly, the gate voltage of the third NMOS transistor becomes a voltage VGND + VTH that is higher than the ground voltage VGND by the threshold voltage VTH of the MOSFET. As a result, the third NMOS transistor can have the second threshold value set to the ground voltage VGND.

  The driver circuit according to an aspect may further include a third current source connected to a drain of the third PMOS transistor and a fourth current source connected to a drain of the third NMOS transistor.

The driver circuit according to an aspect further includes a first resistor provided between the power supply line and the source of the second PMOS transistor, and a second resistor provided between the source of the second NMOS transistor and the ground line. Good.
According to this aspect, it is possible to cancel the temperature dependence of the on-resistance of the MOS transistor and / or suppress variations in output amplitude due to manufacturing variations of the MOS transistor.

  Another aspect of the invention relates to a differential transmitter. The differential transmitter includes two of the above driver circuits in pairs. The differential transmitter is configured to be capable of outputting the output voltage of one driver circuit as a positive signal of the differential signal and the output voltage of the other driver circuit as a negative signal of the differential signal.

Another aspect of the invention also relates to a differential transmitter. The differential transmitter includes two of the above driver circuits in pairs. The differential transmitter is configured to be capable of outputting the output voltage of one driver circuit as a positive signal of the differential signal and the output voltage of the other driver circuit as a negative signal of the differential signal. The source of the second NMOS transistor of one driver circuit and the source of the second NMOS transistor of the other driver circuit are connected in common, and the source of the second PMOS transistor of one driver circuit and the second PMOS of the other driver circuit The transistor sources are connected in common.
According to this aspect, it is possible to cancel the temperature dependence of the on-resistance of the MOS transistor and / or suppress variations in output amplitude due to manufacturing variations of the MOS transistor. In addition, the first PMOS transistor and the first NMOS transistor of one driver circuit and the first PMOS transistor and the first NMOS transistor of the other driver circuit can be operated as a differential pair that branches current from a common resistor, As a result, the output waveform can be adjusted.

  Another embodiment of the present invention relates to an electronic device. The electronic device may include any of the differential transmitters described above.

  Another aspect of the present invention relates to industrial equipment. The industrial equipment may include any of the differential transmitters described above.

  Note that any combination of the above-described components, or a conversion of the expression of the present invention between methods, apparatuses, and the like is also effective as an aspect of the present invention.

  According to an aspect of the present invention, the influence of a backflow prevention diode can be suppressed.

FIG. 1A is a circuit diagram of a differential transmitter studied by the present invention, and FIG. 1B is a diagram showing voltage-current characteristics of the driver circuit of FIG. It is a circuit diagram of a driver circuit concerning an embodiment. FIG. 3A is a diagram illustrating the voltage-current characteristics of the driver circuit of FIG. 2, and FIG. 3B is a diagram illustrating the state of the driver circuit. 4A and 4B are block diagrams of an electronic device and an industrial device including the differential transmitter according to the embodiment. It is a circuit diagram of the driver circuit concerning the 1st modification. FIG. 6 is a block diagram of a differential transmitter including the driver circuit of FIG. 5.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected in addition to the case where the member A and the member B are physically directly connected. It includes the case of being indirectly connected through another member that does not affect the connection state.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

FIG. 2 is a circuit diagram of the driver circuit 10 according to the embodiment. The driver circuit 10 generates the output voltage VOUT of the level corresponding to the first control signal _{S IP} and the second control signal _{S IN} to the output terminal OUT.

  The driver circuit 10 includes a first PMOS transistor MP11, a second PMOS transistor MP12, a third PMOS transistor MP13, a first NMOS transistor MN11, a second NMOS transistor MN12, a third NMOS transistor MN13, a first bias circuit 20, a second bias circuit 30, and a third current. A source CS3, a fourth current source CS4, and ESD protection diodes ESD2 and ESD1 are provided.

The drain of the first PMOS transistor MP11 is connected to the output terminal OUT, and the first control signal _SIP is input to the gate thereof. The drain of the second PMOS transistor MP12 is connected to the source of the first PMOS transistor MP11, and the source is connected to the power supply line LVCC.

The drain of the first NMOS transistor MN11 is connected to the output terminal OUT, and the second control signal _SIN is input to the gate thereof. The drain of the second NMOS transistor MN12 is connected to the source of the first NMOS transistor MN11, and the source is connected to the ground line LVSS.

  The source of the third PMOS transistor MP13 is connected to the output terminal OUT, and the drain thereof is connected to the gate of the second PMOS transistor MP12. The source of the third NMOS transistor MN13 is connected to the output terminal OUT, and the drain is connected to the gate of the second NMOS transistor MN12.

  The first bias circuit 20 biases the gate of the third PMOS transistor MP13 so that the third PMOS transistor MP13 is turned on when the output voltage VOUT generated at the output terminal OUT is higher than a predetermined first threshold value VH. First threshold value VH is set near power supply voltage VCC.

  For example, the first bias circuit 20 includes a fifth PMOS transistor MP15 and a first current source CS1. The source of the fifth PMOS transistor MP15 is connected to the power supply line LVCC, and the drain and gate thereof are connected to the gate of the third PMOS transistor MP13. The first current source CS1 is connected to the drain of the fifth PMOS transistor MP15, and generates a predetermined bias current IBP2. As a result, the drain voltage of the fifth PMOS transistor MP15 becomes VCC-VTH. That is, the first bias circuit 20 applies the bias voltage Vbp = VCC−VTH to the gate of the third PMOS transistor MP13. VTH is a gate-source voltage of the fifth PMOS transistor MP15, which is a physical property value. The third PMOS transistor MP13 is turned on when the output voltage VOUT becomes lower than VH = Vbp + VTH. That is, the first threshold value VH is equal to VCC.

  The second bias circuit 30 biases the gate of the third NMOS transistor MN13 so that the third NMOS transistor MN13 is turned on when the output voltage VOUT generated at the output terminal OUT is lower than a predetermined second threshold value VL. Second threshold VL is set near ground voltage VGND.

  For example, the second bias circuit 30 includes a fifth NMOS transistor MN15 and a second current source CS2. The source of the fifth NMOS transistor MN15 is connected to the ground line LGND, and the drain and gate thereof are connected to the gate of the third NMOS transistor MN13. The second current source CS2 is connected to the drain of the fifth NMOS transistor MN15, and generates a predetermined bias current IBN2. As a result, the drain voltage of the fifth NMOS transistor MN15 becomes VGND + VTH. That is, the second bias circuit 30 applies the bias voltage Vbn = VGND + VTH to the gate of the third NMOS transistor MN13. VTH is a gate-source voltage of the fifth NMOS transistor MN15, which is a physical property value. The third NMOS transistor MN13 is turned on when the output voltage VOUT becomes lower than VL = Vbn−VTH. That is, the second threshold value VL is equal to VGND.

  The source of the fourth PMOS transistor MP14 is connected to the power supply line LVCC, and the drain thereof is connected to the back gates of the first PMOS transistor MP11, the second PMOS transistor MP12, and the third PMOS transistor MP13. The gate of the fourth PMOS transistor MP14 is connected to the drain of the third PMOS transistor MP13.

  The source of the fourth NMOS transistor MN14 is connected to the ground line LGND, and the drain thereof is connected to the back gates of the first NMOS transistor MN11, the second NMOS transistor MN12, and the third NMOS transistor MN13. The gate of the fourth NMOS transistor MN14 is connected to the drain of the third NMOS transistor MN13.

  The third current source CS3 is connected to the drain of the third PMOS transistor MP13, and generates a predetermined bias current IBP1. The fourth current source CS4 is connected to the drain of the third NMOS transistor MN13, and generates a predetermined bias current IBN1.

  The above is the configuration of the driver circuit 10. Next, the operation will be described.

  FIG. 3A is a diagram illustrating the voltage-current characteristics of the driver circuit 10 in FIG. 2, and FIG. 3B is a diagram illustrating the state of the driver circuit 10.

The operation of the driver circuit 10 will be described by dividing it into the following three states.
First state VL <VOUT <VH
Second state VH <VOUT
Third state VOUT <VL

1. First state VL <VOUT <VH
As described above, the bias voltage Vbp is applied to the gate of the third PMOS transistor MP13. When the output voltage VOUT is between the power supply voltage VCC and the ground voltage VGND, the third PMOS transistor MP13 is turned off because the gate-source voltage of the third PMOS transistor MP13 is less than or equal to the threshold voltage VTH. At this time, the drain voltage of the third PMOS transistor MP13, that is, the gate voltage Vgp of the second PMOS transistor MP12 becomes a low level voltage, and the second PMOS transistor MP12 is turned on.

  Further, since the fourth PMOS transistor MP14 is also turned on, the back gates of the first PMOS transistor MP11, the second PMOS transistor MP12, and the third PMOS transistor MP13 are connected to the power supply line LVCC and biased to the power supply voltage VCC.

  Similarly, a bias voltage Vbn is applied to the gate of the third NMOS transistor MN13. When the output voltage VOUT is between the power supply voltage VCC and the ground voltage VGND, since the gate-source voltage of the third NMOS transistor MN13 is equal to or lower than the threshold voltage VTH, the third NMOS transistor MN13 is also turned off. At this time, the drain voltage of the third NMOS transistor MN13, that is, the gate voltage Vgn of the second NMOS transistor MN12 becomes a high level voltage, and the second NMOS transistor MN12 is turned on.

  Since the fourth NMOS transistor MN14 is also turned on, the back gates of the first NMOS transistor MN11, the second NMOS transistor MN12, and the third NMOS transistor MN13 are connected to the ground line LGND and biased to the ground voltage VGND.

2. Second state VH <VOUT
At this time, since the gate-source voltage of the third PMOS transistor MP13 becomes larger than the threshold voltage VTH, the third PMOS transistor MP13 is turned on. Thereby, the drain voltage of the third PMOS transistor MP13, that is, the gate voltage Vgp of the second PMOS transistor MP12 becomes equal to the output voltage VOUT, and the second PMOS transistor MP12 is turned off.

  Therefore, it is possible to prevent a current flowing backward from the output terminal OUT toward the power supply line LVCC via the first PMOS transistor MP11 and the second PMOS transistor MP12.

  At this time, the fourth PMOS transistor MP14 is also turned off, so that the back gates of the first PMOS transistor MP11, the second PMOS transistor MP12, and the third PMOS transistor MP13 are in a floating state. Thereby, the leakage current flowing from the output terminal OUT into the power supply line LVCC via the substrate can also be reduced.

3. Third state VOUT <VL
At this time, since the gate-source voltage of the third NMOS transistor MN13 becomes larger than the threshold voltage VTH, the third NMOS transistor MN13 is turned on. As a result, the drain voltage of the third NMOS transistor MN13, that is, the gate voltage Vgn of the second NMOS transistor MN12 becomes equal to the output voltage VOUT, and the second NMOS transistor MN12 is turned off.
Accordingly, it is possible to prevent a current flowing backward from the output terminal OUT toward the ground line LVCC via the first NMOS transistor MN11 and the second NMOS transistor MN12.

  At this time, the fourth NMOS transistor MN14 is also turned off, so that the back gates of the first NMOS transistor MN11, the second NMOS transistor MN12, and the third NMOS transistor MN13 are in a floating state. As a result, a leakage current flowing from the output terminal OUT to the ground line LGND via the substrate can also be reduced.

  The above is the operation of the driver circuit 10.

  According to the driver circuit 10, in the first state, the second PMOS transistor MP12 and the second NMOS transistor MN12 are turned on, so that their voltage drop can be substantially ignored. Therefore, it is possible to reduce the influence of the backflow preventing diode which is a problem in the driver circuit 10r of FIG. Thereby, the amplitude of the output voltage VOUT can be increased under the condition of the same power supply voltage VCC. Alternatively, the power supply voltage VCC required to obtain the same amplitude can be lowered, so that power consumption can be reduced.

  In the second state or the third state, the second PMOS transistor MP12 and the second NMOS transistor MN12 are turned off, so that a backflow current can be prevented.

  Furthermore, the symmetry of the circuit viewed from the output terminal OUT can be improved as compared with FIG.

Further, in the second state, the fourth PMOS transistor MP14 causes the back gates of the first PMOS transistor MP11, the second PMOS transistor MP12, and the third PMOS transistor MP13 to be in a floating state, thereby reducing a leakage current passing through the substrate.
Similarly, in the third state, the fourth NMOS transistor MN14 causes the back gates of the first NMOS transistor MN11, the second NMOS transistor MN12, and the third NMOS transistor MN13 to be in a floating state, thereby reducing the leakage current passing through the substrate.

Further, by configuring the first bias circuit 20 with the fifth PMOS transistor MP15 and the first current source CS1, the threshold VH at which the second PMOS transistor MP12 is turned off can be made equal to the power supply voltage VCC.
Similarly, by configuring the second bias circuit 30 with the fifth NMOS transistor MN15 and the second current source CS2, the threshold VL at which the second NMOS transistor MN12 is turned off can be made equal to the power supply voltage VGND.

  Next, the application of the driver circuit 10 will be described. The driver circuit 10 of FIG. 2 can be used for a differential transmitter as a pair, as shown in FIG.

  Finally, the use of the differential transmitter 2 will be described. 4A and 4B are block diagrams of an electronic device and an industrial device including the differential transmitter according to the embodiment.

The electronic device 500 in FIG. 4A includes an interface that conforms to the LVDS standard or the DisplayPort standard. For example, the electronic device 500 is a notebook PC (Personal Computer), a smartphone, or a tablet terminal that includes a liquid crystal display.
The electronic device 500 includes a liquid crystal panel 502, a driver IC 504, a timing controller IC 506, and an image processing IC 508. The image processing IC 508 generates image data to be displayed on the liquid crystal panel 502 and transmits it to the timing controller IC 506. The timing controller IC 506 receives the image data from the image processing IC 508, optimizes the timing for each line and each pixel with respect to the liquid crystal panel 502, and transmits it to the driver IC 504. The driver IC 504 drives the liquid crystal panel 502 based on the image data from the timing controller IC 506.
In such an electronic device 500, differential signals are used for data transmission between the image processing IC 508 and the timing controller IC 506 and between the timing controller IC 506 and the driver IC 504. Therefore, the differential transmitter 2 according to the embodiment can be mounted on the transmission interface of the image processing IC 508 and the transmission interface of the timing controller IC 506.

  4B constitutes a network system 600 formed in a relatively wide range such as a factory. The network system 600 includes a plurality of industrial devices 602 and a host device 604. The industrial device 602 and the host device 604 comply with the RS-422 and RS-485 standards, and they have a transmission / reception circuit for transmitting / receiving data to / from each other. The type of the industrial device 602 is not particularly limited.

  The differential transmitter 2 according to the embodiment can be suitably used for such a network system 600. The host device 604 includes the differential transmitter 2 according to the embodiment. The industrial device 602 includes the differential receiver 606 according to the embodiment. The plurality of differential receivers 606 and the differential transmitter 2 are connected via a common bus 608.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
FIG. 5 is a circuit diagram of the driver circuit 10a according to the first modification.
The driver circuit 10a further includes a first resistor R1 and a second resistor R2 in addition to the driver circuit 10 of FIG. The first resistor R1 is provided between the power supply line LVCC and the source of the second PMOS transistor MP12. The second resistor R2 is provided between the source of the second NMOS transistor MN12 and the ground line LGND.

  In the driver circuit 10 of FIG. 2, the circuit operation and the amplitude of the output voltage may be affected by the temperature dependence of the ON resistance of the MOS transistor and the manufacturing variation of the MOS transistor. On the other hand, according to the driver circuit 10a of FIG. 5, the temperature dependency of the MOS transistor is canceled by the first resistor R1 and the second resistor R2, and / or the variation of the output amplitude due to the manufacturing variation of the MOS transistor is suppressed. it can.

FIG. 6 is a block diagram of a differential transmitter 2a including the driver circuit 10a of FIG. The differential transmitter 2a includes two driver circuits 10a in FIG. 5 as a pair. The output voltage VOUT of one driver circuit 10ap is set as a positive signal S _{OUT +} of the differential signal, and the output voltage VOUT of the other driver circuit 10an is set. The negative signal S _OUT− of the differential signal can be output. The source (COMP terminal) of the second PMOS transistor MP12 of one driver circuit 10ap and the source (COMP terminal) of the second PMOS transistor MP12 of the other driver circuit 10an are connected in common. The source (COMN terminal) of the second NMOS transistor MN12 of one driver circuit 10ap and the source (COMN terminal) of the second NMOS transistor MN12 of the other driver circuit 10an are connected in common.

According to the differential transmitter 2a, by providing the first resistor R1 and the second resistor R2, the temperature dependence of the on-resistance of the MOS transistor is canceled and / or the output amplitude varies due to manufacturing variations of the MOS transistor. Can be suppressed.
In addition, by connecting the COMP terminals of the two driver circuits 10a in common and connecting the COMN terminals in common, the first PMOS transistor MP11 and the first NMOS transistor MN11 of one driver circuit 10ap are connected to each other. The first PMOS transistor MP11 and the first NMOS transistor MN11 of the other driver circuit 10an can be operated as a differential pair for branching current from the common resistors R1 and R2, thereby adjusting the output waveform. .

(Second modification)
In the embodiment, the case where the driver circuit 10 is used for a differential transmitter has been described. However, the present invention is not limited to this, and can be applied to a transmitter that transmits a signal in a single end.

(Third Modification)
In the embodiment, the first bias circuit 20 biases the gate voltage of the third PMOS transistor MP13 to VCC-VTH, and the second bias circuit 30 biases the gate voltage of the third NMOS transistor MN13 to VGND + VTH. However, the present invention is not limited to this. For example, the first bias circuit 20 may bias the gate voltage of the third PMOS transistor MP13 to the power supply voltage VCC or other voltage. That is, the first bias circuit 20 may determine the level of the gate voltage of the third PMOS transistor MP13 so that the desired first threshold value VH is obtained.
Similarly, the second bias circuit 30 may bias the gate voltage of the third NMOS transistor MN13 to the ground voltage VGND or other voltage. That is, the second bias circuit 30 may determine the level of the gate voltage of the third NMOS transistor MN13 so that the desired second threshold value VL is obtained.

(Fourth modification)
In the embodiment, the back gates of the first PMOS transistor MP11, the second PMOS transistor MP12, and the third PMOS transistor MP13 are controlled to be in a floating state by the fourth PMOS transistor MP14, and the first NMOS transistor MN11 and the second NMOS are controlled by the fourth NMOS transistor MN14. Although the back gates of the transistor MN12 and the third NMOS transistor MN13 are controlled to be in a floating state, the present invention is not limited to this. If the leakage current via the substrate does not matter so much, the back gate of the PMOS transistor may be connected to the power supply line, and the back gate of the NMOS transistor may be connected to the ground line.

(Fifth modification)
The third current source CS3 and the fourth current source CS4 may be replaced with other elements such as resistors. That is, when the third PMOS transistor MP13 is off, its drain voltage is pulled down, and when it is on, it may be a path of current flowing through the third PMOS transistor MP13. Similarly, when the third NMOS transistor MN13 is off, its drain voltage is pulled up, and when it is on, it may be a path for a current flowing through the third NMOS transistor MN13.
Similarly, the first current source CS1 and the second current source CS2 may be replaced with another element such as a resistor.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 2 ... Differential transmitter, 10 ... Driver circuit, MP11 ... 1st PMOS transistor, MP12 ... 2nd PMOS transistor, MP13 ... 3rd PMOS transistor, MP14 ... 4th PMOS transistor, MP15 ... 5th PMOS transistor, MN11 ... 1st NMOS transistor, MN12 ... 1st 2 NMOS transistors, MN13... 3rd NMOS transistor, MN14... 4th NMOS transistor, MN15... 5th NMOS transistor, 20... 1st bias circuit, 30 ... 2nd bias circuit, CS1 ... 1st current source, CS2 ... 2nd current source, CS3 ... third current source, CS4 ... fourth current source, R1 ... first resistor, R2 ... second resistor, 500 ... electronic device, 502 ... liquid crystal panel, 504 ... driver IC, 506 ... timing controller IC, 508 The image processing IC, 600 ... network system, 602 ... industrial equipment, 604 ... host device, 606 ... differential receiver, 608 ... bus.

Claims (11)

A driver circuit for generating an output voltage at a level corresponding to a first control signal and a second control signal at an output terminal;
A first PMOS transistor having a drain connected to the output terminal and a gate to which the first control signal is input;
A second PMOS transistor having a drain connected to a source of the first PMOS transistor and a source connected to a power supply line;
A first NMOS transistor having a drain connected to the output terminal and a gate to which the second control signal is input;
A second NMOS transistor having a drain connected to a source of the first NMOS transistor and a source connected to a ground line;
A third PMOS transistor having a source connected to the output terminal and a drain connected to the gate of the second PMOS transistor;
A third NMOS transistor having a source connected to the output terminal and a drain connected to the gate of the second NMOS transistor;
A first bias circuit for biasing the gate of the third PMOS transistor so that the third PMOS transistor is turned on when the output voltage is higher than a predetermined first threshold;
A second bias circuit for biasing the gate of the third NMOS transistor so that the third NMOS transistor is turned on when the output voltage is lower than a predetermined second threshold;
A driver circuit comprising: A fourth PMOS transistor having a source connected to the power supply line, a drain connected to the back gates of the first PMOS transistor, the second PMOS transistor, and the third PMOS transistor, and a gate connected to the drain of the third PMOS transistor;
A fourth NMOS transistor having a source connected to the ground line, a drain connected to the back gates of the first NMOS transistor, the second NMOS transistor, and the third NMOS transistor, and a gate connected to the drain of the third NMOS transistor;
The driver circuit according to claim 1, further comprising: The first bias circuit includes:
A fifth PMOS transistor having a source connected to the power supply line and a drain and gate connected to the gate of the third PMOS transistor;
A first current source connected to a drain of the fifth PMOS transistor;
The driver circuit according to claim 1, further comprising: The second bias circuit includes:
A fifth NMOS transistor having a source connected to the ground line and a drain and gate connected to the gate of the third NMOS transistor;
A second current source connected to the drain of the fifth NMOS transistor;
The driver circuit according to claim 1, comprising: A third current source connected to the drain of the third PMOS transistor;
A fourth current source connected to the drain of the third NMOS transistor;
The driver circuit according to claim 1, further comprising: A first resistor provided between the power line and the source of the second PMOS transistor;
A second resistor provided between the source of the second NMOS transistor and the ground line;
The driver circuit according to claim 1, further comprising:   7. The driver circuit according to claim 1, wherein the first threshold value is set near a power supply voltage, and the second threshold value is set near a ground potential.   A driver circuit according to any one of claims 1 to 7 is provided in two pairs, the output voltage of one driver circuit being a positive signal of a differential signal, and the output voltage of the other driver circuit being a negative signal of a differential signal As a differential transmitter configured to be output as. 8. The driver circuit according to claim 7, comprising two pairs of driver circuits, wherein the output voltage of one driver circuit can be output as a positive signal of a differential signal and the output voltage of the other driver circuit can be output as a negative signal of a differential signal And
The source of the second PMOS transistor of one driver circuit and the source of the second PMOS transistor of the other driver circuit are connected in common,
A differential transmitter characterized in that a source of the second NMOS transistor of one driver circuit and a source of the second NMOS transistor of the other driver circuit are connected in common.   An industrial device comprising the differential transmitter according to claim 8.   An electronic apparatus comprising the differential transmitter according to claim 8.

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