JPH09162653A - High frequency differential output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the occurrence of the waveform distortion of an output signal by adding an inductive circuit between the sources of FETs constructing a constant current circuit and a power potential and then compensating the change of capacitive impedance that is caused between the FET source and signal output terminals. SOLUTION: A MES FET Q3 is provided in series between the power potential Vss and the common source of both MES FET Q1 and Q2 which construct a differential pair with both sources connected in common to each other. In such a constitution, a constant current circuit is obtained. Then the signals having prescribed impedances are taken out of the drains of both FET Q1 and Q2 and sent to the output terminals 21 and 22. An inductive circuit 23 consisting of an inductance element Lx is added between the source of the EFT Q3 and the potential Vss. Thus the change of the capacitive impedance that is caused by the parasitic capacitance Cx generated between the terminals 21 and 22 and the source of the FET Q3 can be compensated by the inductive impedance of the circuit 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high frequency differential output circuit, and more particularly to a technology effective when applied to a high frequency differential output circuit constructed by using MES field effect transistors. The present invention relates to a technology effectively used for a communication transceiver.

[0002]

2. Description of the Related Art MES (Metal Semico) such as MOS transistor and GaAs field effect transistor.
A high-frequency differential output circuit configured by using a field effect transistor is used by being integrated and formed in a high-speed communication IC (semiconductor integrated circuit device) for performing, for example, optical fiber communication (for example, Nikkei BP). Published "Nikkei Electronics February 27, 1995 issue.
(No. 630) ”pp. 157-165: Special ISS
See CC95).

In this high-frequency differential output circuit, load resistances are interposed in series between the respective drains of the first and second field effect transistors which form a differential pair with their sources connected in common and one power supply potential. In addition, by interposing a constant current circuit of the third field effect transistor in series between the common source of the pair of field effect transistors and the power supply potential of the other, the first and second field effect transistors are connected in series. A signal output terminal having a predetermined impedance characteristic is taken out from each drain, and the signal output terminal is connected to a load having a predetermined terminating impedance via a transmission line wiring having a predetermined characteristic impedance.

The high-frequency differential output circuit is formed by being incorporated in a communication IC, and circuit wiring within the IC is considered in consideration of transmitting a very high-speed signal in GHz unit. , The optimization was performed in the direction as short as possible and with less detours.

[0005]

However, it has been clarified by the present inventors that the above-described technology has the following problems.

That is, as the field effect transistor used in the above-mentioned conventional high frequency differential output circuit, a high output type one having a large element size is used in order to secure the power driving capability required as the output circuit. In this type of field effect transistor, the gate-drain capacitance (Cgd) and the gate-source capacitance (Cgs) are inevitably larger than those of a normal small-signal field-effect transistor.

Therefore, a large parasitic capacitance (Cx) is interposed in parallel between the signal output terminal taken out from each drain of the first and second field effect transistors and the other power supply potential. This parasitic capacitance (Cx) does not have a significant effect when the frequency range of the output signal is relatively low, but as the frequency range of the output signal increases, the impedance characteristic at the output terminal is greatly affected. Come to do.

That is, when the frequency region of the output signal becomes high, the output terminal cannot maintain the predetermined impedance characteristic set in advance by the drain load resistance or the like, and the impedance matching with the transmission line and the load deteriorates. To do. That is, impedance mismatch (mismatch) occurs. When impedance mismatch occurs, the amount of reflection components to the output terminal increases, which causes a problem that the waveform of the output signal is distorted.

An object of the present invention is to ensure impedance matching between the output terminals of the high frequency differential output circuit, the transmission line and the load, and prevent the waveform distortion of the output signal. To provide.

The above and other objects and characteristics of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, drain load resistors are respectively provided in series between the respective drains of the first and second field effect transistors having their sources connected in common to form a differential pair and one power supply potential, and By interposing a constant current circuit of the third field effect transistor in series between the common source of the field effect transistor and the other power supply potential, a predetermined current is supplied from each drain of the first and second field effect transistors. In a high frequency differential output circuit in which a signal output terminal having an impedance characteristic is taken out, an inductive circuit is interposed between the source of the third field effect transistor and the other power supply potential, and the inductive impedance of this inductive circuit is Due to the parasitic capacitance between the signal output terminal and the source of the third field effect transistor. To compensate for the change in impedance,
That is.

According to the above-mentioned means, even if the parasitic capacitance due to the inter-electrode capacitance (Cgd, Cgs) of each field effect transistor is present in the output terminal, the influence of the parasitic capacitance on the output impedance characteristic is significantly reduced. be able to.

Thus, the object of ensuring the impedance matching between the output terminals of the high frequency differential output circuit, the transmission line and the load, and preventing the waveform distortion of the output signal is achieved. It

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

In the drawings, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an embodiment of a high frequency differential output circuit to which the technique of the present invention is applied.

The high frequency differential output circuit 2 shown in the figure constitutes a transmitting portion of a high speed communication transceiver, and is formed integrally with the pre-stage circuit 1 and the like on the same GaAs semiconductor substrate.

In the figure, the high frequency differential output circuit 2 is
First and second MES field-effect transistors Q1 and Q2 having sources connected in common to form a differential pair, and respective drains of the pair of field-effect transistors Q1 and Q2 and one power supply potential GND in series, respectively. Drain resistances Ro, Ro interposed therebetween, the common source of the pair of field effect transistors Q1, Q2, and the other power supply potential Vss.
A third ME that forms a constant current circuit by interposing in series between the two
S field effect transistor Q3, and first and second
The signal output terminals 21 and 22 having predetermined impedance characteristics are taken out from the respective drains of the field effect transistors Q1 and Q2.

Further, a third field effect transistor Q3
Between the source and the other power supply potential Vss, an inductive circuit 23 formed by an inductance element Lx is interposed. Due to the inductive impedance (XL) of the inductive circuit 23, the signal output terminals 21, 23 and the third The change in the capacitive impedance (XL) caused by the parasitic capacitance Cx between the source and the source of the field effect transistor Q3 is compensated.

Next, the operation will be described.

FIG. 2 shows an equivalent circuit between the output terminals 21 and 22 of the high frequency differential output circuit 2 shown in FIG. 1 and the load circuit 3, and FIG. 2A shows the technique of the present invention. Shows an equivalent circuit in the case where is applied, and (B) shows an equivalent circuit in the case where the technique of the present invention is not applied. Note that this equivalent circuit focuses on high-frequency characteristics, and the two power supply potentials GND and Vss are both treated as the same reference potential.

In FIG. 1 and FIG. 2, the output terminals 21,
Reference numeral 22 denotes a predetermined terminating impedance Ri, via the transmission line wirings L1, L2 having a predetermined characteristic impedance.
It is adapted to be connected to the load circuit 3 having Ri. The output signals Va and Vb of the high frequency differential output circuit 2 are given to the load circuit 3 from the terminals 21 and 22 through the transmission line wirings L1 and L2. As the load circuit 3, for example, an optical drive circuit for converting an electric signal into an optical signal and sending it to an optical fiber transmission line is connected.

The output terminals 21 and 22 have gate-drain capacitances (C) of the field effect transistors Q1, Q2 and Q3.
gd) and the parasitic capacitance Cx due to the gate-source capacitance (Cgs) are equivalently interposed in parallel. This parasitic capacitance Cx is inevitably large in an output field effect transistor having a large element size, that is, a gate width.

The output terminals 21 and 22 have the parasitic capacitance Cx.
The capacitive impedance (XC) due to V is intervened in parallel, and the parallel impedance (XC) becomes larger as the parasitic capacitance Cx becomes larger or the output signal V
The higher the frequencies of a and Vb, the lower the frequencies. Therefore, in the high-frequency differential output circuit using the output field-effect transistor having a large gate width, the output terminals 21, 2 thereof are increased as the frequencies of the output signals Va, Vb are increased.
The capacitive impedance interposed in parallel with 2 is reduced.

Here, if the technique of the present invention is not applied, as shown in FIG.
Is directly bypassed to the reference potential (Vss) by the capacitive impedance XC due to the parasitic capacitance Cx. Therefore, the impedance characteristics at the output terminals 21, 22 are directly affected by the change in the capacitive impedance XC, and the transmission line wiring L1,
It becomes impossible to maintain a good impedance matching state with respect to L2 and the load circuit 3. As a result, a reflected wave (Vr) is generated due to impedance mismatch, and waveform distortion occurs in the output signals Va and Vb.

However, when the technique of the present invention is applied, as shown in FIG. 2A, induction by the inductance element Lx is provided between the capacitive impedance (XC) and the reference potential (Vss). Sexual impedance (XL) is interposed in series. This inductive impedance (XL)
Is higher at higher frequencies, as opposed to capacitive impedance (XC). Therefore, even if the capacitive impedance (XC) interposed in parallel to the output terminals 21 and 22 changes, the inductive impedance (XL) changes in the direction of compensating for this change. As a result, the influence of the impedance characteristics of the output terminals 21 and 22 can be significantly reduced, and a good impedance matching state with the transmission line wirings L1 and L2 and the load circuit 3 can be ensured. In this way, waveform distortion of the output signals Va and Vb due to impedance mismatch can be prevented.

FIG. 3 is an abbreviated plan view showing a structural example of the inductance element Lx forming the inductive circuit 23.

The inductance element Lx, together with the above-mentioned field effect transistors Q1, Q2, Q3, etc., can be integrally formed on the same semiconductor substrate by multilayer wiring.
In FIG. 3, 231 is a first layer wiring, 232 is a second layer wiring, 233 is an interlayer wiring section for connecting between the first layer and the second layer, 24 is a terminal pad section, and 25 is a bonding wire. Is.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say.

In the above description, Ga, which is the field of application of the invention made by the present inventor, was the background.
Although the case where the present invention is applied to the As semiconductor integrated circuit device has been described, the present invention is not limited to this, and the present invention can be applied to, for example, a MOS semiconductor integrated circuit device using a silicon semiconductor substrate.

[0032]

The following is a brief description of an outline of typical inventions among the inventions disclosed in the present application.

That is, the effect of ensuring the impedance matching between the output terminals of the high-frequency differential output circuit and the transmission line and the load and preventing the waveform distortion of the output signal can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an embodiment of a high frequency differential output circuit to which the technique of the present invention is applied.

FIG. 2 is an equivalent circuit diagram showing a portion from an output terminal of the high frequency differential output circuit shown in FIG. 1 to a load circuit.

FIG. 3 is an abbreviated plan view showing a configuration example of an inductance element forming an inductive circuit.

[Explanation of symbols]

 1 pre-stage circuit 2 high frequency differential output circuit 21, 22 output terminal 23 inductive circuit 3 load circuit Q1, Q2, Q3 MES field effect transistor GND one power supply potential Vss other power supply potential Ro drain load resistance Cx parasitic capacitance XC capacitive Impedance Lx Inductance element XL Inductive impedance L1, L2 Transmission line wiring 231 First layer wiring 232 Second layer wiring 233 Interlayer wiring 24 Terminal pad section 25 Bonding wire

Claims (4)

[Claims] 1. A first and a second field effect transistor having sources connected in common to form a differential pair, and a series connection between each drain of the first and second field effect transistors and one power supply potential. And a third field effect transistor forming a constant current circuit by being interposed in series between a common source of the pair of field effect transistors and the other power supply potential. A high-frequency differential output circuit in which a signal output terminal having a predetermined impedance characteristic is taken out from each drain of the second field-effect transistor, the inductive characteristic being provided between the source of the third field-effect transistor and the other power supply potential. By interposing the circuit, the change in the capacitive impedance due to the parasitic capacitance between the signal output terminal and the source of the third field effect transistor is compensated. A high-frequency differential output circuit characterized in that 2. The high frequency differential output circuit according to claim 1, wherein an inductance element is interposed between the source of the third field effect transistor and the other power supply potential as the inductive circuit. 3. The inductive circuit and the field effect transistor are integrated and formed on the same semiconductor substrate.
Alternatively, the high frequency differential output circuit according to item 2. 4. The field effect transistor forming a differential pair is M
The high frequency differential output circuit according to claim 1, wherein the high frequency differential output circuit is an ES field effect transistor.