JP3147642B2 - Electronic devices, integrated circuits and termination devices - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to electronic devices for transmitting signals, and to integrated circuits and terminating devices used in such electronic devices.

[0002]

2. Description of the Related Art Conventionally, as an electronic device for transmitting a small amplitude signal, for example, an electronic device as shown in FIG. 34 is known.

In the figure, 1 is a microprocessor, 2 ₁ ,
2 ₂ and 2 _n are SDRAMs (Synchronous DRAM [dynami
c random access memory]), 3 is a bus line forming a signal transmission path.

At present, a microprocessor 1 and an SDRA
Transmission of signals to and from the M2 ₁ to 2 _n is being performed by the number 10MHz frequency, the transmission of the signal at frequencies above 100MHz is requested.

FIG. 35 is a circuit diagram showing an example of a conventional interface circuit and bus system applied to such an electronic device.

In the figure, reference numeral 5 denotes a microprocessor;
Is a signal input / output terminal used for input / output of the signal DQ, 7 is a reference voltage input terminal for taking in the reference voltage Vref, 8
Is an input circuit composed of a differential amplifier circuit.

Further, 9 is a VCC power supply line for supplying a power supply voltage VCC (3.3 V), and 10 is a power supply voltage VSS (0 V).
, A body circuit, and a push-pull type output circuit.

In this push-pull type output circuit 12, reference numeral 13 denotes an enhancement type pMOS transistor serving as a pull-up element, and reference numeral 14 denotes an enhancement type nMOS transistor serving as a pull-down element.

Reference numeral 15 denotes a bus line forming a signal transmission path;
Reference numeral 6 denotes a termination voltage source that generates a termination voltage VTT (1.65 V), 17 denotes a VTT voltage line that supplies the termination voltage VTT, 1
Reference numerals 8 and 19 denote termination resistors having a resistance value of 50Ω.

Reference numeral 20 denotes an SDRAM; 21, a signal input / output terminal used for input / output of a signal DQ; 22, a reference voltage input terminal for receiving a reference voltage Vref;
Is an input circuit comprising a differential amplifier circuit, and 24 is a push-pull type output circuit.

In this example, the termination voltage VTT output from the termination voltage source 16 is used as the reference voltage Vref and the reference voltage input terminal 7 of the microprocessor 5 and the SDRAM
The reference voltage is supplied to a reference voltage input terminal 22.

In this interface circuit and bus system, a signal DQ is transmitted between the microprocessor 5 and the SDRAM 20 with the intermediate voltage being the reference voltage Vref = 1.65 V and the amplitude being, for example, ± 400 mV.

Here, for example, the microprocessor 5
, When the signal DQ is transmitted to the SDRAM 20, when the pMOS transistor 13 is turned off (non-conducting) and when the nMOS transistor 14 is turned on (conducting), the signal DQ is set at the L level (low level). .

On the other hand, the pMOS transistor 13
= ON and nMOS transistor 14 = OFF, the signal DQ is set to H level (high level).

Therefore, when the output circuit 12 outputs the L level, a current flows from the termination voltage source 16 to the load side, but when the output circuit 12 outputs the H level, the termination voltage source Current will flow into the 16.

Here, as the terminating voltage source 16, a voltage source such as a switching regulator or a series regulator is generally used. However, these voltage sources have a configuration that is expected to allow a current to flow from the load side. If the current flows into these voltage sources from the load side, the termination voltage VTT fluctuates.

Therefore, a bus system as shown in FIG. 36 is actually used. In the figure, 25 is the power supply voltage VC
C is a power supply voltage generating circuit, 26 is a VCC power supply line,
27 is a VSS power supply line.

Reference numerals 28 to 31 denote terminating resistors having a resistance value of 100Ω, 32 and 33 are voltage dividing resistors for dividing the power supply voltage VCC to obtain a reference voltage Vref, and 34 and 35 are power supply voltages of the microprocessor 5. Input terminal.

This bus system is composed of terminating resistors 28 and 29
And the substantial termination resistance value of the termination portion composed of the termination resistors 30 and 31 is set to 50Ω.

[0020]

However, in this bus system, the terminating resistors 28 and 29 and the terminating resistor 3 are used.
0 and 31 are the VCC power supply line 26 and the VSS power supply line 2, respectively.
7 are connected in series with each other, even when a signal is not transmitted, a current flows through these terminating resistors 28 to 31, which causes an increase in power consumption. there were.

On the other hand, by increasing the resistance value of the voltage dividing resistors 32, 33, the voltage dividing resistors 32, 3
However, if the accuracy of the voltage dividing resistors 32 and 33 is not high, the reference voltage Vref may not coincide with the termination voltage VTT.

Here, the reference voltage Vref and the termination voltage VTT
Is the DC offset voltage of the input signal, which reduces the operating margin of the input signal on the H level side or the L level side.

Therefore, as the voltage dividing resistors 32 and 33,
It is necessary to use a high-precision resistor, but in this case, there is a problem that the price is increased.

[0024] In view of the above, the present invention is an electronic device for transmitting a signal, which stabilizes a termination voltage and reduces power consumption.
An electronic device that matches the reference voltage with the termination voltage so that an offset voltage is not generated in the input signal and a sufficient operation margin of the input signal can be secured. An object is to provide a suitable integrated circuit and a termination device.

[0025]

[Means for Solving the Problems]

FIG. 1 is a circuit diagram showing the principle of an electronic device according to a first aspect of the present invention. In FIG. 1, reference numeral 37 denotes a voltage generating circuit.
8 is a voltage generating circuit for generating a voltage V1, 39 is a voltage V2
, 40 and 41 are voltage output terminals.

The voltage generating circuit 37 connects a voltage generating circuit 38 for generating a voltage V1 and a voltage generating circuit 39 for generating a voltage V2 in series.
1 + V2, and outputs the voltage V2 to the voltage output terminal 41.

A power supply line 42 supplies the voltage V1 + V2 output from the voltage generation circuit 37 as a power supply voltage.
43 is a termination voltage line for supplying the voltage V2 output from the voltage generation circuit 37 as the termination voltage VTT.

Reference numeral 44 denotes an integrated circuit for inputting / outputting a signal; 45, a signal input / output terminal for inputting / outputting a signal; 46, a power supply voltage input terminal for receiving a voltage V1 + V2 as a power supply voltage; Voltage V1 + V2
Is a push-pull type output circuit.

In the push-pull type output circuit 48, reference numeral 49 denotes a p-channel insulated gate field effect transistor serving as a pull-up element, and reference numeral 50 denotes an n-channel insulated gate field effect transistor serving as a pull-down element.

Reference numeral 51 denotes a bus line serving as a signal transmission path;
2 is a terminating resistor for terminating the bus line 51.

Reference numeral 53 denotes an integrated circuit for inputting / outputting signals, reference numeral 54 denotes a signal input / output terminal for inputting / outputting signals, and reference numeral 55 denotes a voltage V2 output from the voltage generating circuit 37, which is supplied as a reference voltage Vref. Reference voltage input terminals, 5
6 is an input circuit.

FIG. 2 is a diagram for explaining the principle of the second invention in the present invention. In FIG. 2, reference numeral 58 denotes a voltage generating circuit for generating a voltage V3, and 59 denotes a power supply voltage. Power supply line.

Reference numeral 60 denotes a voltage generating circuit for generating the voltage V4, 61 denotes a power supply voltage input terminal for receiving the voltage V3, 62 denotes a power supply line, and 63 denotes an operational amplifier (operational amplifier).

Reference numerals 64 and 65 denote voltage dividing resistors for dividing the voltage V3, 66 denotes a voltage output terminal from which the voltage V4 is output, and 6
Reference numeral 7 denotes a termination voltage line for supplying the voltage V4 output from the voltage generation circuit 60 as the termination voltage VTT.

The voltage generating circuit 60 supplies a voltage obtained by dividing the voltage V3 by the voltage dividing resistors 64 and 65 to a first input terminal of the operational amplifier 63, and outputs an output of the operational amplifier 63 to a second input terminal of the operational amplifier 63. By feeding back to the input terminal, the power supply voltage V3 is divided by the resistors 64 and 65 to the second input terminal, that is, the voltage output terminal 66, and a voltage V4 equal to the voltage is output.

Reference numeral 68 denotes an integrated circuit for inputting / outputting signals, reference numeral 69 denotes a signal input / output terminal for inputting / outputting signals, reference numeral 70 denotes a power supply voltage input terminal for receiving a voltage V3 as a power supply voltage, and reference numeral 71 denotes a power supply voltage. A power supply line for supplying the voltage V3 is provided, and a push-pull type output circuit 72 is provided.

In the push-pull type output circuit 72, reference numeral 73 denotes a p-channel insulated gate field effect transistor serving as a pull-up element, and 74 denotes an n-channel insulated gate field effect transistor serving as a pull-down element.

Reference numeral 75 denotes a bus line forming a signal transmission path;
6 is a terminating resistor for terminating the bus line 75.

Reference numeral 77 denotes an integrated circuit for inputting / outputting a signal. Reference numeral 78 denotes a signal input / output terminal for inputting / outputting a signal. Reference numeral 79 denotes a voltage V4 output from the voltage generating circuit 60, which is supplied as a reference voltage Vref. Reference voltage input terminal, 8
0 is an input circuit.

[0040]

[Action]

First Invention FIG. 1 In the first invention, a voltage V is applied to the output circuit 48 as a power supply voltage.
Since 1 + V2 is supplied and the voltage V2 is supplied to the terminating resistor 52 as the terminating voltage VTT, it is possible to transmit a signal whose intermediate voltage is V2. Note that the voltage V1 =
With the voltage V2, the termination voltage VTT can be set to 1/2 of the voltage V1 + V2.

Here, when the p-channel insulated gate field effect transistor 49 is turned off and the n-channel insulated gate field effect transistor 50 is turned on, the output of the output circuit 48 becomes L level.

In this case, the voltage generating circuit 39 → the terminating voltage line 43 → the terminating resistor 52 → the bus line 51 → the n-channel insulated gate field effect transistor 50 → the ground → the voltage generating circuit 3
The current i ₀ flows through the closed circuit No. 9 and the voltage of the voltage output terminal 41 is maintained at V2.

On the other hand, when the p-channel insulated gate field effect transistor 49 is turned on and the n-channel insulated gate field effect transistor 50 is turned off, the output of the output circuit 48 becomes H level.

In this case, voltage generation circuit 38 → power supply line 42 → p-channel insulated gate field effect transistor 4
9 → a bus line 51 → a terminating resistor 52 → a current i ₁ flows through a closed circuit consisting of a voltage generating circuit 38, and the voltage of the voltage output terminal 41 is V
Maintained at 2.

As described above, according to the first aspect, the voltage generating circuit 37 is configured by connecting the voltage generating circuits 38 and 39 in series. Even if a current is input, the voltage of the voltage output terminal 41 can be maintained at V2, and the stability of the termination voltage VTT = V2 can be ensured.

According to the first aspect of the present invention, when no signal is transmitted through the bus line 51, no current flows through the terminating resistor 52, so that power consumption can be reduced.

In the first embodiment, the termination voltage VTT can be used as the reference voltage Vref of the integrated circuits 44 and 53. Therefore, the reference voltage Vref and the termination voltage VT can be used.
T can be matched to prevent an offset voltage from being generated in the input signal, and a sufficient operation margin of the input signal can be secured.

Second Invention FIG. 2 In the second invention, if the resistance value of the resistor ₆₄ is R ₆₄ and the resistance value of the resistor 65 is R ₆₅ , the termination voltage VTT is V3 × R ₆₅
/ (R ₆₄ + R ₆₅ ), and transmission of a small-amplitude signal using the terminal voltage VTT as an intermediate voltage can be performed. In addition,
If R ₆₄ = R ₆₅ , the termination voltage VTT can be set to V3 / 2.

Here, when the p-channel insulated gate field effect transistor 73 is turned off and the n-channel insulated gate field effect transistor 74 is turned on, the output of the output circuit 72 becomes L level.

In this case, the operational amplifier 63 → termination voltage line 6
7 → Terminal resistor 76 → Bus line 75 → N-channel insulated gate field effect transistor 74 → Ground → Voltage generating circuit 58
The current i ₃ flows through a closed circuit composed of the power supply lines 59 and 62 → the operational amplifier 63.

On the other hand, when the p-channel insulated gate field effect transistor 73 is turned on and the n-channel insulated gate field effect transistor 74 is turned off, the output of the output circuit 72 goes high.

In this case, the voltage generation circuit 58 → the power supply line 5
9, 71 → p-channel insulated gate field effect transistor 73 → bus line 75 → terminal resistor 76 → terminal voltage line 67 →
The current i ₄ flows through a closed circuit consisting of the operational amplifier 63 → ground → voltage generating circuit 58.

As described above, according to the second aspect, the voltage generation circuit 60 is configured to feedback-control the voltage V4 = termination voltage VTT using the operational amplifier 63. Whether the current is output or the current is input, the stability of the termination voltage VTT = V4 can be ensured.

According to the second aspect of the present invention, when the bus line 75 does not transmit a signal, no current flows through the terminating resistor 76, so that power consumption can be reduced.

In the second embodiment, the termination voltage VTT can be used as the reference voltage Vref of the integrated circuits 68 and 77, so that the reference voltage Vref and the termination voltage VT can be used.
T can be matched to prevent an offset voltage from being generated in the input signal, and a sufficient operation margin of the input signal can be secured.

[0056]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to ninth embodiments of the present invention will be described below with reference to FIGS. 3 to 33, taking an example in which the present invention is applied to an electronic device comprising a microprocessor and an SDRAM. I do.

First Embodiment FIG. 3 to FIG. 11 FIG. 3 is a circuit diagram showing a main part of a first embodiment of the present invention.
In the figure, reference numeral 83 denotes a voltage generation circuit, and 84 and 85 denote voltages V
Voltage generating circuits for generating 5 = 1.0 V, 86 and 87 are voltage output terminals.

This voltage generation circuit 83 is connected in series with voltage generation circuits 84 and 85 for generating a voltage V5, and a voltage 2 × V5 = a power supply voltage VCCQ is applied to a voltage output terminal 86.
2.0V, and outputs the termination voltage VTT to the voltage output terminal 87.
Output voltage V5 = 1.0V.

Reference numeral 88 denotes a VC for supplying the power supply voltage VCCQ = 2 × V5 output from the voltage generation circuit 83.
A CQ power supply line 89 is a termination voltage line for supplying the termination voltage VTT = V5 output from the voltage generation circuit 83.

Reference numeral 90 denotes a microprocessor;
Reference numeral 94 denotes an SDRAM for inputting / outputting 8-bit data DQ0 to DQ7, and reference numerals 95 to 99 denote data input / output terminals for inputting / outputting data DQ0.

Reference numerals 100 to 104 are reference voltage input terminals for receiving the reference voltage Vref. In the first embodiment, the termination voltage VTT is supplied to the microprocessor 90 and the SDRAMs 91 to 94 as the reference voltage Vref. It has a configuration.

Reference numerals 105 to 109 denote input circuits consisting of differential amplifier circuits provided for data DQ0.
Numerals 114 are push-pull type output circuits provided for data DQ0.

Reference numeral 115 denotes a bus line provided for the data DQ0, 116 and 117 denote terminating resistors for terminating the bus line 115, and the terminating resistor 116 has a resistance value of 5
The terminating resistor 117 has a resistance value of 30Ω.

Here, the microprocessor 90 and the SD
In the RAMs 91 to 94, the input / output circuits have the same circuit configuration, and FIG.
0 is shown.

In FIG. 4, reference numeral 119 denotes a power supply voltage VCC (3.3
V) is supplied to a VCC power supply terminal, and 120 is a power supply voltage V
VCCQ power supply terminal to which CCQ (2.0V) is supplied, 1
Reference numeral 21 denotes a VSS power supply terminal to which the ground voltage VSS (0 V) is supplied.

Reference numeral 122 denotes a VCC power supply line connected to the VCC power supply terminal 119, and 123 denotes a VCCQ power supply terminal 12.
A VCCQ power supply line connected to 0 and a VSS power supply line 124 connected to the VSS power supply terminal 121 are shown.

Reference numeral 125 denotes a main circuit to which the power supply voltage VCC is supplied, / DATA denotes data output from the main circuit 125, and / HZ denotes a control signal for controlling whether or not the output state is set to a high impedance state. .

Reference numeral 126 denotes an output control circuit to which the power supply voltage VCC is supplied, 127 denotes a NOR circuit, 128 denotes an inverter, and 129 denotes a NAND circuit.

Further, 130 is an output drive circuit (pre-driver) to which the power supply voltage VCCQ is supplied, 131 and 132 are CMOS type inverters, 133 and 134 are enhancement type pMOS transistors, 135 and 13
Reference numeral 6 denotes an enhancement type nMOS transistor.

In the output circuit 110, 137 is an enhancement type pMOS transistor serving as a pull-up element, and 138 is an enhancement type nMOS transistor serving as a pull-down element.

Here, the pMOS transistors 133, 1
The power supply voltage VC is applied to the N-well where 36 and 137 are formed.
In the case where C is supplied as a back bias voltage, when the power supply voltage VCC = 0 V and the power supply voltage VCCQ = 2 V at power-on or power-off, the sources of the pMOS transistors 133, 136, and 137 are A current may flow through the N well where the pMOS transistors 133, 136, and 137 are formed, and the pMOS transistors 133, 136, and 137 may be destroyed.

Therefore, in the first embodiment, pM
The power supply voltage VCCQ is supplied as a back bias voltage to the N well in which the OS transistors 133, 136, and 137 are formed. When the power supply is turned on or turned off, for example, the power supply voltage VCC = 0V and the power supply voltage VC
Even when CQ = 2V, p
The current is prevented from flowing from the sources of the MOS transistors 133, 136 and 137 to the N well where the pMOS transistors 133 and 137 are formed.
The S transistors 133, 136, and 137 are prevented from being destroyed.

Here, in the microprocessor 90, as shown in FIG. 5, when the control signal / HZ = L level, the output of the inverter 128 becomes H level and the output of the NOR circuit 127 becomes L level.

As a result, the pMOS transistor 133 =
ON, nMOS transistor 135 = OFF, output of inverter 131 = H level, and pMOS transistor 137 = OFF.

The output of the NAND circuit 129 is at H level, the pMOS transistor 134 is OFF, the nMOS transistor 136 is ON, and the output of the inverter 132 is L.
Level, and the nMOS transistor 138 is turned off.

Therefore, in this case, the output circuit 11
The output state of 0 is a high impedance state (Hi-Z).

On the other hand, as shown in FIG. 6, when control signal / HZ = H level, data / DATA
= H level, the output of the NOR circuit 127 becomes L level.

As a result, the pMOS transistor 133 =
ON, nMOS transistor 135 = OFF, output of inverter 131 = H level, and pMOS transistor 137 = OFF.

The output of the NAND circuit 129 is at L level, the pMOS transistor 134 is ON, the nMOS transistor 136 is OFF, and the output of the inverter 132 is H.
Level, and the nMOS transistor 138 = ON.

Therefore, in this case, the output circuit 11
The signal DQ0 output from 0 becomes L level.

As shown in FIG. 7, the control signal / HZ
= H level, when data / DATA = L level, the output of the NOR circuit 127 becomes H level.

As a result, the pMOS transistor 133 =
OFF, nMOS transistor 135 = ON, output of inverter 131 = L level, and pMOS transistor 137 = ON.

The output of the NAND circuit 129 is at H level, the pMOS transistor 134 is OFF, the nMOS transistor 136 is ON, and the output of the inverter 132 is L.
Level, and the nMOS transistor 138 is turned off.

Therefore, in this case, the output circuit 11
The signal DQ0 output from 0 becomes H level.

In the first embodiment, the SDR
AM 91 to 94 are connected to the bus line at equal intervals,
Only a bus line is provided between the microprocessor 90 and the SDRAM 91.

Therefore, when the characteristic impedance of the bus line 115 is Z0, the characteristic impedance of the portion where the SDRAMs 91 to 94 are not connected is larger than that of the SDRAM 91 to 94 by the SDR.
Bus line 11 of a portion where AM 91 to 94 are connected at equal intervals
5 has a small effective characteristic impedance.

In general, characteristic impedance Z0 of bus line 115 can be represented by Z0 = (L / C) ^1/2 . Where L is the wiring inductance per unit length, C
Is the wiring capacitance per unit length.

For example, L = 250 nH / m, C = 10
0 pF is a typical value, in this case, Z0 = (2
50 × 10 ⁻⁹ / 100 × 10 ⁻¹² ) ^1/2 = 50Ω.

On the other hand, when the SDRAMs 91 to 94 are connected, their load capacitances (specifically, the input / output terminals 96
~ 99 capacity), for example, a load capacity of 3.75
If SDRAMs 91 to 94 of pF are connected to the bus line 115 at intervals of 6.25 mm, 160 connections per 1 m are obtained. If the capacity per unit length is CL, CL =
3.75 pF × 160 = 600 pF / m.

In this case, the effective characteristic impedance ZL of the bus line 115 is represented by ZL = [L / (C + CL)] ^1/2 , and in the above example, ZL = [250 × 10 ^-9]
/ (100 × 10 ^-12 + 600 × 10 ^-12 )] ^1/2 = 18.
9Ω, and the characteristic impedance Z0 when there is no load
= 50Ω, which is considerably smaller.

Therefore, in order to strictly match the impedance and avoid the reflection of the transmission signal, the terminating resistor 11 must be used.
The resistance values of 6, 117 should be 18.9Ω, the same value as the effective characteristic impedance ZL.

However, when the resistance values of the terminating resistors 116 and 117 are set to 18.9Ω, the load resistance viewed from the driving side becomes 9.4.
5Ω, and the output circuits 110 to 114 are at least
If there is no current driving capability of about 20 mA, the input circuit 105
To 109 cannot obtain an amplitude that can operate stably.

Therefore, in the first embodiment, the SDRAM
The value of the terminating resistor 117 on the side where 91-94 are concentrated is removed from the strict matching condition, is made larger than the effective characteristic impedance ZL, and the characteristic impedance Z0 of the bus line 115 when there is no load is limited. Has 30Ω
And

On the other hand, on the microprocessor 90 side, since the load connected is small, the value of the terminating resistor 116 is set to 50Ω which is the same value as the characteristic impedance Z0 of the bus line 115 when there is no load.

As a result, the load resistance seen from the driving side is 30
18.75Ω which is the parallel value of Ω and 50Ω
Can be increased as compared with the case where the load circuit is simply used on both sides (load resistance = 15Ω), so that the output circuits 110 to 1
Even when the current driving capability of the N.14 is relatively small, the signal amplitude can be increased.

In the first embodiment, the microprocessor 90 and the output circuit 110 of the SDRAMs 91 to 94 are used.
114 are constituted by a CMOS push-pull type having a power supply voltage of VCCQ, and a termination voltage VTT
Is set to VCCQ / 2, it is possible to transmit a signal having the intermediate voltage as the termination voltage VTT.

Here, for example, when output circuit 110 is outputting the L level, voltage generating circuit 85 → termination voltage line 89 → termination resistors 116, 117 → bus line 115 →
A current flows through a closed circuit consisting of the output circuit 110 (nMOS transistor 138) → ground → voltage generating circuit 85.

When output circuit 110 is outputting the H level, voltage generating circuit 84 → VCCQ power supply line 8
8 → Output circuit 110 (pMOS transistor 137) →
A current flows through a closed circuit consisting of the bus line 115 → the terminating resistors 116 and 117 → the voltage generating circuit 84.

As described above, according to the first embodiment, since the voltage generating circuit 83 is configured by connecting the voltage generating circuits 84 and 85 in series, the current is output from the voltage output terminal 87. Even if a current is input, the voltage of the voltage output terminal 87 can be maintained at V5 = 1.0 V, and the stability of the terminal voltage VTT = V5 = 1.0 V is ensured. be able to.

In the first embodiment, when the bus line 115 is not transmitting a signal, the termination resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

In the first embodiment, the output control circuit and the output circuits 110 to 114 operate at a lower power supply voltage VCCQ = 2.0 V than the power supply voltage VCC = 3.3 V for driving the main body circuit. Because I am going to drive
From this point as well, power consumption can be reduced.

In the first embodiment, the termination voltage VTT is set to the microprocessor 90 and the SDRAM 91.
Since the reference voltage Vref is used as a required reference voltage Vref to 94, the reference voltage Vref is matched with the termination voltage VTT so that an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal is provided. Can be secured.

According to the first embodiment, the power supply voltage of the output drive circuit for driving the output circuits 110 to 114 is the same as the power supply voltage VCCQ as in the case of the output circuits 110 to 114.
Are supplied, so that a pMOS transistor forming a pull-up element and an nMO transistor forming a pull-down element
The S transistor and the S transistor can be driven in a well-balanced manner.

Note that in the microprocessor 90,
The output control circuit 126, the output drive circuit 130, and the output circuit 110 can be configured as shown in the circuit diagram of FIG. The same applies to the SDRAMs 91 to 94.

In FIG. 8, in output control circuit 126, 1
41 is a NAND circuit, 142 is an inverter, and 143 is N
This is an OR circuit.

In the output drive circuit 130,
Reference numeral 4 denotes a CMOS type inverter to which the power supply voltage VCC is supplied, 145 denotes an enhancement type pMOS transistor, and 146 denotes an enhancement type nMOS transistor.

In the output circuit 110, reference numeral 147 denotes a depletion-type nMOS transistor serving as a pull-up element, and 148 denotes an enhancement-type nMOS transistor serving as a pull-down element. They try to improve their abilities.

In this case, a depletion type nMOS
If the L level voltage of the data signal DQ0 is set to V _OL so that the transistor 147 can be cut off,
The threshold voltage V of the nMOS transistor 147
_THD needs to be set to -V _OL ≤ V _THD .

For example, when the termination voltage VTT is 1.0 V, when the signal DQ0 is ± 0.25 V (drive current is 10 mA), V _OL = 1−0.25 = 0.75 V. In this case, In this case, V _THD may be set to −0.75 V or more.

Here, as shown in FIG. 9, the control signal / H
When Z = H level, the output of the inverter 142 = L level, the output of the NAND circuit 141 = H level, the pMOS transistor 145 = OFF, and the nMOS transistor 14
6 = ON, output of inverter 144 = L level, nMO
The S transistor 147 is turned off.

Further, the output of the NOR circuit 143 = L level and the nMOS transistor 148 = OFF, and in this case, the output state of the output circuit 110 becomes a high impedance state.

On the other hand, as shown in FIG. 10, when control signal / HZ = L level, data / DAT
When A = H level, the output of NAND circuit 141 =
L level, pMOS transistor 145 = ON, nMO
The S transistor 146 = OFF, the output of the inverter 144 = H level, and the nMOS transistor 147 = ON.

Further, the output of the NOR circuit 143 = L level, the nMOS transistor 148 turns off, and in this case, the signal DQ0 output from the output circuit 110 =
It becomes H level.

As shown in FIG. 11, control signal / H
When Z / L level and data / DATA = L level, output of NAND circuit 141 = H level, pMOS transistor 145 = OFF, nMOS transistor 146 = ON, output of inverter 144 = L
Level, nMOS transistor 147 = OFF.

Further, the output of the NOR circuit 143 = H level, the nMOS transistor 148 turns ON, and in this case, the signal DQ0 output from the output circuit 110 = L
Level.

The nMOS transistor 147 can be formed of an enhancement type nMOS transistor. In this case, the threshold voltage of the enhancement type nMOS transistor is nM.
Unless the threshold voltage is lower than the threshold voltage of the OS transistor 148, there is no point in increasing the driving capability due to a decrease in the threshold voltage.

Second Embodiment FIGS. 12 to 16 FIG. 12 is a circuit diagram showing a main part of a second embodiment of the present invention. In the second embodiment, a voltage generation circuit 150 having an output voltage different from that of the voltage generation circuit 83 shown in FIG. 3 is provided.

In this voltage generation circuit 150, 15
1, 152 are voltage generating circuits for generating a voltage V6 (1.65 V), and 153, 154 are voltage output terminals.

That is, the voltage generation circuit 150
6 are connected in series, a voltage 2 × V6 = 3.3 V is output as a power supply voltage VCCQ to a voltage output terminal 153, and a voltage V6 = 1 as a termination voltage VTT to a voltage output terminal 154. It outputs .65V.

Reference numerals 155 to 159 denote branch paths of the bus line 115, so-called stubs, and 160 to 164 denote bus lines 11
5 is a resistor connected between the branch point 5 and the stubs 160 to 165.

Further, in the second embodiment, VCC
The power supply voltage VCCQ supplied from the Q power supply line 88 is supplied to the VCC power supply terminal and the VCCQ power supply terminal of the microprocessor 90 and the SDRAMs 91 to 94.

Therefore, in the microprocessor 90 and the SDRAMs 91 to 94, the VCC power supply terminal is externally connected to the VCCQ power supply terminal.
FIG. 13 shows the case of the microprocessor 90.

That is, in the second embodiment, FIG.
As a representative example of the microprocessor 90, not only the main circuit 125 and the output control circuit 126 but also the output drive circuit 130 and the output circuit 110 are driven by the power supply voltage VCCQ = 3.3V.

In this case, nMOS transistor 13
Since the power supply voltage VCCQ = 3.3 V is also supplied to the gate of No. 8, the internal resistance of the nMOS transistor 138 decreases, and an excessive current flows to the output.

Therefore, in the second embodiment,
A resistor 16 is provided between the branch point of the bus line 115 and the stub 155.
0 is connected to set the internal resistance of the output circuit 110 to an appropriate value so that the drive current for the terminating resistors 116 and 117 does not change.

Similarly, resistors 161 to 164 are also connected between the branch point of the bus line 115 and the stubs 156 to 159.

FIGS. 14 and 15 are diagrams for explaining a method of determining the resistance values of the resistors 160 to 164.
Is the nMOS of the output circuit 110 of the microprocessor 90
FIG. 15 shows static characteristics of the transistor 138. FIG.
It is a figure which shows a part of.

That is, in the second embodiment, nMO
The S transistor 138 is configured to have static characteristics as shown in FIG.

Then, when nMOS transistor 138 = ON when VCCQ = 3.3V, V
_GS = 3.3 V, but in this case, the drain-source voltage V _DS = 0.2 V.

Here, the driving current of the nMOS transistor 138 is 10 mA, and the resistance values of the terminating resistors 116 and 117 =
Assuming that the resistance is 50Ω, the load resistance value is 25Ω, and the voltage drop of the terminating resistors 116 and 117 is as shown in FIG.
It becomes 0.25V.

As a result, the voltage of bus line 115 = 1.4 V
Therefore, as the resistance value of the resistor 160, (1.4-0.
2) / 10 × 10 ⁻³ = 120Ω should be selected. The same applies to the resistors 161 to 164.

As described above, by connecting the resistors 160 to 164 between the bus line 115 and the stubs 155 to 159, the influence of signal reflection occurring in the stubs 155 to 159 on the bus line 115 is minimized. can do.

In this case, the characteristic impedance of the stubs 155 to 159 can be determined as follows.

That is, first, the resistances of the resistors 160 to 164 are set to 120Ω in consideration of the driving force of the output circuit. However, since the characteristic impedance of the bus line 115 is 50Ω, the resistance of the bus line 115 is changed from the branch point. When you see, 50Ω is 2
Since the load appears to be in parallel, the load has a characteristic impedance of 25Ω.

On the other hand, the resistance 1 having a resistance value of 120Ω
When 60 to 164 are connected, when looking at the bus line 115 from the stubs 155 to 160, 120Ω + 25Ω = 145Ω
Looks like impedance.

Therefore, the characteristic impedance of the stubs 155 to 159 is preferably set to 145Ω. However, it has been confirmed by simulation that this value does not hinder practical use even if it changes by about ± 50%.

Thus, when a signal enters stubs 155 to 159 from bus line 115, input / output terminals 95
Since 99 is unterminated, it reflects 100%. However, when this reflection is transmitted to the resistors 160 to 164, no reflection occurs due to impedance matching.

That is, since this signal is absorbed by the terminating resistors 116 and 117 after entering the bus line 115, no resonance phenomenon occurs in the stubs 155 to 159 and good signal transmission can be performed thereafter. it can.

As in the case of the first embodiment, VCC
In the case of Q = 2.0 V, when the nMOS transistor 138 is turned ON, V _GS = 2.0 V, but in this case, the drain-source voltage V _DS = 0.75 V.

Here, the driving current of the nMOS transistor 138 = 10 mA, and the resistance values of the terminating resistors 116 and 117 =
Since 50Ω and load resistance = 25Ω, the voltage drop of the terminating resistors 116 and 117 is 0.25 V as shown in FIG. 16, and in this case, the resistor 160 is not required.

In this case, if the power supply voltage VCCQ is lowered,
Since the resistors 160 to 164 are unnecessary, there is an advantage that the number of components can be reduced.

However, as described above, the stubs 155 to 159
Since the effect of suppressing the resonance by the impedance matching cannot be obtained, the lengths of the stubs 155 to 159 need to be as short as possible.

In the second embodiment, the microprocessor 90 and the output circuit 110 of the SDRAMs 91 to 94 are used.
114 are constituted by a CMOS push-pull type having a power supply voltage of VCCQ, and a termination voltage VTT
Is set to VCCQ / 2, it is possible to transmit a small-amplitude signal using the intermediate voltage as the termination voltage VTT.

Here, for example, when output circuit 110 is outputting the L level, voltage generating circuit 152 → terminal voltage line 89 → terminal resistors 116, 117 → bus line 115
→ Output circuit 110 (nMOS transistor 138) → Ground → Current flows through a closed circuit consisting of voltage generation circuit 152.

When output circuit 110 is outputting the H level, voltage generating circuit 151 → VCCQ power supply line 88 → output circuit 110 (pMOS transistor 137)
A current flows through a closed circuit consisting of → the bus line 115 → the terminating resistors 116 and 117 → the voltage generating circuit 151.

As described above, according to the second embodiment, since the voltage generating circuit 150 is configured by connecting the voltage generating circuits 151 and 152 in series, the voltage output terminal 154 is provided.
Irrespective of whether a current is output or a current is input, the voltage of the voltage output terminal 154 is set to V6 =
1.65 V and the termination voltage VTT = V
6 = 1.65V stability can be ensured.

In the second embodiment, when the bus line 115 is not transmitting a signal, the termination resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

Further, in the second embodiment, the termination voltage VTT is changed by the microprocessor 90 and the SDRAM 91.
Since the reference voltage Vref is used as a required reference voltage Vref to 94, the reference voltage Vref is matched with the termination voltage VTT so that an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal is provided. Can be secured.

In the second embodiment, since the resistors 160 to 164 are connected to the branch point of the bus line 115, it is possible not only to prevent an excessive current from flowing to the output, but also to prevent the stubs 155 to 155 from flowing. Even when 159 is required, when the reflection component of the signal generated at these stubs 155 to 159 flows into the bus line 115, the high-frequency component is cut by the resistors 160 to 164, so that the transmission waveform is distorted. This is advantageous in that it is difficult to occur.

Therefore, the second embodiment is different from the SDRA
It can be said that this is suitable for a system in which the M91 to M94 are mounted on a module (SIMM) and connected to the bus line 115 of the board via the connector of the module.

On the other hand, in the structure of the first embodiment, the SDRAM is used to suppress the generation of stubs 155 to 159.
It can be said that this is suitable for a system in which 91 to 94 are directly connected to the bus line 115.

Third Embodiment FIG. 17 FIG. 17 is a circuit diagram showing a main part of a third embodiment of the present invention. In the third embodiment, the bus line 115 and the stubs 156 to 156 are used.
159, the resistors 161 to 164 are connected, and the bus line 1
No resistor is connected between the microprocessor 15 and the microprocessor 90, and the other components are the same as those shown in FIG.
The configuration is the same as that of the embodiment.

Here, the SDRAMs 91 to 94 are replaced with SIMMs.
When mounted on the bus, the bus wire 115 and the stubs 155 to 155
59, it is easy to insert the resistors 161 to 164, but the microprocessor 90 has a PGA (pin grid a).
rray) Packaged on a package with a large number of pins.
There is often no place to put the resistor 160 shown in FIG.

Therefore, in the third embodiment, the resistors 161 to 161 are connected between the bus line 115 and the stubs 156 to 159.
164, the bus line 115 and the microprocessor 9
Between 0 and 0, the resistor 160 shown in FIG. 12 was not connected.

Here, even if the resistor 160 shown in FIG. 12 is not used, the microprocessor 90 is connected to the end of the bus line 115 in many cases, and the terminating resistor 116 is used.
, The distortion of the transmission signal can be relatively reduced.

In such a case, the output circuit 110 of the microprocessor 90 can reduce the driving force of the transistor so that the internal resistance is relatively high, around 100Ω, so that the resistor 160 shown in FIG. At least, it is configured to prevent an excessive current from flowing.

The internal resistance of the output circuit 110 is set to 100
As a method for setting the resistance around Ω, the pMOS transistor 1
There is a method in which a resistor is connected in series to the output of the output circuit 110 near the output circuit 110, for example, on a chip or in a package, depending on the size of the 37 and the nMOS transistor 138.

PMOS transistor 137 and nMOS
Depending on the size of the transistor 138, pMOS
Transistor 137 has a gate width of, for example, 5
00 μm and the gate length may be 1 μm, for example. The nMOS transistor 138 has a gate width of
For example, 200 μm, and the gate length is, for example, 1 μm
It is good.

On the other hand, when a resistor is connected in series with the output, the pMOS transistor 137 may have a gate width of, for example, 1000 μm and a gate length of, for example, 1 μm.
Has a gate width of, for example, 400 μm and a gate length of, for example, 1 μm.

Here, if a resistor connected in series to the output circuit 110 has a negative temperature coefficient, the output circuit 11
Since the internal resistance of the 0-transistor has a positive temperature characteristic, it can be offset from this, which is preferable.

As a specific example, it can be formed by using an amorphous semiconductor material generally called a thermistor.

As a simple method, it may be formed by using a region called a diffusion layer formed on a semiconductor substrate. In particular, the p-type diffusion layer has a larger temperature coefficient than the n-type diffusion layer and is suitable for this purpose.

Since these transistors have a property that the resistance value decreases at a high temperature, it is possible to cancel the phenomenon that the driving force of the transistor decreases at a high temperature.

Fourth Embodiment FIG. 18 FIG. 18 is a circuit diagram showing a main part of a fourth embodiment of the present invention. The fourth embodiment of the present invention includes a temperature sensor 165,
The voltage V6 generated by the voltage generation circuits 151 and 152 is controlled by the temperature sensor 165, and the other configuration is the same as that of the third embodiment.

Here, bus line 115 and stubs 156-1
59, the resistors 161 to 164 are connected to the bus line 11
In the case where no resistor is connected between the microprocessor 5 and the microprocessor 90 and the driving force of the transistor of the output circuit 110 of the microprocessor 90 is reduced, the temperature dependence of the driving force of the output circuit 110 of the microprocessor 90 You need to be careful.

This is because the MOS transistor has a negative drive current temperature coefficient, and the drive power decreases as the operating temperature increases.

Therefore, regardless of the operating temperature, the bus line 115
In order to keep the above signal amplitude constant, the voltage generation circuit 151,
It is preferable to make the voltage V6 output from 152 have a positive temperature coefficient. For example, it is preferable that the value of V6 be 1.3 V at 25 ° C. and 1.65 V at 100 ° C.

Note that only the power supply voltage of the input / output circuit may be made to depend on the temperature, the power supply voltage of the main body circuit may be kept constant, or the power supply voltage of the input / output circuit and the main body circuit may be made to depend on the temperature.

Further, such temperature compensation is performed by the bus line 11.
5 can be applied regardless of the presence or absence of the resistor connected to 5.

Fifth Embodiment FIGS. 19 to 22 FIG. 19 is a circuit diagram showing a main part of a fifth embodiment of the present invention. In the fifth embodiment, a termination voltage generation circuit 166 is provided instead of the voltage generation circuit 83 shown in FIG.

In response to this, termination voltage generating circuit 166
VCCQ power supply line 167 for supplying power supply voltage VCCQ = 2.0 V to power supply voltage VSSQ.
A VSSQ power supply line 168 for supplying Q is provided.

In the fifth embodiment, the power supply voltage VCCQ is supplied from the VCCQ power supply line 167 to the microprocessor 90 and the SDRAMs 91 to 94. Is configured similarly to the first embodiment shown in FIG.

Here, in the termination voltage generating circuit 166, 171 is an operational amplifier, and 172 and 173 are voltage dividing resistors having the same resistance value.

This termination voltage generating circuit 166 converts the power supply voltage VCCQ to VCCQ / 2 = by the voltage dividing resistors 172 and 173.
The output voltage of the operational amplifier 171 is fed back to the negative-phase input terminal (inverting input terminal) of the operational amplifier 171, and the voltage is supplied to the positive-phase input terminal (non-inverting input terminal) of the operational amplifier 171. Operational amplifier 171
Is obtained at the output terminal as VCCQ / 2 as the termination voltage VTT.

Here, in the fifth embodiment, the termination voltage generating circuit 166, the voltage dividing resistors 172 and 173, and the data D
The terminating resistor 117 for the bus line 115 provided corresponding to Q0 and the terminating resistor for the bus line provided corresponding to the data DQ1 to DQ7 are integrated on one chip.
SDRAM as termination module (termination device) 174
It is packaged in the same dimensions as 91 to 94.

FIG. 20 is a diagram schematically showing the terminal module 174. In FIG.
76 to 181 are bus line terminating resistors provided corresponding to the data DQ1 to DQ7, 182 to 200 are external terminals, and these external terminals 182 to 200 are SDRAs.
M91-94 are provided at the same positions as the corresponding external terminals.

Therefore, in the fifth embodiment, FIG.
As shown in FIG. 1, the SDRAMs 91 to 94 and the termination module 174 are integrated as a memory stack 201 and mounted on a circuit board 202.

Therefore, in the fifth embodiment,
Supply of the power supply voltage VCCQ from the VCCQ power supply line 167 to the SDRAMs 91 to 94 is performed by the memory stack 20.
1 is performed.

In FIG. 21, 203 and 204 are vertical sub boards, and 205 and 206 are data DQ1 and DQ.
Bus lines provided corresponding to Q7, 207, 20
Reference numerals 8 and 209 denote connector sections.

In this case, the assembly cost can be reduced, and the bus line can be minimized to be suitable for high-speed signal transmission.
Since the termination voltage VTT is generated in the vicinity of .about.94, fluctuation of the reference voltage Vref due to noise or the like can be avoided.

The terminal resistors 116, 117, 176-
181 as the termination module, and the termination voltage generation circuit 1
It is also possible to make it separate from 66.

In the fifth embodiment, the termination voltage generating circuit 166 is configured as shown in FIG.

In the figure, 211 is a VCCQ power supply line, 212 is a VSSQ power supply line, 213 and 214 are differential amplifier circuits, and in the differential amplifier circuit 213, 215 and 216 are enhancement elements constituting a load current mirror circuit. PMOS transistor.

Reference numerals 217 and 218 denote enhancement type nMOS transistors serving as drive transistors.
19 is an enhancement type nMO functioning as a resistor.
It is an S transistor.

In the differential amplifying circuit 214, 22
0 is an enhancement type pMOS functioning as a resistor
Transistors 221 and 222 are enhancement type pMOS transistors forming driving transistors, 22
Reference numerals 3 and 224 denote an enhancement type nMOS forming a load.
It is a transistor.

Reference numeral 225 denotes an output circuit, 226 denotes an enhancement type pMOS transistor serving as a pull-up element, and 227 denotes an enhancement type nMOS transistor serving as a pull-down element.

When terminating voltage generating circuit 166 is configured in this manner, a stable terminating voltage VTT can be obtained even when the power supply voltage VCCQ fluctuates.

In the fifth embodiment, the microprocessor 90 and the output circuit 110 of the SDRAMs 91 to 94 are used.
To 114 are CMOs with a power supply voltage of VCCQ = 2.0 V
It is configured as an S-type push-pull type, and since the termination voltage VTT is VCCQ / 2 = 1.0 V, it is possible to transmit a signal having the intermediate voltage as the termination voltage VTT.

Here, for example, when output circuit 110 is outputting L level, termination voltage generating circuit 166
→ Terminal voltage line 89 → Terminal resistors 116 and 117 → Bus line 1
15 → Output circuit 110 (nMOS transistor 138)
A current flows through a closed circuit consisting of → ground → power supply voltage generation circuit (not shown) for generating power supply voltage VCCQ → VCCQ power supply line 167 → termination voltage generation circuit 166.

On the other hand, when output circuit 110 is outputting the H level, VCCQ power supply line 167 → output circuit 110 (pMOS transistor 137) → bus line 1
15 → Terminal resistor 116,117 → Terminal voltage generation circuit 16
6 → VSSQ power supply line 168 → power supply voltage generating circuit (not shown) for generating power supply voltage VCCQ → VCCQ power supply line 16
7, a current flows through the closed circuit.

As described above, in the fifth embodiment,
The termination voltage generation circuit 166 uses the operational amplifier 171 to output the output voltage of the operational amplifier 171, that is, the termination voltage VT.
Since T is configured to perform feedback control, even if a current is output from the termination voltage generation circuit 166 to the termination voltage line 89, the current is supplied from the termination voltage line 89 to the termination voltage generation circuit 166. Even when the voltage is input, the stability of the terminal voltage VTT = VCCQ / 2 = 1.0 V can be ensured.

In the fifth embodiment, when the bus line 115 is not transmitting a signal, the termination resistor 11
Since no current flows through 6, 117, power consumption can be reduced.

In the fifth embodiment, it is assumed that the input / output circuit section is configured in the same manner as in the first embodiment, and the output driving circuits and the output circuits 110 to 114 are provided with a power supply voltage for driving the main body circuit. Since the power supply is driven at a power supply voltage VCCQ = 2.0 V which is lower than VCC = 3.3 V, power consumption can be reduced from this point as well.

In the fifth embodiment, the termination voltage VTT is changed by the microprocessor 90 and the SDRAM 91.
Since the reference voltage Vref is used as a required reference voltage Vref to 94, the reference voltage Vref is matched with the termination voltage VTT so that an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal is provided. Can be secured.

According to the fifth embodiment, the input / output circuit section is configured in the same manner as in the first embodiment. Power supply voltage VC as in circuits 110 to 114
Since CQ is supplied, a pMOS transistor serving as a pull-up element and n serving as a pull-down element
The MOS transistors and the MOS transistors can be driven in a well-balanced manner.

Sixth Embodiment FIGS. 23 and 24 FIG. 23 is a circuit diagram showing a main part of a sixth embodiment of the present invention. In the figure, 228 is a VCC power supply line for supplying a power supply voltage VCC = 3.3 V, and 229 is a power supply voltage VCCQ = 1.2 V
Is a VCCQ power supply line.

Reference numeral 230 denotes a microprocessor; 231, a signal input / output terminal for inputting / outputting a signal;
232 is a VCC power supply terminal for taking in the power supply voltage VCC, and 233 is a VCCQ power supply line for taking in the power supply voltage VCCQ = 1.2V.

Reference numeral 234 denotes a VCC power supply line for supplying the power supply voltage VCC to an internal circuit, and 235 denotes a power supply voltage V
VCCQ power supply line for supplying CCQ to internal circuits,
236 is a push-pull type output circuit.

In the push-pull type output circuit 236, 237 is a pMOS transistor forming a pull-up element, and 238 is an nMOS transistor forming a pull-down element.

Further, 240 is a bus line for transmitting signals, 241 is a terminator, 242 and 243 are diodes having a forward voltage of 0.65 V, and 244 and 245 are resistors having a resistance of 15Ω. is there.

Here, since the added value of the forward voltage of diodes 242 and 243 is 1.3 V, bus line 240
Does not transmit a signal, no current flows through the terminating portion 241.

Reference numeral 246 denotes an SDRAM.
Is a signal input / output terminal for inputting / outputting a signal, 248 is a reference voltage input terminal to which 0.65 V is supplied as a reference voltage Vref, 249 is a VCC power supply terminal to which a power supply voltage VCC is supplied, and 250 is an input circuit. .

FIG. 24 is a graph showing the characteristics of the termination 241. The horizontal axis shows the voltage of the bus line 240, and the positive side of the vertical axis shows the pMOS transistor 237 = ON, nMOS
When transistor 238 is turned off, VCCQ
From the power supply line 235 indicates the current value of the pMOS transistor 237 → bus line 240 → the resistor 245 → diode 243 → current flows to the ground i _5.

On the negative side of the vertical axis, the pMOS transistor 237 = OFF and the nMOS transistor 238 = ON
In this case, the current i ₆ flows from the VCCQ power supply line 229 to the diode 242 → the resistor 244 → the bus line 240 → the nMOS transistor 238 → the ground.

That is, in the sixth embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₅ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 starts to rise.

[0206] Thereafter, when the voltage of the bus line 240 exceeds 0.65V is the forward voltage of the diode 243, next to the diode 243 is ON, so that current flows i ₅ to resistor 245 and diode 243.

The voltage of the bus line 240 is 0.65 V
(Forward voltage of diode 243) + 15Ω (resistance 24
5) × 0.01 mA (pMOS transistor 2)
37 drive current) = 0.8V.

On the other hand, pMOS transistor 23
7 = OFF and nMOS transistor 238 = ON, the bus line 240 connects the nMOS transistor 238
, A current i ₆ flows to the ground, and the voltage of the bus line 240 decreases.

Thereafter, when the voltage of the bus line 240 becomes lower than 0.65 V which is the forward voltage of the diode 242, the diode 242 is turned on and the diode 242 is turned on.
The current i ₆ also flows through the resistor 244.

Then, the voltage of the bus line 240 is 1.2-
0.65V (forward voltage of diode 242) + 15Ω
(The resistance value of the resistor 244) × 0.01 mA (the drive current of the nMOS transistor 238) = 0.4V.

As described above, according to the sixth embodiment, even when the H level is output from output circuit 236, no current flows into VCCQ power supply line 229, so that termination voltage VTT = The stability of VCCQ = 1.2V can be ensured.

Note that when signals are input and output from the output circuit 236, the diodes 242 and 243 are in a non-conductive state, so that transmission signals may be reflected until the diode 242 or the diode 243 becomes conductive. However, since this reflection is very small, it does not substantially affect signal transmission.

In the sixth embodiment, when the bus line 240 is not transmitting a signal, the terminal 241
, No current flows, so that power consumption can be reduced.

In the sixth embodiment, output circuit 236 has power supply voltage VCC = 3.
Since driving is performed with a power supply voltage VCCQ = 1.2 V lower than 3 V, power consumption can be reduced from this point as well.

In the sixth embodiment, when inputting / outputting a signal, the terminal 241 is open when viewed from the output circuit 236, so that the voltage of the bus line 240 changes rapidly.
After that, the termination will be added.

As a result, when a large load is connected to the bus line 240 and the effective characteristic impedance of the bus line 240 is small, the resistance values of the resistors 243 and 244 are reduced to match the effective characteristic impedance. Also,
A signal with a sufficient amplitude can be obtained.

Seventh Embodiment FIGS. 25 to 27 FIG. 25 is a circuit diagram showing a main part of a seventh embodiment of the present invention. In the seventh embodiment of the present invention, the terminal 241 shown in FIG.
A termination 252 having a different circuit configuration from that of the sixth embodiment is provided, and the other configuration is the same as that of the sixth embodiment shown in FIG.

The terminal section 252 is connected to the VCCQ power supply line 22.
9 and the bus line 240, the diode 2 shown in FIG.
In place of the diode 243 and the resistor 245, a diode-connected enhancement type nMOS transistor 253 is connected instead of the resistor 244 and the diode 243 shown in FIG. 254 are connected.

Here, a diode-connected nMOS
In the transistors 253 and 254, the relationship between the voltage V applied between the drain and the source and the current I flowing between the drain and the source is as follows: if the gain constant is β, I = β
(V-VTH) < ² > / 2.

Therefore, the H level voltage of the transmission signal is set to 0.8
Assuming that the V and L level voltages are 0.4 V, the voltage V applied between the drain and source of the nMOS transistors 253 and 254 is 0.8 V.

Therefore, pMOS transistor 237
And the drive current of the nMOS transistor 238 is 10 mA.
Then, from 10 × 10 ⁻³ = β (0.8−0.65) ² , β = 0.44.

Here, β can be expressed by β = μC _OX W / L. Where μ is the effective mobility of the electron,
About 400 cm / V _S , C _OX is the gate capacitance per unit area.

Therefore, the nMOS transistors 253, 2
At 54, the gate oxide film is 10 nm, W / L = 33
If it is set to 00, the characteristics of the terminal end portion 252 can be as shown in FIG.

In FIG. 26, the horizontal axis represents the bus line 24.
When the pMOS transistor 237 = ON and the nMOS transistor 238 = OFF, the current i flowing from the VCCQ power supply line 235 to the pMOS transistor 237 → the bus line 240 → the nMOS transistor 254 is shown on the positive side of the vertical axis. ₇ shows the current value.

On the negative side of the vertical axis, the pMOS transistor 237 = OFF and the nMOS transistor 238 = ON
In this case, the current i ₈ flows from the VCCQ power supply line 229 to the nMOS transistor 253 → the bus line 240 → the nMOS transistor 238.

That is, in the seventh embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₇ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 rises.

Thereafter, the voltage of bus line 240 is changed to the threshold voltage VTH of nMOS transistor 254 = 0.6.
When the voltage exceeds 5 V, the nMOS transistor 254 turns on, and the current i ₇ flows through the nMOS transistor 254.

Then, the voltage of the bus line 240 is
ON resistance of nMOS transistor 254 × 0.01 mA
(Current drive capability of pMOS transistor 237) = 0.
It rises to 8V.

On the other hand, pMOS transistor 23
7 = OFF and nMOS transistor 238 = ON, the bus line 240 connects the nMOS transistor 238
, A current i ₈ flows to the ground, and the voltage of the bus line 240 decreases.

Thereafter, the voltage of bus line 240 is changed to the threshold voltage VTH of nMOS transistor 253 = 0.6.
When the voltage becomes lower than 5 V, the nMOS transistor 253 turns on, and the current i ₈ flows through the nMOS transistor 253.

The voltage of the bus line 240 is 1.2-
ON resistance of nMOS transistor 253 × 0.01 mA
(Current drive capability of nMOS transistor 238) = 0.
It falls to 4V.

As described above, according to the seventh embodiment, even when the H level is output from output circuit 236, no current flows into VCCQ power supply line 229, so that termination voltage VTT = The stability of VCCQ = 1.2V can be ensured.

Since the nMOS transistors 253 and 254 are off when signals are input and output from the output circuit 236, the transmission signal is not reflected until the nMOS transistor 253 or 254 becomes conductive. However, this reflection is so small that it does not substantially affect the signal transmission.

In the seventh embodiment, when the bus line 240 is not transmitting a signal, the terminal 252
, No current flows, so that power consumption can be reduced.

In the seventh embodiment, output circuit 236 has power supply voltage VCC = 3.
Since driving is performed with a power supply voltage VCCQ = 1.2 V lower than 3 V, power consumption can be reduced from this point as well.

In the seventh embodiment, at the time of input / output of a signal, since the terminal 252 is open when viewed from the output circuit 236, the voltage of the bus line 240 changes rapidly.
After that, the termination will be added.

As a result, a signal having a sufficient amplitude can be obtained even when a large load is connected to the bus line 240 and the effective characteristic impedance of the bus line 240 is small.

According to the seventh embodiment, the nMOS
Since the internal resistance of the transistors 253 and 254 is larger than the resistance of the diode, the resistances 244 and 24 shown in FIG.
5 is unnecessary, and the circuit configuration can be simplified accordingly.

Here, when the terminating section 252 is applied as a terminating section of a bus line connected to an SDRAM for inputting / outputting 8-bit data, as shown in FIG. It is preferable to make it modular.

Reference numeral 255 denotes a terminal module main body;
6, 257 are resistors for obtaining the reference voltage Vref.

Eighth Embodiment FIGS. 28 to 32 FIG. 28 is a circuit diagram showing a main part of an eighth embodiment of the present invention. In the eighth embodiment of the present invention, a terminal 259 having a different circuit configuration from the terminal 241 shown in FIG. 23 is provided.

The terminal 259 is connected to the VCCQ power supply line 22.
9 and the bus line 240, the diode 2 shown in FIG.
Instead of the resistor 42 and the resistor 244, an enhancement type nMOS transistor 26 constituting a source follower circuit is used.
0, and an enhancement type pMOS transistor 261 constituting a source follower circuit is connected between the bus line 240 and the ground in place of the diode 243 and the resistor 245 shown in FIG.

That is, the terminal 259 is connected to the nMO
S transistor 260 and pMOS transistor 261
And a complementary source-follower circuit.

Further, in the eighth embodiment, a bias voltage generating circuit 262 for supplying bias voltages VN and VP is provided in the terminating section 259, and in other respects, the sixth embodiment shown in FIG. It is configured similarly to.

The bias voltages VN, VP and nMO
The threshold voltage V _{TH-n of the} S transistor 260;
The threshold voltage V of the pMOS transistor 261
The relationship with _TH-p is VN-VP < _VTH-n + | _VTH-p |.

That is, when the bus line 240 is not transmitting a signal, the nMOS transistor 260 and the pMOS
The transistor 261 is set to be off.

Here, the bias voltage generation circuit 262 is configured as shown in FIG. In the figure, reference numeral 264 denotes a VCC power supply line for supplying the power supply voltage VCC, and 265 denotes a VSS power supply line for supplying the power supply voltage VSS.

266 is an nMOS transistor 26
An operational amplifier 267 for generating a bias voltage VN for supplying to 0 is an operational amplifier for generating a bias voltage VP for supplying to the pMOS transistor 261.

Also, 268 to 271 are operational amplifiers 266
The reference voltage Vref ₂₆₆ to be supplied to a resistor for generating a reference voltage Vref ₂₆₇ to be supplied to the reference voltage Vref and the operational amplifier 267 is supplied to the input circuit 250.

Here, the operational amplifier 266 is configured as shown in FIG. In the figure, reference numerals 272 and 273 denote differential amplifier circuits.
Reference numerals 4 and 275 denote enhancement-type pMOS transistors constituting a current mirror circuit forming a load.

Further, reference numerals 276 and 277 denote enhancement type nMOS transistors which serve as drive transistors,
78 is an enhancement type nMO functioning as a resistor.
It is an S transistor.

In the differential amplifier circuit 273, 27
9 is an enhancement type pMOS functioning as a resistor
Transistors 280 and 281 are enhancement-type pMOS transistors forming driving transistors, 28
Reference numerals 2 and 283 denote an enhancement type nMOS forming a load.
It is a transistor.

Reference numeral 284 denotes an output circuit; 285, an enhancement pMOS transistor serving as a pull-up element; and 286, an enhancement nMOS transistor serving as a pull-down element.

When the operational amplifier 266 is configured as described above, a stable bias voltage VN can be obtained with a constant voltage even when the power supply voltage VCC fluctuates.

The operational amplifier 267 is configured as shown in FIG. In the figure, reference numerals 287 and 288 denote differential amplifier circuits.
Reference numeral 290 denotes an enhancement-type pMOS transistor constituting a current mirror circuit forming a load.

Further, reference numerals 291 and 292 denote enhancement type nMOS transistors as drive transistors,
93 is an enhancement type nMO functioning as a resistor.
It is an S transistor.

In the differential amplifier circuit 288, 29
4 is an enhancement type pMOS functioning as a resistor
Transistors 295 and 296 are enhancement-type pMOS transistors serving as drive transistors, 29
7 and 298 are enhancement type nMOSs forming a load.
It is a transistor.

Reference numeral 299 denotes an output circuit, reference numeral 300 denotes an enhancement pMOS transistor serving as a pull-up element, and reference numeral 301 denotes an enhancement nMOS transistor serving as a pull-down element.

When the operational amplifier 267 is configured as described above, a stable bias voltage VP can be obtained even when the power supply voltage VCC fluctuates.

FIG. 32 is a graph showing the characteristics of the termination 259. The horizontal axis shows the voltage of the bus line 240, and the vertical axis shows the pMOS transistor 237 = ON, nMO
When the S transistor 238 is turned off, VCC
Current i flowing from Q power supply line 235 to pMOS transistor 237 → bus line 240 → pMOS transistor 261
₉ shows the current value.

On the negative side of the vertical axis, the pMOS transistor 237 = OFF and the nMOS transistor 238 = ON
If it is a shows the current i ₁₀ flowing from the VCCQ power supply line 229 to the nMOS transistor 260 → bus line 240 → nMOS transistor 238.

That is, in the eighth embodiment, pMO
S transistor 237 = ON, nMOS transistor 2
When 38 = OFF, the current i ₉ flows from the VCCQ power supply line 235 to the bus line 240 via the pMOS transistor 237, and the voltage of the bus line 240 rises.

After that, the voltage of the bus line 240 becomes VP-V _TH
When the voltage exceeds _-P , the pMOS transistor 261 is turned on, and a current flows through the pMOS transistor.
The voltage of the bus line 240 is an H level voltage, for example, 0.8
It rises to V.

On the other hand, pMOS transistor 23
7 = OFF and nMOS transistor 238 = ON, the bus line 240 connects the nMOS transistor 238
A current i ₁₀ to ground through the flow, the voltage of the bus line 240 decreases.

Thereafter, the voltage of the bus line 240 becomes VN-V
_{When the} voltage is lower than _TH-n , the nMOS transistor 260 is turned on, a current flows through the nMOS transistor 260, and the voltage of the bus line 240 becomes the L level voltage,
For example, it falls to 0.4V.

As described above, according to the eighth embodiment, even when the H level is output from output circuit 236, no current flows into VCCQ power supply line 229, so that termination voltage VTT = The stability of VCCQ = 1.2V can be ensured.

At the time when a signal is input / output from output circuit 236, nMOS transistor 260 and pMO
Since S transistor 261 is off, nMO
S transistor 260 or pMOS transistor 261
Until is turned on, reflection of the transmission signal may occur, but this reflection is so small that it does not substantially affect the transmission of the signal.

In the eighth embodiment, when the bus line 240 is not transmitting a signal, the termination unit 259
, No current flows, so that power consumption can be reduced.

The nMOS transistor 260 and p
Bias voltage V supplied to MOS transistor 261
N and VP are not generated by a voltage generation circuit based on resistance division, and a bias voltage generation circuit 2 comprising a differential amplifier circuit is provided.
The reason for providing 62 is that when current is drawn from the source side,
This is to prevent the gate voltage from being modulated by the parasitic capacitance between the gate and the source to stop the source follower function.

Ninth Embodiment FIG. 33 FIG. 33 is a circuit diagram showing a main part of a ninth embodiment of the present invention. In the figure, reference numeral 303 denotes an input circuit of a microprocessor, and 304 denotes a VC for supplying a power supply voltage VCC = 3.3 V.
C power line.

Reference numeral 305 denotes an output circuit of the microprocessor, reference numeral 306 denotes a VCCQ power supply line for supplying a power supply voltage VCCQ = 1.2 V, reference numeral 307 denotes a depletion type nMOS transistor serving as a pull-up element, and reference numeral 308 denotes a pull-down element Is an enhancement type nMOS transistor.

Reference numeral 309 denotes an input circuit of the SDRAM. Reference numerals 310 and 311 denote enhancement-type pMOS transistors forming loads, and reference numerals 312 and 313 denote enhancement-type nMOS transistors forming a current mirror circuit.

Reference numeral 314 is a waveform shaping inverter, 315 is an enhancement type pMOS transistor, and 316 is an enhancement type nMOS transistor.

Reference numeral 317 denotes an output circuit, reference numeral 318 denotes a depletion type nMOS transistor serving as a pull-up element, and reference numeral 319 denotes an enhancement type nMOS transistor serving as a pull-down element.

Reference numeral 320 denotes a VCCQ power supply line, reference numeral 321 denotes a bus line forming a signal transmission path, reference numerals 322 and 323 denote termination portions for terminating the bus line, reference numerals 324 to 327 denote diodes for setting the forward voltage to 0.65 V, 328 to 331 are resistors having a resistance value of 15Ω.

Reference numeral 332 denotes a reference voltage generation circuit for generating the reference voltage Vref. Reference numerals 333 and 334 denote diodes for setting the forward voltage to 0.65 V, and reference numerals 335 and 336 denote resistors.

In the ninth embodiment, the pMOS transistor 311 → the nMOS transistor 313 → the resistor 3
The current iref flows from 36 → diode 334 → ground, and the voltage of the node 337, that is, the reference voltage Vref is set to 0.65V which is the forward voltage of the diode 334.

As a result, when the bus line 321 does not transmit a signal, the pMOS transistor 310 → nMO
S transistor 312 → bus line 321 → resistor 329, 3
31 → diodes 325, 327 → ground, a current i _IN flows, and the voltage of the bus line 321 is also similar to the reference voltage Vref.
Set to 0.65V.

Here, for example, in the output circuit 305, when the nMOS transistor 307 is turned off and the nMOS transistor 308 is turned on, the VCCQ power supply line 320 → diodes 324, 326 → resistance 328,
330 → bus line 321 → nMOS transistor 308 →
A current flows to the ground, and the voltage of the bus line 321 becomes, for example,
It falls to 0.4V.

As a result, the level of the drain of the nMOS transistor 312 becomes L level, and the output of the inverter 314 becomes H level.

On the other hand, for example, output circuit 305
, NMOS transistor 307 = ON, nMO
When the S transistor 308 is turned off, VC
CQ power supply line 306 → nMOS transistor 307 → bus line 321 → resistors 329 and 331 → diodes 325 and 3
27 → Current flows from the ground, and the voltage of the bus line 321 rises to, for example, 0.8V.

As a result, the level of the drain of the nMOS transistor 312 becomes H level, and the output of the inverter 314 becomes L level.

In the ninth embodiment, the reference voltage Vre
Since f = 0.65 V is set, the bus line 321 is transmitted when the L level signal is transmitted, compared with the time required for the bus line 321 to rise to 0.8 V when the H level signal is transmitted.
There is a possibility that the time until 1 falls to 0.4 V may be long, but this is because nM which forms a pull-down element of the output circuit
This can be avoided by increasing the driving capability of the OS transistors 308 and 319.

As described above, according to the ninth embodiment, even when the output circuits 305 and 317 output the H level, no current flows into the VCCQ power supply line 320, so that the termination voltage The stability of VTT = VCCQ = 1.2V can be ensured.

Since the diodes 324 to 327 are in a non-conductive state when signals are input and output from the output circuits 305 and 317, transmission is performed until the diodes 324 and 325 or the diodes 326 and 327 are in a conductive state. Although signal reflections can occur, the reflections are so small that they have no substantial effect on signal transmission.

In the ninth embodiment, the output circuits 305 and 317 have a lower power supply voltage VCCQ = 1.3 than the power supply voltage VCC = 3.3 V for driving the input circuits 303 and 309 and the main circuit. Since driving is performed at 2 V, power consumption can be reduced.

[0287]

According to the first aspect of the present invention, two voltage generating circuits are connected in series, and a voltage obtained by adding the voltages of these two voltage generating circuits is supplied to an output circuit.
Since the voltage at the connection point of these two voltage generating circuits is supplied to the terminating resistor as the terminating voltage, even when a current flows from the bus line to the terminating voltage line via the terminating resistor, The termination voltage can be maintained at a constant voltage value, and the stability of the termination voltage can be ensured.

According to the first aspect, when no signal is transmitted through the bus line, no current flows through the terminating resistor, so that power consumption can be reduced.
Since the termination voltage can be used as the reference voltage, the reference voltage and the termination voltage can be matched, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

According to the second aspect of the present invention, the voltage generation circuit for outputting the termination voltage is configured to feedback-control the termination voltage by using an operational amplifier. Even when a current flows through the terminating voltage line via the resistor, the terminating voltage can be maintained at a constant voltage value and the stability of the terminating voltage can be ensured.

According to the second aspect of the present invention, when no signal is transmitted through the bus line, no current flows through the terminating resistor, so that power consumption can be reduced.
Since the termination voltage can be used as the reference voltage, the reference voltage and the termination voltage can be matched, an offset voltage is not generated in the input signal, and a sufficient operation margin of the input signal can be secured.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of an electronic device according to a first aspect of the present invention.

FIG. 2 is a diagram illustrating the principle of an electronic device according to a second aspect of the present invention.

FIG. 3 is a circuit diagram showing a main part of the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a part of a microprocessor provided in the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 6 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing an operation of a part of the microprocessor provided in the first embodiment of the present invention.

FIG. 8 is a circuit diagram illustrating another example of the output control circuit, the output drive circuit, and the output circuit that constitute the microprocessor provided in the first embodiment of the present invention.

FIG. 9 is a circuit diagram illustrating the operation of another example of the output control circuit, the output drive circuit, and the output circuit included in the microprocessor provided in the first embodiment of the present invention.

FIG. 10 is a circuit diagram illustrating operations of another example of an output control circuit, an output drive circuit, and an output circuit included in the microprocessor provided in the first embodiment of the present invention.

FIG. 11 is a circuit diagram illustrating operations of another example of an output control circuit, an output drive circuit, and an output circuit included in the microprocessor provided in the first embodiment of the present invention.

FIG. 12 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 13 is a circuit diagram showing a microprocessor provided in a second embodiment of the present invention.

FIG. 14 is a diagram illustrating static characteristics of an nMOS transistor included in an output circuit of a microprocessor provided in a second embodiment of the present invention.

FIG. 15 is a circuit diagram showing a part of the second embodiment.

FIG. 16 is a circuit diagram showing a part of the first embodiment.

FIG. 17 is a circuit diagram showing a main part of a third embodiment of the present invention.

FIG. 18 is a circuit diagram showing a main part of a fourth embodiment of the present invention.

FIG. 19 is a circuit diagram showing a main part of a fifth embodiment of the present invention.

FIG. 20 is a diagram schematically showing a termination module provided in a fifth embodiment of the present invention.

FIG. 21 is a schematic perspective view showing a main part of a fifth embodiment of the present invention.

FIG. 22 is a circuit diagram showing a termination voltage generation circuit provided in a fifth embodiment of the present invention.

FIG. 23 is a circuit diagram showing a main part of a sixth embodiment of the present invention.

FIG. 24 is a diagram showing characteristics of a termination portion provided in a sixth embodiment of the present invention.

FIG. 25 is a circuit diagram showing a main part of a seventh embodiment of the present invention.

FIG. 26 is a diagram showing characteristics of a termination portion provided in a seventh embodiment of the present invention.

FIG. 27 is a view schematically showing a termination module in which a termination section provided in a seventh embodiment of the present invention is packaged.

FIG. 28 is a circuit diagram showing a main part of an eighth embodiment of the present invention.

FIG. 29 is a circuit diagram showing a bias voltage generation circuit provided in an eighth embodiment of the present invention.

FIG. 30 is a diagram illustrating an operational amplifier constituting a bias voltage generating circuit according to an eighth embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an operational amplifier that generates a bias voltage of an OS transistor.

FIG. 31 is a diagram illustrating an operation amplifier constituting a bias voltage generation circuit according to an eighth embodiment of the present invention.
FIG. 3 is a circuit diagram illustrating an operational amplifier that generates a bias voltage of an OS transistor.

FIG. 32 is a view showing characteristics of a termination portion provided in the eighth embodiment of the present invention.

FIG. 33 is a circuit diagram showing a main part of a ninth embodiment of the present invention.

FIG. 34 is a circuit diagram illustrating an example of an electronic device that transmits a small-amplitude signal.

FIG. 35 is a circuit diagram illustrating an example of an interface circuit and a bus system applied to an electronic device that transmits a small-amplitude signal.

FIG. 36 is a circuit diagram illustrating another example of an interface circuit and a bus system applied to an electronic device that transmits a small-amplitude signal.

[Explanation of symbols]

 (FIG. 1) 43 termination voltage line 48 output circuit 51 bus line 52 termination resistor 56 input circuit (FIG. 2) 63 operational amplifier 67 termination voltage line 72 output circuit 75 bus line 76 termination resistor 80 input circuit

Claims (63)

(57) [Claims] 1. A push-pull type output circuit is provided.
An electronic device, comprising: a plurality of integrated circuits for inputting / outputting signals; and a bus line terminated at both ends with a terminating resistor and shared by the plurality of integrated circuits. 1 voltage generating circuit and a second voltage generating circuit for generating a second voltage are connected in series so that the first voltage can be added to the second voltage, and the first voltage and the second voltage An electronic device configured to supply a voltage obtained by adding the second voltage to the output circuit as a power supply voltage to the output circuit, and to supply the second voltage as a termination voltage to the termination resistor. 2. A push-pull type output circuit is provided.
An electronic device, comprising: a plurality of integrated circuits for inputting / outputting signals; and a bus line terminated at both ends with a terminating resistor and shared by the plurality of integrated circuits. 1 voltage generating circuit, and the first
Is supplied as a power supply voltage, a voltage obtained by dividing the first voltage is supplied to a first input terminal, an output terminal is connected to a second input terminal, and the first terminal is connected to the output terminal.
And a second voltage generating circuit having an operational amplifier configured to obtain a second voltage equal to the voltage obtained by dividing the voltage of the output circuit. And the second voltage is supplied to the termination resistor as a termination voltage. 3. The electronic device according to claim 1, wherein the plurality of integrated circuits are connected to the bus line via a resistor connected to a branch point of the bus line. 4. The resistance value of the resistor is such that when a power supply voltage supplied to the output circuit is increased, a drive current equal to a drive current of the output circuit when there is no resistance is obtained. The electronic device according to claim 3, wherein 5. The plurality of integrated circuits are connected to the bus line without a resistor and connected to the bus line via a resistor connected to a branch point of the bus line. The electronic device according to claim 1, wherein the electronic device includes an electronic device. 6. A drive current value as viewed from the bus line side of an output circuit of an integrated circuit connected to the bus line without passing through the resistor, and via a resistor connected to a branch point of the bus line. 6. The electronic device according to claim 5, wherein a drive current value of the output circuit of the integrated circuit connected to the bus line is equal to or substantially equal to a drive current value viewed from the bus line side. 7. A characteristic impedance value of a wiring connecting the integrated circuit connected to the bus line via the resistor and the resistor, the resistance value of the resistor being two times the characteristic impedance of the bus line. 7. The electronic device according to claim 3, wherein the value is within a value obtained by adding the value of (1). 8. An integrated circuit connected to the bus line without passing through the resistor, wherein an output is taken out via a resistor arranged near the output circuit. The electronic device according to 5, 6, or 7. 9. A resistor arranged near the output circuit,
9. The electronic device according to claim 8, wherein the electronic device has a negative temperature coefficient. 10. The electronic device according to claim 8, wherein the resistor arranged near the output circuit is arranged in a package forming an integrated circuit. 11. The first voltage generated by said first voltage generating circuit.
3. The voltage of (1) changes depending on the operating temperature of a part or all of the output circuits of the plurality of integrated circuits, and has a positive temperature coefficient. 3,
The electronic device according to 4, 5, 6, 7, 8, 9, or 10. 12. A second voltage generating circuit according to claim 2, wherein:
12. The electronic device according to claim 11, wherein the voltage changes depending on an operating temperature of a part or all of the output circuits of the plurality of integrated circuits, and has a positive temperature coefficient. apparatus. 13. The first voltage generating circuit is controlled by a temperature detecting device attached to a part or all of the plurality of integrated circuits to control a part or all of output circuits of the plurality of integrated circuits. 4. The method according to claim 1, wherein the first voltage has a positive temperature coefficient that changes a voltage value depending on an operating temperature.
The electronic device according to 6, 7, 8, 9 or 10. 14. The second voltage generating circuit is controlled by a temperature detecting device attached to a part or all of the plurality of integrated circuits, and controls a part or all of output circuits of the plurality of integrated circuits. 14. The electronic device according to claim 13, wherein the electronic device is configured to generate a second voltage having a positive temperature coefficient that changes a voltage value depending on an operating temperature. 15. A first voltage generator according to claim 1, wherein:
Voltage changes depending on the operating temperature of a part or all of the output circuit of the integrated circuit connected to the bus line without passing through the resistor, and has a positive temperature coefficient. The electronic device according to claim 5, 6, 7, 8, 9 or 10. 16. A second voltage generating circuit according to claim 2, wherein:
Voltage changes depending on the operating temperature of a part or all of the output circuit of the integrated circuit connected to the bus line without passing through the resistor, and has a positive temperature coefficient. The electronic device according to claim 15, wherein: 17. The first voltage generating circuit is controlled by a temperature detecting device attached to an integrated circuit connected to the bus line without passing through the resistor, and connected to the bus line without passing through the resistor. 9. A system according to claim 8, wherein said first circuit has a positive temperature coefficient for changing a voltage value depending on an operating temperature of an output circuit of a connected integrated circuit. The electronic device according to 5, 6, 7, 8, 9 or 10. 18. The second voltage generating circuit is controlled by a temperature detecting device attached to an integrated circuit connected to the bus line without passing through the resistor, and connected to the bus line without passing through the resistor. 9. The apparatus according to claim 8, wherein said second circuit has a positive temperature coefficient for changing a voltage value depending on an operating temperature of an output circuit of said integrated circuit. The electronic device according to claim 17, 19. The output circuit according to claim 1, wherein the p-channel insulated gate field effect transistor is configured as a pull-up element and the n-channel insulated gate field effect transistor is configured as a pull-down element.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
The electronic device according to 3, 14, 15, 16, 17 or 18. 20. A complementary first inverter comprising an insulated gate field effect transistor for driving said p-channel insulated gate field effect transistor, and an insulated gate electric field for driving said n-channel insulated gate field effect transistor. A complementary second inverter composed of an effect transistor is provided, and a power supply voltage of the same voltage as the power supply voltage supplied to the output circuit is supplied to the first and second inverters. 20. The electronic device according to claim 19, wherein: 21. The output circuit, comprising: a first n-channel insulated gate field effect transistor having a pull-up element;
Wherein the threshold voltage of the first n-channel insulated gate field effect transistor is equal to or higher than a low level voltage of a signal output from the output circuit, and 4. The method according to claim 1, wherein the voltage is lower than a threshold voltage of the second n-channel insulated gate field effect transistor.
6, 7, 8, 9, 10, 11, 12, 13, 14, 1
The electronic device according to 5, 16, 17 or 18. 22. The output circuit, wherein a depletion-type first n-channel insulated-gate field-effect transistor is a pull-up element, and an enhancement-type second n-channel insulated-gate field-effect transistor is a pull-down element. And a threshold voltage of the first n-channel insulated gate field effect transistor is equal to or higher than a low level voltage of a signal output from the output circuit. , 5, 6,
7, 8, 9, 10, 11, 12, 13, 14, 15, 1,
The electronic device according to 6, 17, or 18. 23. An apparatus according to claim 1, further comprising a terminating device formed by packaging a plurality of terminating resistors.
3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1
3, 14, 15, 16, 17, 18, 19, 20, 21
Or the electronic device according to 22. 24. A terminal device comprising a plurality of integrated terminating devices packaged with a plurality of terminating resistors and a plurality of integrated circuits arranged in a hierarchical manner using a substrate. Claims 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 13, 14, 15, 16, 17, 1
The electronic device according to 8, 19, 20, 21 or 22. 25. The electronic device according to claim 23, wherein said termination device has a reference voltage output terminal for outputting a termination voltage as a reference voltage. 26. The semiconductor device according to claim 2, further comprising a terminating device in which a plurality of terminating resistors and said second voltage generating circuit are packaged. 8,
9, 10, 11, 12, 13, 14, 15, 16, 1
The electronic device according to 7, 18, 19, 20, 21 or 22. 27. A terminating device in which a plurality of terminating resistors and the second voltage generating circuit are packaged, and a plurality of integrated circuits for inputting and outputting signals are hierarchically arranged using a substrate. 2. The method according to claim 1, wherein the first and second parts are integrated.
1, 12, 13, 14, 15, 16, 17, 18, 1
23. The electronic device according to 9, 20, 21 or 22. 28. The terminal device according to claim 26, wherein the termination device has a reference voltage output terminal for outputting the second voltage output from the second voltage generation circuit as a reference voltage.
Or the electronic device of 27. 29. The operational amplifier, wherein the first voltage is supplied as a power supply voltage, and a first differential amplifier circuit using first and second n-channel insulated gate field effect transistors as driving transistors; A first voltage is supplied as a power supply voltage, a second differential amplifier circuit using first and second p-channel insulated gate field effect transistors as driving transistors, and the first voltage is supplied as a power supply voltage. A third p-channel insulated gate field effect transistor forming a pull-up element driven by the first differential amplifier circuit and a third n-forming element forming a pull-down element driven by the second differential amplifier circuit An output circuit comprising a channel insulated gate field effect transistor;
A connection point between the gate of the channel insulated gate field effect transistor and the gate of the first p-channel insulated gate field effect transistor is defined by the first input terminal and the second
The connection point between the gate of the n-channel insulated gate field effect transistor and the gate of the second p-channel insulated gate field effect transistor is defined as the second input terminal, and the output terminal of the output circuit is defined as the output terminal. Claims 2, 3, 4, 5, 6, 7, 8,
9, 10, 11, 12, 13, 14, 15, 16, 1
7, 18, 19, 20, 21, 22, 23, 24, 2
29. The electronic device according to 5, 26, 27 or 28. 30. Terminating resistors at both ends of the bus line
The resistance value of one of the terminating resistors is set larger than the value of the effective characteristic impedance of the bus line and smaller than the value of the characteristic impedance of the bus line when no load is applied. 1, 2, 3, 4, 5, 6,
7, 8, 9, 10, 11, 12, 13, 14, 15, 1,
6, 17, 18, 19, 20, 21, 22, 23, 2,
The electronic device according to 4, 25, 26, 27, 28 or 29. 31. First, second, third... For inputting / outputting a signal.
..The n-th integrated circuit in this order and the second and third circuits
.. Connected to the bus line so that the n-th integrated circuit is connected at relatively small intervals, and the first and the n-th integrated circuits are connected to the first integrated circuit side and the n-th integrated circuit side of the bus line. In the electronic device comprising two terminal resistors, the second terminal resistor has a resistance value larger than an effective characteristic impedance value of a bus line and a characteristic impedance of the bus line at no load. An electronic device, wherein the value is set to a value smaller than the value. 32. An output circuit using a first p-channel insulated-gate field-effect transistor as a pull-up element, a first n-channel insulated-gate field-effect transistor as a pull-down element, and a second p-channel insulated-gate field-effect transistor. A first inverter driving the first p-channel insulated gate field effect transistor, wherein the first n-channel insulated gate field effect transistor is a pull-down element, and a third p-channel insulation. A second inverter that drives the first n-channel insulated-gate field-effect transistor, wherein the gate-type field-effect transistor is a pull-up element, the third n-channel insulated-gate field-effect transistor is a pull-down element, The first and second inverters are supplied to the output circuit. Integrated circuit power supply voltage source voltage and the same voltage, characterized in that it is configured to be supplied. 33. A power supply voltage to be supplied to said output circuit as a back bias voltage of said second and third p-channel insulated gate field effect transistors. Item 33. The integrated circuit according to Item 32. 34. An output circuit comprising: a first n-channel insulated gate field effect transistor having a pull-up element; and a second n-channel insulated gate field effect transistor having a pull-down element. The threshold voltage of the gate-type field-effect transistor is a low-level voltage or more of a signal output from the output circuit and lower than the threshold voltage of the second n-channel insulated-gate field-effect transistor. An integrated circuit characterized by the above. 35. A pull-up device comprising: a first n-channel insulated gate field effect transistor of a depletion type;
An output circuit using a second n-channel insulated-gate field-effect transistor of an enhancement type as a pull-down element, wherein a threshold voltage of the first n-channel insulated-gate field-effect transistor is a signal output from the output circuit. An integrated circuit characterized by a low level voltage or higher. 36. A terminating device characterized by being packaged including a plurality of terminating resistors. 37. A terminating device characterized by being packaged including a plurality of terminating resistors and a terminating voltage generating circuit. 38. The terminating device according to claim 36, further comprising a reference voltage output terminal for outputting a reference voltage. 39. The terminating device according to claim 36, 37 or 38, and a plurality of integrated circuits for inputting / outputting a signal are integrated by arranging them hierarchically using a substrate. Electronic devices. 40. An electronic device comprising a push-pull type output circuit, a plurality of integrated circuits for inputting / outputting signals, and a bus line shared by the plurality of integrated circuits. Between the terminal voltage line supplying voltage and the bus line,
A first nonlinear element having a rising characteristic is connected in a forward direction, and a second nonlinear element having a rising property is connected between the bus line and a voltage line supplying a voltage lower than the termination voltage in a forward direction. An electronic device, wherein a terminal is provided to prevent current from flowing when no signal is present on the bus line. 41. The electronic device according to claim 40, wherein said first and second nonlinear elements are diodes. 42. The electronic device according to claim 40, wherein said first and second nonlinear elements comprise a series circuit of a diode and a resistor. 43. The electronic device according to claim 40, wherein said first and second nonlinear elements are diode-connected insulated gate field effect transistors. 44. An n-channel insulation device, wherein the first nonlinear element has a drain connected to a termination voltage line for supplying a termination voltage, a source connected to the bus line, and a gate supplied with a first bias voltage. A gate type field effect transistor, wherein the second non-linear element has a source connected to the bus line, a drain connected to a voltage line supplying a voltage lower than the termination voltage, and a second bias voltage applied to the gate. 41. The electronic device according to claim 40, wherein the electronic device is a p-channel insulated gate field-effect transistor to which is supplied. 45. A value obtained by subtracting the second bias voltage from the first bias voltage is a threshold voltage of the first n-channel insulated gate field effect transistor and a threshold voltage of the second p-channel insulated gate field effect transistor. 46. The electronic device according to claim 44, wherein the sum of the threshold value and the absolute value of the threshold voltage of the effect transistor is smaller than the sum. 46. A first differential amplifier circuit using first and second n-channel insulated gate field effect transistors as drive transistors, and a first and second p-channel insulated gate field effect transistors as drive transistors. A second p-channel insulated gate field effect transistor serving as a pull-up element driven by the first differential amplifier circuit, and a second differential amplifier circuit driven by the second differential amplifier circuit A first output circuit comprising a third n-channel insulated-gate field-effect transistor forming a pull-down element, wherein a gate of the first n-channel insulated-gate field-effect transistor and the first p-channel insulation are provided. A connection point with the gate of the gate type field effect transistor is defined as a first input terminal,
A second input terminal connecting a connection point between the gate of the second n-channel insulated gate field effect transistor and the gate of the second p-channel insulated gate field effect transistor;
A first operational amplifier having an output terminal of the first output circuit as an output terminal; connecting an output terminal of the first operational amplifier to a first input terminal; a second operational amplifier of the first operational amplifier; A first bias voltage generating circuit for supplying a reference voltage to an input terminal and obtaining the first bias voltage at an output terminal of the second operational amplifier; a fourth and a fifth n-channel insulated gate type A third differential amplifier circuit using a field-effect transistor as a driving transistor; a fourth differential amplifier circuit using fourth and fifth p-channel insulated gate field-effect transistors as a driving transistor; A sixth p-channel insulated gate field effect transistor serving as a pull-up element driven by a dynamic amplifier circuit and a sixth n-channel insulation serving as a pull-down element driven by the fourth differential amplifier circuit A second output circuit comprising a gate type field effect transistor, wherein a connection point between a gate of the fourth n-channel insulated gate field effect transistor and a gate of the fourth p-channel insulated gate field effect transistor is provided. A first input terminal,
A second input terminal connecting a connection point between the gate of the fifth n-channel insulated gate field effect transistor and the gate of the fifth p-channel insulated gate field effect transistor;
A second operational amplifier having an output terminal of the second output circuit as an output terminal; connecting an output terminal of the second operational amplifier to a first input terminal; A reference voltage is supplied to an input terminal, and a bias voltage generating circuit including a second bias voltage generating circuit configured to obtain the second bias voltage is provided at an output terminal of the second operational amplifier. The electronic device according to claim 44 or 45, wherein: 47. An apparatus according to claim 40, further comprising a terminating device integrated including said first and second nonlinear elements. Electronic devices. 48. The apparatus according to claim 40, further comprising a terminating device integrated including said first and second nonlinear elements and a terminating voltage generating circuit.
47. The electronic device according to 44, 45 or 46. 49. The electronic device according to claim 47, wherein the terminal device has a reference voltage output terminal for outputting the reference voltage. 50. An integrated circuit comprising the terminating device according to claim 47, 48 and 49, and a plurality of integrated circuits for inputting and outputting signals, arranged in a hierarchical manner using a substrate. 41. A method according to claim 40, wherein
The electronic device according to 3, 44, 45 or 46. 51. A third nonlinear element having a rising characteristic is connected in a forward direction between a terminal voltage line for supplying a terminal voltage and the bus line, and a voltage lower than the bus line and the terminal voltage. A fourth non-linear element having a rising characteristic is connected in the forward direction to a voltage line for supplying the input signal, and a reference necessary for an input circuit is connected to a connection point between the third non-linear element and the fourth non-linear element. 41. A device for obtaining a voltage.
The electronic device according to 4, 45, 46, 47, 48, 49 or 50. 52. The input circuits of the plurality of integrated circuits have first and second loads connected at one end to a power supply line for supplying a power supply voltage, and a drain connected to the other end of the first load. ,
A first n-channel insulated gate field effect transistor having a gate connected to the source and a source connected to the reference voltage input terminal, a drain connected to the other end of the second load, and a gate connected to the first load; 2. The semiconductor device according to claim 1, further comprising a second n-channel insulated-gate field-effect transistor connected to the gate of the n-channel insulated-gate field-effect transistor and having a source connected to the signal input / output terminal. 40, 41, 42, 43, 44, 45,
The electronic device according to 46, 47, 48, 49, 50 or 51. 53. An electronic device according to claim 51, wherein said third and fourth nonlinear elements are diodes. 54. An electronic device according to claim 51, wherein said third and fourth non-linear elements comprise a series circuit of a diode and a resistor. 55. The electronic device according to claim 51, wherein said third and fourth nonlinear elements are diode-connected insulated gate field effect transistors. 56. A first nonlinear element having a rising characteristic to be connected in a forward direction between a termination voltage line supplying a termination voltage and a bus line, and supplying a voltage lower than the bus line and the termination voltage. And a second non-linear element having a rising characteristic to be connected in the forward direction between the terminal and the voltage line. 57. A first nonlinear element having a rising characteristic to be connected in a forward direction between a terminal voltage line supplying a terminal voltage and a bus line, and supplying a voltage lower than the bus line and the terminal voltage. A second nonlinear element having a rising characteristic to be connected in a forward direction between the second nonlinear element and a terminating voltage generating circuit. 58. The terminating device according to claim 56, wherein said first and second nonlinear elements are diodes. 59. The terminating device according to claim 56, wherein said first and second non-linear elements comprise a series circuit of a diode and a resistor. 60. A terminating device according to claim 56, wherein said first and second nonlinear elements are diode-connected insulated gate field effect transistors. 61. The first non-linear element should have a drain connected to a termination voltage line supplying a termination voltage,
An n-channel insulated-gate field-effect transistor whose source should be connected to the bus line and whose gate should be supplied with a first bias voltage; and wherein the second nonlinear element has a source connected to the bus. P-channel insulated gate type, the drain of which should be connected to a voltage line supplying a voltage lower than the termination voltage, and the gate of which should be supplied with a second bias voltage. The termination device according to claim 56 or 57, wherein the termination device is a field effect transistor. 62. A device according to claim 56, further comprising a reference voltage output terminal for outputting a reference voltage.
62. The termination device according to claim 59, 60 or 61. 63. Claims 56, 57, 58, 59, 60,
62. An electronic device, wherein the terminating device according to 61 or 62 and a plurality of integrated circuits for inputting / outputting signals are integrated by arranging them hierarchically using a substrate.