KR100924016B1 - Calibration circuit of On Die Termination Device - Google Patents

Abstract

The present invention relates to a calibration circuit of an on-die termination device that allows a constant current to flow during termination. The calibration circuit of the on-die termination device according to the present invention includes a calibration node to which a reference voltage and an external resistor are connected. A code generator configured to generate a pull-up calibration code in response to a voltage of; And a pull-up calibration resistor configured to pull-up the calibration node in response to the pull-up calibration code, and calibrated to have a larger resistance value as the power supply voltage increases.

On Die Termination, Calibration, Constant Current

Description

Calibration circuit of On Die Termination Device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a calibration circuit of an on die termination device used for impedance matching of input / output terminals in various semiconductor devices. It is about.

Various semiconductor devices implemented as integrated circuit chips, such as CPUs, memories and gate arrays, are incorporated into various electrical products such as personal computers, servers or workstations. In most cases, the semiconductor device has a receiving circuit for receiving various signals transmitted from the outside world through an input pad and an output circuit for providing an internal signal to the outside through an output pad.

Meanwhile, as the operating speed of an electrical product is increased, the swing width of a signal interfaced between the semiconductor devices is gradually reduced. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching (also referred to as mismatch) at the interface stage becomes more severe. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like. When impedance mismatching occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted. Therefore, when the semiconductor device on the receiving side receives the distorted output signal to the input terminal, problems such as setup / hold fail or input level determination error may occur frequently.

In particular, a memory device requiring high speed of operation employs an impedance matching circuit called on die termination in the vicinity of a pad in an integrated circuit chip to solve the above problems. In general, in an on die termination scheme, source termination is performed by an output circuit on the transmission side, and parallel termination is performed by a termination circuit connected in parallel to a receiving circuit connected to the input pad on the receiving side.

ZQ calibration refers to the process of generating pull-up and pull-down calibration codes that change as PVT (Process, Voltage, Temperature) conditions change, which is generated as a result of ZQ calibration. The above codes are used to adjust the resistance value of the on-die termination device (the termination resistance value on the DQ pad side in the case of a memory device) (using the ZQ node, which is a node for calibration, the calibration is performed. It is called ZQ calibration because it is done.)

Hereinafter, the ZQ calibration performed in the on die termination device will be described.

1 is a configuration diagram of a portion (calibration circuit) for performing a ZQ calibration operation in a conventional on-die termination device.

As shown in the figure, the conventional on-die termination device is a pull-up calibration resistor 110, a dummy calibration resistor 120, a pull-down calibration resistor 30, a reference voltage generator 102, Comparators 103 and 104 and counters 105 and 106 are included to perform a ZQ calibration operation. The pull-up calibration resistor unit 110 is configured to include a plurality of pull-up resistors that are turned on / off by receiving the pull-up calibration codes PCODE <0: N>. In addition, the dummy calibration resistor 120 is configured in the same manner as the pull-up calibration resistor 110, and the pull-down calibration resistor 130 receives the pull-down calibration code NCODE <0: N>. It consists of a number of pull-down resistors that receive inputs on and off.

The pull-up calibration resistor unit 110 is used to generate a primary calibration code (PCODE <0: N>) while calibrating with an external resistor 101 connected to a ZQ node, and a dummy calibration resistor. The unit 120 and the pull-down calibration resistor unit 130 may use a second calibration code (PCODE <0: N>) generated using the pull-up calibration resistor unit 110. To generate NCODE <0: N>).

In operation, a comparator 103 is formed by connecting an external resistor 101 (generally 240?) And a pull-up calibration resistor 110 connected to a ZQ pin (outside the chip of the ZQ node). The voltage of the ZQ node and the reference voltage generated by the internal reference voltage generator 102 (VREF, which is generally set to VDD / 2) are compared to generate an UP / DOWN signal.

The counter 105 receives the up / down signal UP / DOWN to generate a binary code PCODE <0: N>. The counter 105 generates a pull-up calibration resistor with the generated binary code PCODE <0: N>. Adjust the resistance value by turning on / off the resistors connected in parallel in 110). The resistance value of the adjusted pull-up calibration resistor unit 110 again affects the voltage of the ZQ node and the operation as described above is repeated. Since the calibration operation is performed until the voltage of the ZQ node is equal to the reference voltage (VREF = 1 / 2VDD), the total resistance value of the pull-up calibration resistor circuit 110 is determined by the external resistance 101 (generally, The pull-up calibration resistor circuit 110 is calibrated to be equal to the resistance value of 240?) (Pull-up calibration).

The binary code (PCODE <0: N>, pull-up calibration code) generated during the above-described pull-up calibration process is input to the dummy calibration resistor 120 and the entire dummy calibration resistor 120 The resistance value is determined (finally the dummy calibration resistor circuit has the same resistance value as the pull-up calibration resistor circuit). The pull-down calibration operation now begins, similar to the pull-up calibration, using the comparator 104 and the counter 106 so that the voltage at node a equals the reference voltage (VREF), that is, the pull-down calibration resistor. The total resistance value of the unit 130 is calibrated to be equal to the total resistance value of the dummy calibration resistance unit 120 (pull-down calibration).

The binary codes PCODE <0: N> and NCODE <0: N> generated as a result of the above-described ZQ calibration (pull-up and pull-down calibration) are the pull-up and pull-down of the calibration circuit of FIG. The resistance value of the die termination device input to the pull-up and pull-down resistors (termination resistors) on the input / output pad side laid out in the same manner as the calibration resistors 110 and 130 is determined. The pullup and pulldown termination resistors on the DQ pad side.

FIG. 2 determines a termination resistance value of an output driver (termination circuit) of a semiconductor memory device using calibration codes PCODE <0: N> and NCODE <0: N> generated by the calibration circuit of FIG. 1. It is a figure which shows.

The output driver outputs data from the semiconductor memory device, and as shown in the figure, pre-drivers 210 and 220 provided for up / down and pull-up termination resistors for outputting data ( 230 and a pull-down termination resistor 240.

In brief, the pre-drivers 210 and 220 provided in the up / down control the pull-up termination resistor 230 and the pull-down termination resistor 240, respectively. When the resistor unit 230 is turned on to make the data pin DQ high, and the output low data, the pull-down termination resistor 240 is turned on to bring the data pin DQ low. Make. In other words, the data pin DQ is terminated by pull-up or pull-down to output 'high' or 'low' data.

At this time, the number of resistors in the pull-up termination resistor 230 and the pull-down termination resistor 240 that are turned on are the pull-up calibration code (PCODE <0: N>) and the pull-down calibration code (NCODE <0: N>). Determined by That is, whether the pull-up termination resistor 230 is turned on or the pull-down termination resistor 240 is turned on depends on the logic state of the output data, but each resistor in the turned-on termination resistor 230 or 240 is turned on. The on / off of is determined by the calibration codes PCODE <0: N> and NCODE <0: N>.

For reference, a resistance value target value of the pull-up termination resistor circuit 230 and the pull-down termination resistor circuit 230 must be equal to the resistance value 240Ω of the calibration resistor unit 110, 120, and 130 of FIG. 1. It may not have the same value, but may have values such as 120Ω, 60Ω, which are 1/2 and 1/4 of 240Ω, and the termination resistance parts 240, 120, and 60 may be different depending on the applied system. It is also possible to adopt the method of having all of them) and using them selectively.

DQp_CTRL and DQn_CTRL input to the predrivers 210 and 220 of the drawing represent a group of control signals input to the predrivers 210 and 220.

The output driver (FIG. 2, termination circuit of the on-die termination device) uses its own calibration code (PCODE <0: N>, NCODE <0: N>) generated by the calibration circuit (FIG. 1). Since the termination resistance values (resistance values 230 and 240 in Fig. 2) are determined, constant resistance values are always maintained.

If the power supply voltage VDD is changed while the termination resistance value (the resistance values 230 and 240 of FIG. 2) is constant, the amount of current flowing through the input / output node DQ also changes. For example, if the power supply voltage VDD is doubled while the termination resistance value (230 and 240 in FIG. 2) is constant, the current amount of the input / output node DQ is also doubled. If (VDD) decreases in half, the amount of current also decreases in half.

According to the calibration result, the termination resistance value (resistance value of 230 and 240 in FIG. 2) maintains a constant resistance value regardless of the change of PVT. This is the purpose of ZQ calibration, but the semiconductor device is applied. Depending on the system, the amount of current flowing through the input / output node DQ may be required to be constant rather than the termination resistance value (the resistance values 230 and 240 of FIG. 2). Therefore, a technology that can satisfy these needs is required.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and keeps the current amount of the input / output node constant even if the power supply voltage changes, so as to meet the requirements of the system (requires constant current amount). An object of the present invention is to provide a calibration circuit of an on-die termination device.

The calibration circuit of the on-die termination device according to an embodiment of the present invention (when generating a pull-up calibration code), the pull-up calibration in response to the voltage of the calibration node connected to the reference voltage and the external resistance Code generation unit for generating a code; And a pull-up calibration resistor configured to pull-up the calibration node in response to the pull-up calibration code, and calibrated to have a larger resistance value as the power supply voltage increases.

The pull-up calibration resistor unit is calibrated to have a resistance value equal to the external resistance when the power supply voltage is equal to a predetermined voltage, and to have a resistance value greater than the external resistance when the power supply voltage is higher than the predetermined voltage. When the power supply voltage is lower than the predetermined voltage may be calibrated to have a resistance value smaller than the external resistance.

The reference voltage may have a value of the power supply voltage * 1 / N (N is a natural number of 1 or more), and the value of N may be increased as the power supply voltage increases.

The calibration circuit of the on-die termination device according to another embodiment of the present invention generates a pull-up calibration code in response to a voltage of a calibration node connected with a first reference voltage and an external resistor, and generates a second reference voltage. A code generator configured to generate a pull-down calibration code in response to voltages of the A node and the A node; A pull-up calibration resistor unit configured to pull-up the calibration node in response to the pull-up calibration code and to be calibrated to have a larger resistance value as the power supply voltage increases; A dummy calibration resistor configured to pull-up the node A in response to the pull-up calibration code and to be calibrated to have the same resistance value as the pull-up calibration resistor; And a pull-down calibration resistor configured to pull-down the A node in response to the pull-down calibration code and to be calibrated to have the same resistance value as that of the dummy calibration resistor.

The pull-up calibration resistor unit is calibrated to have a resistance value equal to the external resistance when the power supply voltage is equal to a predetermined voltage, and to have a resistance value greater than the external resistance when the power supply voltage is higher than the predetermined voltage. When the power supply voltage is lower than the predetermined voltage may be calibrated to have a resistance value smaller than the external resistance.

The first reference voltage may have a value of the power supply voltage * 1 / N (N is a natural number of 1 or more), and the value of N may be increased as the power supply voltage increases.

According to the present invention, when the power supply voltage is increased, the calibration resistors (like all the calibration resistors) of the calibration circuit are calibrated to have a larger resistance value than the external resistance, and when the power supply voltage is lowered, the calibration is performed. The resistor unit is calibrated to have a smaller resistance value than the external resistor.

Accordingly, the termination resistor of the termination circuit (eg, the output driver) also has a large resistance value when the power supply voltage is high and a small resistance value when the power supply voltage is low. Therefore, even if the power supply voltage changes, a constant amount of current can always flow through the input / output node.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a configuration diagram of a calibration circuit of an on die termination apparatus according to an embodiment of the present invention (generating only one calibration code).

As shown in the figure, the calibration circuit according to the present invention, the pull-up calibration code (PCODE <) in response to the voltage of the calibration node (ZQ) to which the reference voltage (VREF_ZQ) and the external resistor (301) is connected. 0: N>) to generate a code generation unit 320; And a calibration resistor that pulls up the calibration node ZQ in response to the pull-up calibration code PCODE <0: N> and is calibrated to have a larger resistance value as the power supply voltage VDD is higher. It is configured to include a portion 330. The reference voltage generator 310 for supplying the reference voltage VREF_ZQ to the calibration circuit 320 + 330 may be provided inside or outside the calibration circuit.

3 shows a calibration circuit in the case of generating only the pull-up calibration code PCODE <0: N>, which means that the calibration circuit always has two calibration codes PCODE <0: N>, NCODE <0: N>) is not generated. In the case of terminating the input / output node (DQ) only by the pull-up in the termination circuit, the pull-up calibration code (PCODE <0: N>) only needs to be generated in the calibration circuit. For example, in the case of graphics DRAM, the input / output node (DQ) is terminated only by pull-up when receiving data.

The code generator 320 generates a pull-up calibration code PCODE <0: N> in response to the reference voltage VREF_ZQ and the voltage of the calibration node as in the related art. The code generator 320 may include a comparator 321 comparing the voltage of the reference voltage VREF_ZQ and the calibration node ZQ, and a pull-up calibration code PCODE <0 in response to the output of the comparator 321. And a counter 322 counting: N>).

The pull-up calibration resistor unit 330 internally turns on / off parallel resistors in response to the pull-up calibration code PCODE <0: N> and pulls up the calibration node ZQ. Conventional pull-up calibration resistors are always calibrated to have the same resistance as the external resistors, but the pull-up calibration resistors 330 of the present invention have a larger resistance value as the power supply voltage VDD increases. It is characterized in that the transition.

Therefore, if the power supply voltage VDD is equal to the predetermined voltage based on the predetermined voltage, the device is calibrated to have the same resistance value as the external resistor 301. If the power supply voltage VDD is higher than the predetermined voltage, In order to have a resistance value, when the power supply voltage VDD is lower than the predetermined voltage, it is calibrated to have a resistance value smaller than the external resistance 301. Since the pull-up calibration resistor unit 330 is calibrated in this manner, the predetermined voltage is used to change the termination resistance value when the power supply voltage VDD deviates from the stable steady state level (ie, shakes). It is preferable that the voltage VDD is at the same level as the voltage which is in a steady state (stable state).

Since the pull-up calibration resistor unit 330 of the calibration circuit is higher than the external resistor 301 because the power supply voltage VDD is high, the pull-up calibration code PCODE <0: N>) is generated in the direction of making the resistance value larger. Therefore, the pull-up termination resistor of the termination circuit configured in the same manner as the pull-up calibration resistor 330 and receiving the same pull-up calibration code PCODE <0: N> also has a larger resistance value than the conventional one. Therefore, even if the power supply voltage VDD increases, the termination resistance value also increases, so that the amount of current flowing through the input / output node DQ can be kept constant.

On the contrary, when the pull-up calibration resistor 330 is calibrated to a value smaller than the external resistor 301 because the power supply voltage VDD is low, the pull-up termination resistor of the termination circuit also has a smaller resistance value than the conventional one. Even if the voltage VDD decreases, the termination resistance value also decreases accordingly, so that the amount of current flowing through the input / output node DQ can be kept constant.

As described above, in the present invention, when the power supply voltage VDD maintains the normal voltage level, the pull-up calibration resistor unit 330 is calibrated to the same resistance value as the external resistor 301. The pull-up calibration resistor unit 330 is calibrated to a value greater than the external resistor 301 when the voltage level is greater than the steady state. When the power supply voltage VDD is smaller than the voltage level in the steady state, the pull-up calibration is performed. The resistor 330 is to be calibrated to a value smaller than the external resistor 301 is the key.

As described above, the pull-up calibration resistor unit 330 may be calibrated by generating the reference voltage VREF_ZQ unlike the related art. Because the calibration operation in the calibration circuit counts the pull-up calibration code (PCODE <0: N>) until the voltage at the reference voltage (VREF_ZQ) and the calibration node (ZQ) are equal. to be.

4 is a diagram showing the level of the reference voltage VREF_ZQ in the present invention.

Since the conventional reference voltage VREF has always maintained the level of the power supply voltage VDD * 1/2, even if the power supply voltage VDD fluctuates, the pull-up calibration resistor section 110 of FIG. , 301 was calibrated to have the same resistance value.

However, as shown in the drawing, the reference voltage VREF_ZQ according to the present invention is preferably the power supply voltage VREF is a predetermined voltage (as described above, the predetermined voltage is a voltage level of the reference voltage in the steady state. At the same level, the power supply voltage VDD * 1/2 is smaller, but when the power supply voltage VDD is higher than the steady state voltage, the power supply voltage VDD * 1/2 is smaller than the power supply voltage VDD * 1/2.

The calibration operation is a process of causing the voltage of the calibration node ZQ to follow the level of the reference voltage VREF_ZQ, so if the level of the reference voltage VREF_ZQ is less than the power supply voltage VDD * 1/2, it is pulled up. The calibration resistor unit 330 is calibrated to a larger value than the external resistor 301. For example, when the level of the reference voltage VREF_ZQ is the power supply voltage VDD * 2/5, the resistance ratio of the calibration resistor unit 330: the external resistor 301 is 3: 2.

In addition, when the level of the power supply voltage VDD is lower than the level of the steady state voltage, the reference voltage VREF_ZQ of the present invention becomes larger than the power supply voltage VDD * 1/2. Therefore, the pull-up calibration resistor 330 is calibrated to a smaller value than the external resistor 301. For example, when the level of the reference voltage VREF_ZQ is the power supply voltage VDD * 3/5, the resistance ratio of the calibration resistor unit 330: the external resistor 301 is 2: 3.

That is, the reference voltage VREF_ZQ of the present invention does not simply have a value of power supply voltage VDD * 1/2, but has a value of power supply voltage VDD * 1 / N (N is a natural number of 1 or more). Is larger as the power supply voltage VDD is increased. In detail, when power supply voltage VDD = steady state voltage, N = 2, but when the power supply voltage VDD becomes smaller than the steady state voltage, the N value becomes smaller and smaller when the power supply voltage VDD becomes larger than the steady state voltage. The value is getting bigger.

FIG. 5 is a diagram of one embodiment of a reference voltage generator 310 generating the reference voltage VREF_ZQ as shown in FIG. 4.

The reference voltage VREF_ZQ as shown in FIG. 4 is generated by connecting the output of the bandgap circuit 510 for generating a constant voltage and the output of the voltage distribution circuit 520 for voltage-dividing and outputting the power supply voltage VDD. can do.

First, the bandgap circuit 510 used to generate a constant voltage will be described.

The bandgap circuit 510 uses a vertical PNP BJT transistor with little change in process. This is done by creating a Proportional to Absolute Temperature (PTAT) term that increases the amount of current flowing with temperature and a Complementary proportional to Absolute Temperature (CTAT) term that decreases the amount of current flowing with temperature.

In this circuit, the formula for a typical diode current versus voltage expressed as the emitter current of two BJTs (Q1, Q2) with a ratio of N: 1 under the assumption that node A and node B are virtually shorted is: .

Applying this to Q1 and Q2, respectively, is as follows.

,

,

Where I _Q1 and I _Q2 are the emitter currents flowing through each BJT.

If the potential of node A and node B is the same, the IPTAT current flowing through the resistor R1 is as follows.

And under the same circumstances, the ICTAT current flowing through the R2 resistor is the same.

Assuming the same amount of current flows through the same size MOS, the currents of M * IPTAT and K * ICTAT become M * IPTAT and K * ICTAT as indicated.

Based on this, the output voltage VREF_ZQ of the bandgap circuit 510 is expressed as follows (assuming that there is no voltage divider circuit on the right side).

VREF_ZQ = K · R3 / R2 · {V _BE1 + (M · R2) / (K · R1) · ln (N · α) · V _T }

By properly adjusting the values of M, R1, R2, R3, K, and M so that temperature compensation occurs, the output VREF_ZQ will have a constant value for the PVT change. In general, the N, R1, R2, and R3 values are fixed and only the K and M values are adjusted to adjust the amount of current in PTAT and CTAT.

That is, the band gap circuit alone outputs a constant voltage.

In addition, when only the voltage distribution circuit 520 is present, the output VREF_ZQ = VDD * (R5 / (R4 + R5)) of the voltage distribution circuit 520 becomes.

And now if you think that the bandgap circuit and the voltage distribution circuit are connected and set up the current formula in the VREF_ZQ stage,

VREF_ZQ = {(R3 · R5) / (R3 + R5)} · (K / R2) · (V _BE1 + ((M · R2) / (K · R1)) · ln (N · α) · V _T + VDD / (R4 + R5)}.

In simpler terms, VREF_ZQ = A + B * VDD. That is, by adjusting the constant values of the above equation, the reference voltage VREF_ZQ of the present invention as shown in FIG. 4 can be generated.

To sum up the principle, as a result of connecting the bandgap circuit 510 for generating a constant constant voltage A and the voltage distribution circuit for voltage division (B * VDD) of the power supply voltage VDD, the line A as shown in FIG. A reference voltage VREF_ZQ is generated which draws + B * VDD.

When the power supply voltage VDD is very low (left side of FIG. 4), the level of the reference voltage VREF_ZQ is formed equal to the power supply voltage VDD is that the reference voltage VREF_ZQ is also made using the power supply voltage VDD. This is because the reference voltage VREF_ZQ cannot be higher than the level of the power supply voltage VDD.

6 is a block diagram of a calibration circuit of an on die termination device according to another embodiment of the present invention (both generation of calibration codes).

As shown in the figure, the calibration circuit according to the present invention, in response to the voltage of the calibration node (ZQ) connected to the first reference voltage (VREF_ZQ) and the external resistor (601) pull-up calibration code ( A code generator 630 for generating PCODE <0: N> and generating a pull-down calibration code NCODE <0: N> in response to the second reference voltage VREF and the voltage of the A node; A pull-up calibration is performed to pull up the calibration node ZQ in response to the pull-up calibration code PCODE <0: N> and to have a larger resistance value as the power supply voltage VDD increases. Resistance unit 640; A dummy calibration resistor 650 that pulls up node A in response to the pull-up calibration code PCODE <0: N> and is calibrated to have the same resistance value as that of the pull-up calibration resistor 640. ); And a pull-down calibration resistor unit that is pulled-down in response to the pull-down calibration code NCODE <0: N> and is calibrated to have the same resistance value as the dummy calibration resistor 650. 660).

The reference voltage generators 610 and 620 for supplying the first reference voltage VREF_ZQ and the second reference voltage VREF to the calibration circuit may be provided inside or outside the calibration circuit.

The code generator 630 generates a pull-up calibration code PCODE <0: N> in response to the voltages of the first reference voltage VREF_ZQ and the calibration node ZQ, and the second reference voltage VREF. And a pull-down calibration code (NCODE <0: N>) in response to node A and voltage of node A. The code generator 630 replies to the output of the first comparator 631 and the first comparator 631 to compare the voltage of the first reference voltage VREF_ZQ and the calibration node ZQ. To the outputs of the first and second comparators 633 and 633 comparing the voltage of the first node 632, the second reference voltage VREF, and the A node, which counts the codes PCODE <0: N>. It may be configured to include a second counter 634 in response to counting the pull-down calibration code (NCODE <0: N>).

The pull-up calibration resistor 640 is configured in the same manner as the pull-up calibration resistor 330 of FIG. 3 and has the same characteristics. Since this has been described in detail in the foregoing embodiment, further description will be omitted here.

The dummy calibration resistor 650 also receives the same code (PCODE <0: N>) as the pull-up calibration resistor 640 and is configured identically, so the same resistance as that of the pull-up calibration resistor 640. Has a value. Originally, the dummy calibration resistor 650 itself generates a pull-down calibration code (NCODE <0: N>) by pull-up driving the A node while copying the pull-up calibration resistor 640 as it is. It is natural that the dummy calibration resistor 650 has the same characteristics as the pull-up calibration resistor 640 because it is possible to do so.

The pulldown calibration resistor unit 660 is calibrated to have the same resistance value as the dummy calibration resistor unit 650 as in the related art. That is, the resistance value of the pull-up calibration resistor 640 = the resistance value of the dummy calibration resistor 650 = the resistance of the pull-down calibration resistor 660. As the pull-up calibration resistor unit 640 is calibrated to have a larger resistance value as the power supply voltage VDD increases as described above in detail with reference to FIG. 3, the pull-up calibration resistor unit 650 and the remaining dummy calibration resistor unit 650 are pulled down. The calibration resistor unit 660 is also calibrated to have a larger resistance value as the power supply voltage VDD increases.

The first reference voltage VREF_ZQ is a reference voltage used to generate the pull-up calibration codes PCODE <0: N> and is the same reference voltage as the reference voltage VREF_ZQ used in FIG. 3. That is, they have the same level as shown in FIG. 4 and are generated through the reference voltage generator 610 = FIG. 5 as shown in FIG.

The second reference voltage VREF is simply a reference voltage having a level of VDD * 1/2 as in the related art. Since the pull-up calibration resistor 640 is already calibrated to have a larger resistance value as the power supply voltage VDD increases, the remaining dummy calibration resistor 650 and the pull-down calibration resistor ( This is because the calibration method of 660 may be the same as in the related art.

In summary, the embodiment of FIG. 6 may be regarded as a configuration for generating the original pull-down calibration code from the embodiment of FIG. 3. If only the pull-up calibration resistor 640 is already calibrated as described with reference to FIG. 3, the remaining calibration resistors 650 and 660 are also calibrated in the same manner. Can be achieved.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a block diagram of a portion (calibration circuit) for performing a ZQ calibration operation in a conventional on-die termination device.

FIG. 2 determines a termination resistance value of an output driver (termination circuit) of a semiconductor memory device using calibration codes PCODE <0: N> and NCODE <0: N> generated by the calibration circuit of FIG. 1. Drawing to show.

3 is a block diagram of a calibration circuit of an on die termination apparatus according to an embodiment of the present invention (generating only one calibration code).

4 is a diagram showing the level of the reference voltage VREF_ZQ in the present invention.

FIG. 5 is a diagram of one embodiment of a reference voltage generator 310 for generating a reference voltage VREF_ZQ as shown in FIG. 4.

6 is a block diagram of a calibration circuit of an on die termination device according to another embodiment of the present invention (both generation of calibration codes).

Claims (5)

A code generator configured to generate a pull-up calibration code in response to a voltage of a calibration node connected with a reference voltage and an external resistor; And A pull-up calibration resistor configured to pull-up the calibration node in response to the pull-up calibration code, and calibrated to have a larger resistance value as the power supply voltage increases, And the reference voltage has a value of the power supply voltage * 1 / N (N is a natural number of 1 or more), and the value of N increases as the power supply voltage increases. The method of claim 1, The pull-up calibration resistor unit, If the power supply voltage is the same as the predetermined voltage is calibrated to have the same resistance value as the external resistance, An on-die termination device characterized in that the power supply voltage is higher than the predetermined voltage so as to have a resistance value greater than the external resistance; Calibration circuit. The method of claim 1, The reference voltage is, If the power supply voltage is equal to a predetermined voltage, the power supply voltage has a value of 1/2. When the power supply voltage is higher than the predetermined voltage, the power supply voltage has a value smaller than 1/2 of the power supply voltage. And the power supply voltage has a value greater than the power supply voltage * 1/2 when the power supply voltage is lower than the predetermined voltage. The method of claim 2 or 3, The level of the predetermined voltage, And a voltage level of said power supply voltage in a steady state. The method of claim 1, The reference voltage is, And an output of a bandgap circuit for generating a constant voltage and an output of a voltage distribution circuit for dividing and outputting the power supply voltage.

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