KR20090022043A - Calibration circuit for on die termination device - Google Patents

Calibration circuit for on die termination device Download PDF

Info

Publication number
KR20090022043A
KR20090022043A KR1020070087069A KR20070087069A KR20090022043A KR 20090022043 A KR20090022043 A KR 20090022043A KR 1020070087069 A KR1020070087069 A KR 1020070087069A KR 20070087069 A KR20070087069 A KR 20070087069A KR 20090022043 A KR20090022043 A KR 20090022043A
Authority
KR
South Korea
Prior art keywords
calibration
reference voltage
code
node
voltage
Prior art date
Application number
KR1020070087069A
Other languages
Korean (ko)
Inventor
윤태식
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020070087069A priority Critical patent/KR20090022043A/en
Publication of KR20090022043A publication Critical patent/KR20090022043A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0005—Modifications of input or output impedance
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

A calibration circuit of an on die termination device is provided to change a calibration code by controlling a level of a reference voltage by a control signal. A reference voltage generating part(310) outputs a reference voltage in response to one or more control signal. A code generating part(320) generates one or more calibration code in response to the reference voltage and a voltage of one or more calibration node, and includes a comparator, a counter, and a calibration resistance part. The comparator(321) compares the calibration node with the reference voltage. The counter(322) counts the calibration code according to a compared result of the comparator. The calibration resistance part(323) is connected to the calibration node. A resistance value of the calibration resistance part is determined by an inputted calibration code.

Description

Calibration circuit for On Die Termination Device

The present invention relates to an on-die termination device used for impedance matching in various semiconductor integrated circuits such as a semiconductor memory device, and more particularly, to easily correct an error occurring in the on-die termination device.

Various semiconductor devices implemented as integrated circuit chips, such as CPUs, memories and gate arrays, are incorporated into various electrical products such as personal computers, servers or workstations. In most cases, the semiconductor device has a receiving circuit for receiving various signals transmitted from the outside world through an input pad and an output circuit for providing an internal signal to the outside through an output pad.

Meanwhile, as the operating speed of an electrical product is increased, the swing width of a signal interfaced between the semiconductor devices is gradually reduced. The reason is to minimize the delay time for signal transmission. However, as the swing width of the signal decreases, the influence on external noise increases, and the reflection of the signal due to impedance mismatching (also referred to as mismatch) at the interface stage becomes more severe. The impedance mismatch occurs due to external noise, fluctuations in power supply voltage, change in operating temperature, change in manufacturing process, or the like.

When impedance mismatching occurs, high-speed data transfer is difficult and output data output from the data output terminal of the semiconductor device may be distorted. Therefore, when the semiconductor device on the receiving side receives the distorted output signal to the input terminal, problems such as setup / hold fail or input level determination error may occur frequently.

In particular, a memory device requiring high speed of operation employs an impedance matching circuit called on die termination in the vicinity of a pad in an integrated circuit chip to solve the above problems. In general, in an on die termination scheme, source termination is performed by an output circuit on the transmission side, and parallel termination is performed by a termination circuit connected in parallel to a receiving circuit connected to the input pad on the receiving side.

ZQ calibration refers to a process of generating pull-up and pull-down codes that change as the PVT (Process, Voltage, Temperature) process changes. The ZQ calibration results from the ZQ calibration. The codes are used to adjust the resistance value of the on-die termination device (the termination resistance on the DQ pad side in the case of memory devices) (since calibration is performed using the ZQ node, which is a node for calibration). It is called ZQ calibration.)

Hereinafter, the ZQ calibration performed in the on die termination device will be described.

1 is a configuration diagram of a calibration circuit for performing a ZQ calibration operation in a conventional on-die termination device.

As shown in the drawing, the conventional on-die termination device includes a first calibration resistor 110, a dummy calibration resistor 120, a second calibration resistor 130, and a reference voltage generator ( 102), the comparators 103 and 104, and the counters 105 and 106 to perform a ZQ calibration operation. The first calibration resistor unit 110 is configured to include a plurality of pull-up resistors that are turned on / off by receiving a pull-up calibration code PCODE <0: N>. The dummy calibration resistor 120 is configured in the same manner as the first calibration resistor 110, and the pull-down calibration resistor 130 has a pull-down calibration code NCODE <0: N>. It is configured to include a plurality of pull-down resistors that are input on and off.

The first calibration resistor unit 110 is to generate a first calibration code PCODE <0: N> while being calibrated with the external resistor 101 connected to the ZQ node. The calibration resistor 130 uses a calibration code PCODE <0: N> generated through the first calibration resistor 110 to generate a second calibration code NCODE <0: N>. To generate the. In the process, the dummy calibration resistor 120 having the same resistance value as the first calibration resistor 110 is used.

In operation, a comparator 103 is generated by connecting an external resistor 101 (generally 240?) Connected to a ZQ pin (outside the chip of the ZQ node) and the first calibration resistor 110. The voltage of the ZQ node and the reference voltage (VREF, generally set to VDDQ / 2) generated by the internal reference voltage generator 102 are compared to generate an UP / DOWN signal.

The pull-up counter 105 receives the up / down signal and generates a binary code PCODE <0: N>, and the first calibration resistor unit 110 generates the binary code PCODE <0: N>. Adjust the resistance value by turning on / off the resistors connected in parallel. The adjusted resistance value of the first calibration resistor 110 affects the voltage of the ZQ node again, and the operation as described above is repeated. That is, the first calibration resistor 110 is calibrated so that the total resistance of the first calibration resistor 110 is equal to the resistance of the external resistor 101 (typically 240 Ω). (Pull-up calibration)

The binary code (PCODE <0: N>, pull-up calibration code) generated during the above-described pull-up calibration process is input to the dummy calibration resistor 120 and the whole of the pull-up calibration resistor 120 The resistance value is determined (the first calibration resistor section has the same resistance value as the external resistor). The pull-down calibration operation now starts, similar to the pull-up calibration, using the comparator 104 and the pull-down counter 106 so that the voltage at node a equals the reference voltage (VREF), i.e., the second calibration curve. The total resistance of the resistance unit 130 is calibrated to be equal to the total resistance of the dummy calibration resistance unit 120. (Pull-down calibration)

The binary codes PCODE <0: N> and NCODE <0: N> generated as a result of the above-described ZQ calibration (pull-up and pull-down calibration) are the pull-up and pull-down of the calibration circuit of FIG. The resistance value of the die termination device input to the pull-up and pull-down resistors (termination resistors) on the input / output pad side laid out in the same way as the calibration resistor unit is determined. Determine pull-up and pull-down termination resistors)

For reference, in the above-described conventional technique, both the pull-up and pull-down calibration are performed to generate a die termination for generating a pull-up calibration code (PCODE <0: N>) and a pull-down calibration code (NCODE <0: N>). Although the case of determining the resistance values of the pull-up termination resistors and pull-down termination resistors of the device has been described, the on-die termination device does not always include both the pull-up termination resistors and the pull-down termination resistors.

For example, in the case of a semiconductor memory device, both a pull-up termination resistor and a pull-down termination resistor are used on the output driver side, but only a pull-up termination resistor is used on the input buffer side.

Therefore, when the on-die termination device is composed of only a pull-up termination resistor on the input / output pad side, the pull-up which is a part for generating the pull-up calibration code (PCODE <0: N>) also in the calibration circuit of FIG. It is sufficient to consist only of the calibration resistor part 110, the counter 105, and the comparator 103. And the operation at that time is the same as the pull-up calibration process described above.

FIG. 2 illustrates an example in which an on die termination device is applied to a semiconductor memory device, using calibration codes PCODE <0: N> and NCODE <0: N> generated by the calibration circuit of FIG. 1. The figure which shows the determination of the termination resistance value of an output driver.

That is, an example is shown in which the calibration circuit of the on die termination device is shown in FIG. 1 and the termination circuit of the on die termination device is an output driver (FIG. 2).

The output driver outputs data from the semiconductor memory device, and as shown in the figure, pre-drivers 210 and 220 provided for up / down and pull-up termination resistors for outputting data ( 230 and a pull-down termination resistor 240.

In brief, the pre-drivers 210 and 220 provided in the up / down control the pull-up termination resistor 230 and the pull-down termination resistor 240, respectively. When the resistor unit 230 is turned on to make the data pin DQ high, and the output low data, the pull-down termination resistor 240 is turned on to bring the data pin DQ low. Make. In other words, the output is 'high' or 'low' by terminating by pull-up or pull-down.

At this time, the number of resistors in the pull-up termination resistor 230 and the pull-down termination resistor 240 that are turned on are the pull-up calibration code (PCODE <0: N>) and the pull-down calibration code (NCODE <0: N>). Determined by That is, whether the pull-up termination resistor 230 is turned on or the pull-down termination resistor 240 is turned on depends on the logic state of the output data, but one resistor in the turned-on termination resistor 230 or 240 is turned on. One on / off is determined by the calibration codes PCODE <0: N> and NCODE <0: N>.

For reference, the target values of the pull-up termination resistor 230 and the pull-down termination resistor 240 must be the same as the resistance values 240Ω of the calibration resistors 110, 120, and 130 of FIG. 1. Alternatively, it may have a value of 120Ω, 60Ω, etc., which is 1/2 or 1/4 of 240Ω. DQp_CTRL and DQn_CTRL input to the predrivers 210 and 220 of the drawing represent a group of control signals input to the predrivers 210 and 220.

The ZQ calibration operation of the on-die termination device described above has no mismatch between the calibration resistors (110, 120, and 130 of FIG. 1) and the termination resistors 230 and 240, and provides a resistance value at a constant ratio. Based on the assumption that you can make it bigger or smaller.

However, there is a mismatch between the resistors due to process variation, etc., and the offset of the comparator in the calibration circuit, the noise of the supply voltage, the line loading, the pad Many factors, such as pad and package resistance, can cause the termination resistor to have no target value. If the termination resistors do not have the desired resistance value, distortion of the input / output data may occur.

In addition, the value of the reference voltage VREF may fluctuate due to a process, temperature, etc., and thus the termination resistor may not have the target resistance value.

The present invention has been proposed to solve the above-mentioned problems of the prior art, and an object thereof is to provide an on-die termination device that easily corrects errors caused by various factors.

The calibration circuit of the on-die termination device according to an embodiment of the present invention for achieving the above object, the reference voltage generator for outputting a reference voltage whose level is adjusted in response to one or more control signals; And a code generator configured to generate one or more calibration codes in response to the reference voltage and the voltages of one or more calibration nodes.

In addition, the calibration circuit of the on-die termination apparatus according to another embodiment of the present invention, the first reference voltage generator for outputting a first reference voltage whose level is adjusted in response to one or more first control signals; A second reference voltage generator configured to output a second reference voltage whose level is adjusted in response to at least one second control signal; And generating a first calibration code in response to the first reference voltage and the voltage of the first calibration node, and generating a second calibration code in response to the voltage of the second reference voltage and the second calibration node. It includes a code generator for generating code.

In the present invention, the level of the reference voltage is changed by the control signal. Since the calibration code is generated by comparing the level of the reference voltage with the voltage level of the calibration node, it is possible to change the calibration code by changing the reference voltage by the control signal.

The calibration circuit of the on-die termination device according to the present invention includes at least one reference voltage generator for outputting a reference voltage whose level changes in accordance with a control signal. Therefore, by adjusting the level of the reference voltage by the control signal, it is possible to change the generated calibration code, thereby making it possible to easily correct the error occurring in the on-die termination device.

DETAILED DESCRIPTION Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a configuration diagram of a calibration circuit of an on die termination device according to an embodiment of the present invention.

The on-die termination device according to an embodiment of the present invention, the reference voltage generator 310 for outputting a reference voltage (VREF) whose level is adjusted in response to one or more control signals (TM1, 2, 3, 4), And a code generator for generating one or more calibration codes PCODE <0: N> and NCODE <0: N> in response to the reference voltage VREF and the voltages of one or more calibration nodes ZQ and A. And 320.

The reference voltage generator 310 does not always output the reference voltage VREF having a constant level, and generates the reference voltage VREF to which the voltage level is changed according to the control signals TM1, 2, 3, and 4. do.

The code generator 320 may include a first comparator 321 comparing the first calibration node ZQ and the reference voltage VREF; A first counter 322 counting a first calibration code PCODE <0: N> according to a comparison result of the first comparator 321; A first calibration resistor unit 323 that receives a first calibration code PCODE <0: N> to determine its resistance value and is connected to the first calibration node ZQ; A dummy calibration resistor unit 324 connected to the second calibration node A to determine its resistance by receiving the first calibration code PCODE <0: N>; A second comparator 325 for comparing the second calibration node A with the reference voltage VREF; A second counter 326 that counts a second calibration code NCODE <0: N> according to a comparison result of the second comparator 325; And receiving a second calibration code NCODE <0: N> to determine its resistance value, and including a second calibration resistor 327 connected to the second calibration node A. It is composed.

Although the code generation unit 320 includes two calibration codes PCODE <0: N> and NCODE <0: N> including two comparators 321 and 325, counters 322 and 326, and the like. Although shown to generate a, as described in the prior art, the code generation unit 320 may generate only one calibration code (PCODE <0: N> or NCODE <0: N>). In this case, the code generator 320 includes only the comparator 321, the counter 322, and the calibration resistor 323 to generate one calibration code. (In this case, the comparator counter calibration resistor. Since only one part needs to be provided, expressions such as first and second are omitted from the name.)

Further, although the first calibration code is illustrated as a pull-up calibration code (PCODE <0: N>) and the second calibration code as a pull-down calibration code (NCODE <0: N>) in the drawing, This may change with each other. The first calibration code generated while directly calibrating the external resistor 301 is a pull-down calibration code (NCODE <0: N>), and is calibrated with the dummy calibration resistor 324. When the generated second calibration code is a pull-up calibration code (PCODE <0: N>), unlike the drawing, the external resistor 301 should be connected to the ZQ node in the form of a pull-up resistor. The calibration resistor 323 is in the form of a pull-down resistor, the dummy calibration resistor 324 is also in the form of a pull-down resistor, the second calibration resistor 327 should be configured in the form of a pull-up resistor. . Such modifications are obvious to those skilled in the art, and thus detailed descriptions thereof will be omitted.

Now look at the operation of the present invention. When the reference voltage is 1 / 2VDDQ, the first calibration code PCODE <0: N> is generated such that the resistance ratio of the external resistor 301: the first calibration resistor 323 is 1: 1. . In addition, a second calibration code NCODE <0: N> is generated such that the resistance ratio of the dummy calibration resistor 324 to the second calibration resistor 327 is 1: 1. However, if the reference voltage VREF is changed by the control signals TM1, 2, 3, and 4, this ratio is not maintained. That is, when the reference voltage VREF is changed using the control signals TM1, 2, 3, and 4, the change is applied to the calibration codes PCODE <0: N> and NCODE <0: N>. For example, when the reference voltage VREF is 55/100 VDDQ, the first calibration code PCODE <0: may be such that the resistance ratio of the external resistor 301: the first calibration resistor 323 is 55:45. N>) is generated. Therefore, the calibration codes PCODE <0: N> and NCODE <0: N> at this time are generated differently than when the reference voltage is 1 / 2VDDQ.

When the level of the reference voltage VREF is changed by the application of the control signals TM1, 2, 3, and 4, the change is also made to the calibration codes PCODE <0: N> and NCODE <0: N>. . Since the resistance value of the termination resistor (see Fig. 2) is determined by applying the calibration codes (PCODE <0: N>, NCODE <0: N>), there is an error between the actual termination resistance value and the target resistance value. The error can be corrected by changing the calibration codes PCODE <0: N> and NCODE <0: N> using the control signals TM1, 2, 3, and 4. That is, the present invention makes it possible to correct the error of the on die termination device by simply adjusting the control signals TM1, 2, 3, 4. In addition, when the level of the reference voltage VREF is changed due to various factors, the level of the reference voltage VREF may be corrected through the control signals TM1, 2, 3, and 4.

4 is a configuration diagram of a calibration circuit of an on die termination device according to another embodiment of the present invention.

The calibration circuit of the on-die termination device according to another embodiment of the present invention outputs a first reference voltage VREF_A whose level is adjusted in response to one or more first control signals TM_A1, 2, 3, and 4. A first reference voltage generator 411; A second reference voltage generator 412 outputting a second reference voltage VREF_B whose level is adjusted in response to one or more second control signals TM_B1, 2, 3, and 4; And a first calibration code PCODE <0: N> in response to the voltages of the first reference voltage VREF_A and the first calibration node ZQ, and generate the second reference voltage VREF_B and the second reference voltage VREF_B. And a code generator 420 for generating a second calibration code NCODE <0: N> in response to the voltage of the second calibration node A. FIG.

Unlike the embodiment of FIG. 3, the embodiment of FIG. 4 includes two reference voltage generators 411 and 412. Therefore, the first reference voltage VREF_A and the second reference voltage VREF_B are separately changed using the first control signal TM_A1, 2, 3, and 4 and the second control signal TM_B1, 2, 3, and 4. . Therefore, the first calibration code and the second calibration code, that is, the pull-up calibration code (PCODE <0: N>) and the pull-down calibration code (NCODE <0: N>) can be changed separately. . Therefore, the embodiment of FIG. 4 can more accurately correct the error than the embodiment of FIG. 3.

The first reference voltage generator 411 and the second reference voltage generator 412 respectively control the first control signals TM_A1, 2, 3, and 4 and the second control signals TM_B1, 2, 3, and 4. In response, the first reference voltage VREF_A and the second reference voltage VREF_B are changed. Only the input control signals TM_A1, 2, 3, 4, TM_B1, 2, 3, and 4 and the output reference voltages VREF_A and VREF_B are different from each other, but may be designed to be identical to each other.

The code generator 420 may include a first comparator 421 for comparing the first calibration node ZQ and the first reference voltage VREF_A; A first counter 422 counting a first calibration code PCODE <0: N> according to a comparison result of the first comparator 421; A first calibration resistor unit 423 connected to the first calibration node ZQ to determine its resistance by receiving the first calibration code PCODE <0: N>; A dummy calibration resistor unit 424 connected to the second calibration node A to receive a first calibration code PCODE <0: N> and determine a resistance thereof; A second comparator 425 for comparing the second calibration node A with the second reference voltage VREF_B; A second counter 426 counting a second calibration code NCODE <0: N> according to the comparison result of the second comparator 425; And receiving a second calibration code NCODE <0: N> to determine its resistance value, and including a second calibration resistor 427 connected to the second calibration node A. It is composed. That is, compared to the code generator of FIG. 3, the input voltages are changed to two VREF_A and VREF_B, and the first calibration codes PCODE <0: N> and the second corrected errors are made through the two reference voltages. It generates a calibration code (NCODE <0: N>).

5 is a configuration diagram of an embodiment of the reference voltage generators 310, 411, and 412.

As shown in the figure, the reference voltage generating unit must be in series between the high voltage VDDQ and the low voltage VSSQ to output the reference voltages (VREF_A, VREF_B for VREF, 411, 412, but typically VREF) by voltage division. And a plurality of resistors (501, 502, 503, 504) of the plurality of resistors are control signals (TM1, 2, 3, 4) (TM_A1, 2, 3, 4 TM_B1, 2, 3, 4 may be input, but only a TM is representatively shown). In detail, transistors 505, 506, 507, and 508 are connected in parallel to the resistors 501, 502, 503, and 504 turned on / off by the control signals TM1, 2, 3, and 4, respectively. 507 and 508 are turned on / off by the control signals TM1, 2, 3 and 4. Accordingly, the resistors 501, 502, 503, 504 may be turned on / off by the control signals TM1, 2, 3, and 4, and thus the level of the reference voltage VREF is changed and output.

The number of control signals TM1, 2, 3, and 4 and the number of resistors 501, 502, 503, 504 controlled by the control signals TM1, 2, 3, and 4 may be arbitrarily determined. When the reference voltage VREF is to be roughly changed, only one control signal TM1, 2, 3, 4 and one resistor 501, 502, 503, 504 controlled by the control signal may be provided. In order to finely change VREF, the number of control signals TM1, 2, 3, and 4 and the resistances 501, 502, 503, 504 turned on / off by the control signal may be increased.

Control signals TM1, 2, 3, and 4 for changing the level of the reference voltage VREF may be generated in various ways. The signal may be a test mode signal determined by an MRS setting or the like, or may be a signal output from a fuse circuit whose logic varies depending on whether a fuse is cut. Alternatively, when the level of the reference voltage VREF is changed as the test mode signal and all errors of the on-die termination device are corrected, the logic value of the control signal may be set to be fixed using the fuse circuit. The generation or setting of the control signals TM1, 2, 3, and 4 may be easily performed by those skilled in the art, and thus detailed description thereof will be omitted.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a configuration diagram of a calibration circuit for performing a ZQ calibration operation in a conventional on-die termination device.

2 illustrates an example in which an on die termination device is applied to a semiconductor memory device.

3 is a block diagram of a calibration circuit of an on die termination device according to an embodiment of the present invention.

4 is a configuration diagram of a calibration circuit of an on die termination device according to another embodiment of the present invention.

5 is a configuration diagram of one embodiment of the reference voltage generators 310, 411, and 412.

* Explanation of symbols for the main parts of the drawings

310: reference voltage generator 320: code generator

411: first reference voltage generator 412: second reference voltage generator

420: code generator

Claims (13)

A reference voltage generator for outputting a reference voltage whose level is adjusted in response to one or more control signals; And Code generation unit for generating one or more calibration codes in response to the reference voltage and the voltage of one or more calibration nodes. Calibration circuit of the on-die termination device comprising a. The method of claim 1, The reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage to output the reference voltage by voltage division, At least one of the resistors is turned on / off in response to the at least one control signal. The method of claim 1, The reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage for outputting the reference voltage by voltage division; And One or more transistors connected in parallel to one or more of the resistors, respectively, for receiving the one or more control signals to their gates; The calibration circuit of the on-die termination apparatus comprising a. The method of claim 1, The code generation unit, A comparator for comparing the calibration node with the reference voltage; A counter for counting the calibration code according to a comparison result of the comparator; And Calibration resistance unit connected to the calibration node, the resistance value is determined by receiving the calibration code is received The calibration circuit of the on-die termination apparatus comprising a. The method of claim 4, wherein The calibration node, The calibration circuit of the on-die termination device, characterized in that the ZQ node connected to the external resistor for calibration. The method of claim 1, The code generation unit, A first comparator for comparing a first calibration node with the reference voltage; A first counter counting a first calibration code according to a comparison result of the first comparator; A first calibration resistor unit configured to receive the first calibration code and determine a resistance thereof, and to connect the first calibration node to the first calibration node; A dummy calibration resistor configured to receive the first calibration code and determine a resistance thereof, and to be connected to a second calibration node; A second comparator comparing the second calibration node with the reference voltage; A second counter counting a second calibration code according to a comparison result of the second comparator; And A second calibration resistor connected to the second calibration node, having its resistance determined by receiving the second calibration code; The calibration circuit of the on-die termination apparatus comprising a. A first reference voltage generator configured to output a first reference voltage whose level is adjusted in response to one or more first control signals; A second reference voltage generator configured to output a second reference voltage whose level is adjusted in response to at least one second control signal; And Generate a first calibration code in response to the first reference voltage and the voltage of the first calibration node, and generate a second calibration code in response to the voltage of the second reference voltage and the second calibration node. Code generator to generate Calibration circuit of the on-die termination device comprising a. The method of claim 7, wherein The first reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage to output the first reference voltage by voltage division, At least one of the resistors is turned on / off in response to the at least one first control signal. The method of claim 7, wherein The second reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage to output the second reference voltage by voltage division, At least one of the resistors is turned on / off in response to the at least one second control signal. The method of claim 7, wherein The first reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage for outputting the first reference voltage by voltage division; And One or more transistors connected in parallel to one or more of the resistors, respectively, and receiving the one or more first control signals to their gates. The calibration circuit of the on-die termination apparatus comprising a. The method of claim 7, wherein The second reference voltage generator, A plurality of resistors connected in series between a high voltage and a low voltage for outputting the second reference voltage by voltage division; And One or more transistors connected in parallel to one or more of the resistors, respectively, to receive the one or more second control signals to respective gates thereof. The calibration circuit of the on-die termination apparatus comprising a. The method according to any one of claims 7 to 11, The first calibration node, The calibration circuit of the on-die termination device, characterized in that the ZQ node connected to the external resistor for calibration. The method of claim 7, wherein The code generation unit, A first comparator comparing the first calibration node with the first reference voltage; A first counter counting the first calibration code according to a comparison result of the first comparator; A first calibration resistor unit configured to receive the first calibration code and determine a resistance thereof, and to connect the first calibration node to the first calibration node; A dummy calibration resistor unit configured to receive the first calibration code and determine a resistance thereof, and to be connected to the second calibration node; A second comparator comparing the second calibration node with the second reference voltage; A second counter counting the second calibration code according to a comparison result of the second comparator; And A second calibration resistor connected to the second calibration node, having its resistance determined by receiving the second calibration code; The calibration circuit of the on-die termination apparatus comprising a.
KR1020070087069A 2007-08-29 2007-08-29 Calibration circuit for on die termination device KR20090022043A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020070087069A KR20090022043A (en) 2007-08-29 2007-08-29 Calibration circuit for on die termination device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070087069A KR20090022043A (en) 2007-08-29 2007-08-29 Calibration circuit for on die termination device

Publications (1)

Publication Number Publication Date
KR20090022043A true KR20090022043A (en) 2009-03-04

Family

ID=40691992

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020070087069A KR20090022043A (en) 2007-08-29 2007-08-29 Calibration circuit for on die termination device

Country Status (1)

Country Link
KR (1) KR20090022043A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024244B1 (en) * 2009-11-30 2011-03-29 주식회사 하이닉스반도체 Impedance adjusting device
KR101110795B1 (en) * 2010-10-15 2012-02-27 주식회사 하이닉스반도체 Inpedance code generation circuit and semiconductor device including the same
US8476923B2 (en) 2011-02-28 2013-07-02 Hynix Semiconductor Inc. Impedance control circuit and integrated circuit chip including the same
US9196325B2 (en) 2013-07-19 2015-11-24 Samsung Electronics Co., Ltd. Integrated circuit with on die termination and reference voltage generation and methods of using the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101024244B1 (en) * 2009-11-30 2011-03-29 주식회사 하이닉스반도체 Impedance adjusting device
US7961001B1 (en) 2009-11-30 2011-06-14 Hynix Semiconductor Inc. Impedance adjusting device
KR101110795B1 (en) * 2010-10-15 2012-02-27 주식회사 하이닉스반도체 Inpedance code generation circuit and semiconductor device including the same
US8319519B2 (en) 2010-10-15 2012-11-27 Hynix Semiconductor Inc. Impedance code generation circuit and integrated circuit including the same
US8476923B2 (en) 2011-02-28 2013-07-02 Hynix Semiconductor Inc. Impedance control circuit and integrated circuit chip including the same
US9196325B2 (en) 2013-07-19 2015-11-24 Samsung Electronics Co., Ltd. Integrated circuit with on die termination and reference voltage generation and methods of using the same

Similar Documents

Publication Publication Date Title
KR100879783B1 (en) On Die Termination Device and Semiconcuctor Memory Device including thereof
KR100886644B1 (en) Calibration circuit for on die termination device
KR100879782B1 (en) On Die Termination Divice and Semiconductor Memory Device including the same
KR100904482B1 (en) Calibration circuit of On Die Termonation device
KR100853466B1 (en) On die termination device and method for accelerating calibration operation of the on die termination device
KR100780646B1 (en) On die termination device and semiconductor device which the on die termination device
KR100875673B1 (en) On-die termination device and its calibration method
US8120381B2 (en) Impedance adjusting device
US20110109344A1 (en) Semiconductor devices having on-die termination structures for reducing current consumption and termination methods performed in the semiconductor devices
KR100820783B1 (en) On die termination device with reduced mismatch
US20100007375A1 (en) Termination resistance circuit
KR100870427B1 (en) On Die Termination Device
KR100907929B1 (en) BUUB test apparatus and test method for semiconductor chip
KR20130072056A (en) Impedance code generating circuit and semiconductor device including the same
KR20090022043A (en) Calibration circuit for on die termination device
KR101175245B1 (en) Circuit for impedance adjusting and integrarted circuit chip including the same
KR100968419B1 (en) Parallel Resistor Circuit and On Die Termination Device, On Die Termination Comprising The Same
KR100838366B1 (en) Calibration circuit of on die termination device that can compensate offset
KR100976414B1 (en) Calibration circuit, on die termination device, and semiconductor memory device
KR100904466B1 (en) Termination circuit of On Die Termination Device
KR20090023833A (en) On die termination device
KR20120004145A (en) Impedance mismatching circuit to reduce impedance mismatch
KR20100109143A (en) Calibration circuit having fast speed

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E902 Notification of reason for refusal
E601 Decision to refuse application
J201 Request for trial against refusal decision
J301 Trial decision

Free format text: TRIAL DECISION FOR APPEAL AGAINST DECISION TO DECLINE REFUSAL REQUESTED 20090914

Effective date: 20100929