JP2007081923A - Differential output circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a differential output circuit capable of decreasing variations in a cross point caused when dispersion exists in speeds of signal transmission by transistors configuring the circuit or a power supply voltage received by the circuit is subject to change or like state by using a small number of components. <P>SOLUTION: The differential output circuit 1 is characterized in that each of a positive signal output circuit 3 and a negative signal output circuit 5 is provided with a delay circuit 19 comprising N type transistors and for forming a delay applied to a signal fed to a P type transistor 23 and a delay circuit 21 comprising P type transistors and for forming a delay applied to a signal fed to an N type transistor 27, the delay circuit 19 delays a received signal 37 in response to a speed of transmitting the signal to the P type transistor, and the delay circuit 21 delays a received signal 39 in response to a speed of transmitting the signal to the N type transistor. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a differential output circuit, for example, a technique effective for a semiconductor integrated circuit equipped with a USB (Universal Serial Bus) interface, for example.

  For example, there are input / output interfaces using differential signals such as a USB interface and an LVDS (Low Voltage Differential Signaling) interface. In this differential signal input / output interface, the differential input circuit is operated by the potential at the point where the pair of complementary signals cross each other, that is, the cross point. It is comprised so that the signal of this may be output. More specifically, in a differential output circuit, a positive or negative signal is input, and one circuit that outputs a positive or negative signal is complementary to a signal input to the one circuit. A signal is input, and the other circuit that outputs a signal complementary to the signal output from one circuit is included. By inputting a signal that is complementary to each circuit, each circuit is input. To output a complementary signal.

  Here, the complementary relationship indicates, for example, a relationship between logic levels of 0 and 1, and when one circuit outputs a logic level 1, that is, a positive signal, the other circuit has a logic level 0, that is, It means that there is an opposite relationship such as outputting a negative signal.

  However, such a differential output circuit has a problem that the cross point shifts from the reference potential. More specifically, the differential output circuit is designed so that the cross point becomes a reference potential, that is, a reference value. The reference value is a potential that is determined when designing the differential output circuit, and varies depending on the purpose of use of the differential output circuit, but is, for example, a potential that is half the maximum output voltage or power supply voltage. . However, in practice, for example, due to variations in the manufacture of semiconductor elements, semiconductor elements, i.e., transistors, having variations in signal transmission speed are manufactured. As a result, for example, one circuit rises, i.e., logic level 1 is fast. As a result of the output of the signal, the other circuit falls, that is, it outputs a slow signal of logic level 0, the cross point deviates from the reference value, or the input power supply voltage changes. For example, one circuit outputs a signal having a higher voltage than the other circuit, and the cross point is deviated from the reference value. If the cross point deviates from the reference value in this manner, the subsequent differential input circuit is affected by malfunction or the like.

  In order to reduce EMI (Electro-Magnetic Interference) noise, the pair of signals output by the differential output circuit must be kept symmetric, and the cross point is the logic level 1, that is, the potential of the power supply voltage. It was necessary to be located at the center point of the logic level 0, that is, the ground potential. Therefore, even if there are variations in the speed at which the signals of the transistors that make up the differential output circuit are transmitted, or even when there is a change in the power supply voltage input to the differential output circuit, the deviation from the reference value of the crosspoint That is, there has been a demand for a technique capable of reducing the fluctuation of the cross point.

  Here, Patent Document 1 discloses a technique for controlling cross-point variation using an external reference voltage. More specifically, the technique disclosed in Patent Document 1 is based on a crosspoint between a signal output from one circuit and a signal output from the other circuit, a signal output from one circuit, and an external reference. The cross point is compared with the voltage, and if there is a deviation between the two, the resistance of the differential output circuit is controlled to correct the deviation.

However, the technique disclosed in Japanese Patent Laid-Open No. 2001-177391 has a problem that the number of elements increases because it is necessary to form a cross point with an external reference voltage. Semiconductor integrated circuits equipped with USB interfaces, LVDS interfaces, etc. are mainly used in markets with intense price competition, such as digital home appliances, so it is essential to reduce the price of semiconductor integrated circuits. Therefore, it is necessary to make each circuit constituting the semiconductor integrated circuit fewer elements.

  The present invention eliminates such drawbacks of the prior art, such as when there is a variation in the speed of transmitting the signals of the transistors constituting the differential output circuit, or when the power supply voltage input to the differential output circuit changes. An object of the present invention is to provide a differential output circuit capable of reducing the fluctuation of the cross point generated in the above with fewer elements.

  In order to solve the above-described problem, in the present invention, a positive or negative signal is input, and a circuit that outputs a positive or negative signal and a signal that is input to the one circuit are in a complementary relationship. In the differential output circuit including the other circuit that outputs a signal that is complementary to the signal output from one circuit, one circuit converts the signal input to this circuit to the other circuit. The output of the signal is delayed according to the characteristics of the signal output, that is, the signal speed, the signal voltage, etc., and the other circuit outputs the signal input to this circuit to the signal output by one circuit. This is a differential output circuit that outputs the signal with a delay in accordance with the characteristics. As described above, since one circuit and the other circuit delay the signals output by themselves according to the characteristics of the signals output by the other party, it is possible to reduce the variation of the cross point.

  For example, when one circuit rises, that is, outputs a fast signal of logic level 1, the other circuit falls, that is, when to output a logic level 0 signal, and when one circuit outputs a signal Therefore, it is possible to bring the cross point close to the reference potential. Also, for example, when one circuit outputs a rising signal with a high voltage, the other circuit makes the timing for outputting the falling signal faster than the timing for one circuit to output the signal. It becomes possible to bring the cross point close to the potential. Such signal delay is performed by delay circuits included in one circuit and the other circuit.

  According to the present invention, even when there is a variation in the transmission speed of the transistors constituting the differential output circuit, or when the power supply voltage input to the differential output circuit changes, the delay circuit By forming the delay, it is possible to reduce the variation of the cross point. Therefore, it is possible to reduce the variation of the cross point with a simple circuit configuration and a small number of elements, and as a result, it is possible to reduce the price of the reaction body integrated circuit.

  Next, embodiments of the differential output circuit of the present invention will be described in detail with reference to the accompanying drawings. In the following description, reference numerals of signals are represented by connecting line reference numerals that appear. FIG. 1 is a circuit diagram showing a configuration of an embodiment of a differential output circuit 1 of the present invention. In FIG. 1, a differential output circuit 1 receives a positive or negative signal and outputs a positive or negative signal, that is, a positive signal output circuit 3 and a positive signal output circuit 3. A signal that is complementary to the signal is input, and the other circuit that outputs a signal that is complementary to the signal output from the positive signal output circuit 3, that is, the negative signal output circuit 5 is included. The positive signal output circuit 3 and the negative signal output circuit 5 are each input with complementary signals. When the complementary signals are input in this way, the positive signal output circuit 3 and the negative signal output circuit 5 Outputs a pair of signals in a complementary relationship as shown in FIGS. 5 and 8, for example. The output pair of signals is transmitted to a differential input circuit (not shown), and a cross point of the pair of signals becomes an input signal of the differential input circuit.

  In the present embodiment, a pair of complementary signals input to the operation output circuit 1 are an AP signal 7 and an AM signal 9 as shown in FIG. The AM signal 9 can be obtained by inverting the AP signal 7 by an inverter (not shown). In FIG. 2, the solid line is the AP signal 7 and the dotted line is the AM signal 9. In the present embodiment, not only the AP signal 7 and the AM signal 9 but also the EB signal 11 as an output enable signal is input to the differential output circuit 1. The EB signal 11 is a signal having a function of electrically connecting or disconnecting the signal output from the differential output circuit 1, and in this embodiment, the differential output is performed when the EB signal 11 is at the logic level 1. When the output of the circuit 1 is electrically connected and the EB signal 11 is at logic level 0, the output of the differential output circuit 1 is not electrically connected, that is, high impedance. In the present embodiment, the EB signal 11 is also input to the differential output circuit 1, but the present invention is not limited to this, and for example, the EB signal 11 may not be provided.

  In the present embodiment, the pair of complementary signals output from the differential output circuit 1 are the DP signal 13 and the DM signal 15. DP signal 13 is output when AP signal 7 and EB signal 11 are input to positive signal output circuit 3, and DM signal 15 is input to AM signal 9 and EB signal 11 at negative signal output circuit 5. It is a signal that is output when The DP signal 13 and the DM signal 15 are in a complementary relationship. For example, when the DP signal 13 is at the logic level 1, when the DP signal 13 is at the logic level 1, the DM signal 15 is at the logic level 0. When signal 13 is at logic level 0, DM signal 15 is at logic level 15. The DP signal 13 is at logic level 1 when the input AP signal 7 is at logic level 1, and the DP signal 13 is at logic level 0 when the AP signal 7 is at logic level 0. is there. The same applies to the relationship between the DM signal 15 and the AM signal 7.

  Returning to FIG. 1, the positive signal output circuit 3 and the negative signal output circuit 5 are both input terminals 7, 9, 11, a tristate control circuit 17, a delay circuit 19 as a first delay circuit, and a second delay. The circuit includes a delay circuit 21, a pre-driver 25 for a P-channel transistor 23, a P-channel transistor 23, a pre-driver 29 for an N-channel transistor 27, an N-channel transistor 27, and output terminals 13 and 15. Connected as in 1. The positive signal output circuit 3 and the negative signal output circuit 5 have the same signal slew rate. Hereinafter, since the positive signal output circuit 3 and the negative signal output circuit 5 have the same configuration, only the positive signal output circuit 3 will be described.

  The input terminal of the positive signal output circuit 3 includes an input terminal 7 to which the AP signal 7 is input and an input terminal 11 to which the EB signal 11 is input. The two input terminals 7 and 11 are respectively connected to the tristate control circuit 17, and the AP signal 7 and the EB signal 11 are sent to the tristate control circuit 17.

  The tri-state control circuit 17 is a circuit having a function of assigning one of three states of logic level 0, logic level 1, or high impedance to the signals input from the input terminals 7 and 11, The signals 37 and 39 to which one of the three states is assigned are transferred to the delay circuit 19 that is the first delay circuit and the delay circuit 21 that is the second delay circuit, respectively. The signals 37 and 39 are signals of the same logic level except when they are high impedance, that is, when the EB signal 11 is at logic level 0. For example, if signal 37 is at logic level 0, signal 39 is also at logic level 0. In the case of high impedance, the signal 37 and the signal 39 are different. Specifically, the signal 37 has a logic level 0 and the signal 39 has a logic level 1. Since the AP signal 7 input to the positive signal output circuit 3 and the AM signal 9 input to the negative signal output circuit 5 are in a complementary relationship, the positive signal output circuit 3 is The signals 37 and 39 from the tristate control circuit 17 and the signals 37 and 39 from the tristate control circuit 17 in the negative signal output circuit 5 are also in a complementary relationship, for example, the tristate in the positive signal output circuit 3 When the signals 37 and 39 from the control circuit 17 are at logic level 1, the signals 37 and 39 from the tristate control circuit 17 included in the negative signal output circuit 5 are at logic level 0, and conversely, the positive signal output circuit 3 When the signals 37 and 39 from the tristate control circuit 17 are at logic level 0, the signals 37 and 39 from the tristate control circuit 17 in the negative signal output circuit 5 are at logic level 1. In the present embodiment, the tristate control circuit 17 is provided, but the present invention is not limited to this, and the tristate control circuit 17 is not provided, and the AP signal 7 and the EB signal 11 from the input terminal are provided. The signal may be directly input to the delay circuits 19 and 21.

  The signal 37 whose state is determined by the tristate control circuit 17 is input to the delay circuit 19. The delay circuit 19 has a function of delaying the input signal 37 and outputs a signal 41 obtained by delaying the signal 37. The signal 41 is input to the pre-driver 25 of the P-channel transistor 23. In this embodiment, the pre-driver 25 of the P-channel transistor 23 is an OR circuit, inverts the logic level of the input signal 41 and outputs a signal 43, and the output signal 43 is output from the P-channel transistor 23. Input to gate 45. In the P-channel transistor 23, the source 47 is connected to the output terminal 13, the drain 49 is connected to the power source, and when a logic level 0 signal is input to the gate 45, a logic level 1 signal, that is, an operation that rises Conducts the current that forms the waveform.

  The signal 39 whose state is determined by the tri-state control circuit 17 is input to the delay circuit 21. The delay circuit 21 has a function of delaying the input signal 39, and outputs a signal 51 obtained by delaying the signal 39. The signal 51 is input to the pre-driver 29 of the N-channel transistor 27. In the present embodiment, the pre-driver 29 of the N-channel transistor 27 is an OR circuit, and the signal 53 is output by inverting the logic level of the input signal 51. Input to gate 55. The N-channel transistor 27 has a drain 57 connected to the output terminal 13, a source 59 grounded, and a logic level 0 signal, that is, an operation waveform that falls when a logic level 1 signal is input to the gate 55. Conducting current to form.

  The output terminal 13 is connected to both the P channel transistor 23 and the N channel transistor 27, and outputs a logic level 1 signal conducted by the P channel transistor 23 or a logic level 0 signal conducted by the N channel transistor 27. . This output signal is the DP signal 13. More specifically, the output terminal 13 is connected to the source 47 of the P-channel transistor 23. When a logic level 0 signal is input to the gate 45 of the P-channel transistor 23, the output terminal 13 is connected between the source 47 and the drain 49. 1 is output, that is, a DP signal 13 that forms a rising operation waveform. The output terminal 13 is connected to the drain 57 of the N-channel transistor 27. When a logic level 1 signal is input to the gate 55 of the N-channel transistor, the output terminal 13 has a logic level 0 flowing between the source 59 and the drain 57. The DP signal 13, that is, the DP signal 13 that forms the falling operation waveform is output.

  When a logic level 1 signal is input to the gate of the P-channel transistor 23, no signal flows between the source 47 and the drain 49, and when a logic level 0 signal is input to the N-channel transistor 27, Since no signal flows between source 59 and drain 57, DP signal 13 is either a logic level 1 signal or a logic level 0 signal, and a logic level 1 signal and a logic level 0 signal Both of them do not become DP signal 13. In the present embodiment, the number of output terminals provided in the positive signal output circuit 3 is one, but the present invention is not limited to this. For example, an output terminal from which a signal of logic level 1 by the P-channel transistor 23 is output. And two output terminals for the output of the logic level 0 signal from the N-channel transistor 27, respectively, so that the logic level 1 signal and the logic level 0 signal can be output at separate output terminals. Is possible. In the negative signal output circuit 5, only the input terminal 7 is changed to the input terminal 9 and the output terminal 13 is changed to the output terminal 15, and the rest is the same as the positive signal output circuit 3.

  In the differential output circuit 1 having such a configuration, for example, when a logic level 1 is input to the AP signal 7, a logic level 0 is input to the AM signal 9, and a logic level 1 signal is input to the EB signal 11, a positive signal output In the circuit 3, signals 37 and 39 of the logic level 1 are output from the tristate control circuit 17, and the signal 43 transmitted to the P channel transistor 23 through the delay circuit 19 and the pre-driver 25 of the P channel transistor 23 is used as the P channel transistor. 23 transmits a logical level 1 signal, and a logical level 1 DP signal 13 is output from the output terminal 13. In the negative signal output circuit 5, the signals 37 and 39 of logic level 0 are output from the tristate control circuit 17, and the signal 53 transmitted to the N channel transistor 27 through the delay circuit 21 and the pre-driver 29 of the N channel transistor 27 is output. As a result, the N-channel transistor 27 transmits a signal of logic level 0, and the DM signal 15 of logic level 0 is output from the output terminal 15. Also, for example, when a logic level 0 signal is input to the AP signal 7, a logic level 1 signal is input to the AM signal 9, and a logic level 1 signal is input to the EB signal 11, the N-channel transistor 27 transmits the signal in the positive signal output circuit 3. Thus, the DP signal 13 at the logic level 0 is output from the output terminal 13, and the P-channel transistor 23 transmits the signal in the negative signal output circuit 5, so that the DM signal 15 at the logic level 1 is output from the output terminal 15. Is output.

  In this embodiment, a P-channel transistor 23, which is a field effect transistor having a MOS structure, is adopted as a P-type transistor, and similarly, a MOS-type N-channel transistor 27 is adopted as an N-type transistor. However, the present invention is not limited to this, and if it is possible to transmit a logic level 1 signal and a logic level 0 signal to the output terminals 13 and 15, depending on the purpose of the differential output circuit 1. Any type of transistor can be employed.

  FIG. 3 is a circuit diagram showing an example of the configuration of the delay circuit 19 of FIG. In this embodiment, the delay circuit 19 is a circuit that forms a delay by using a MOS-type ON resistance. A P-channel transistor 81 having a MOS-type structure is adopted as a P-type transistor, and a MOS is used as an N-type transistor. An N-channel transistor 83 having a type structure is employed. Note that the present invention is not limited to this embodiment, and any type of transistor can be employed depending on the purpose of the differential output circuit.

  In this embodiment, as shown in FIG. 3, three N-channel transistors 83 are employed, and these are connected in series in multiple stages to constitute an N-channel transistor stage 85 which is an N-type transistor stage. Further, a delay circuit 19 is configured by connecting one P-channel transistor 81 in parallel to the N-channel transistor stage 85. That is, the end point of the P-channel transistor 81 and the end point of the N-channel transistor stage 85 are connected to each other, and the connected one end point 87 is connected to the connection line 37 to which the signal 37 is input to the delay circuit 19 and connected. The other end point 89 is connected to a connection line 41 that transmits the signal 41 delayed by the delay circuit 19 to the pre-driver 25 of the P-channel transistor 23.

  The gate length of the individual N-channel transistors 83 constituting the N-channel transistor stage 85 is substantially the same as the minimum value of the process, and is 0.5 μm in this embodiment. Here, the substantially same gate length is preferably the same gate length as the minimum value, but the present invention is not limited to this, and the length is more than the minimum value of the process and about 20 times the minimum value. Any length can be adopted as long as it is as follows. Here, the minimum value of the process is a minimum value of the gate length that can be taken at the time of manufacturing the semiconductor device, and is a value that depends on the technology for manufacturing the semiconductor device, for example, 0.34 μm. Therefore, the gate length of the N-channel transistor 83 is preferably 0.2 μm or more and 6 μm or less, more preferably 0.3 μm or more and 5 μm or less. However, the present invention is not limited to this, and any value can be adopted. It is. Note that since the transistor forms a delay, it is preferable not to make it too long, but this is not restrictive. In this embodiment, the gate width of the N channel transistor 83 is 1 μm.

  In the present invention, the gate length of the P-channel transistor 81 needs to be longer than the gate length of the N-channel transistor 83 described above. In this embodiment, the gate length of the N-channel transistor 83 is four times or more. The length is 4.0 μm. The gate width of the P channel transistor 81 is 3 μm. In this embodiment, the gate length of the P-channel transistor 81 is 4.0 μm, but the present invention is not limited to this, and the gate length of one N-channel transistor 83 constituting the N-channel transistor stage 85 is not limited to this. Any value can be employed as long as it is 2 to 30 times, more preferably 4 to 20 times. However, if the length is too long, the area occupied by the circuit increases, which is not practical. Therefore, it is preferably about 1 μm or more and 10 μm or less, but is not limited thereto.

  By configuring the delay circuit 19 as described above, the delay circuit 19 is configured to have a delay according to the signal transmission speed of the N-channel transistor stage 85, that is, the N-channel transistor 83. For example, even when the signal transmission speed of the P-channel transistor 81 is increased, the delay circuit 19 forms a delay according to the signal transmission speed of the N-channel transistor 83, so the delay by the delay circuit 19 does not change. As a result, the timing at which the P-channel transistor 23 transmits the logic level 1 current to the output terminal 13 does not substantially change. Conversely, when the signal transmission speed of the N-channel transistor 83 is increased, the signal transmission speed of the N-channel transistor stage 85 of the delay circuit 19 is increased and the delay is reduced, and the signal is transmitted to the pre-driver 25 of the P-channel transistor 23. Speed up the transmission timing of 41. As a result, the timing at which the signal 43 is transmitted from the pre-driver 25 to the P-channel transistor 23 is accelerated, and the timing at which the P-channel transistor 23 transmits the logic level 1 current to the output terminal 13 can be accelerated. Therefore, by adopting a transistor having substantially the same signal transmission speed as the N channel transistor 83 that constitutes the N channel transistor 27 and the delay circuit 19, when the N channel transistor 27 outputs a fast signal, the delay circuit 19 Since the delay becomes small and the timing at which the P-channel transistor 23 outputs can be accelerated, it becomes possible to approach the potential with the cross point as a reference, and the fluctuation can be reduced. Similarly, when the signal transmission speed of the N-channel transistor 27 becomes slow, the delay of the delay circuit 19 becomes large and the timing at which the P-channel transistor 23 outputs can be accelerated, so that the cross-point fluctuation is reduced. Is possible to do.

  In this embodiment, three N-channel transistors are used in the N-channel transistor stage 85, but the present invention is not limited to this, and the number of N-channel transistors 83 may be larger than the number of P-channel transistors 81. What is necessary is just to have at least two. However, if the number of N-channel transistors 83 is too large, the area occupied by the circuit is increased by the N-channel transistor stage 85, and therefore preferably 2 or more and 7 or less, more preferably 3 or more and 5 or less. Good. The number of P-channel transistors 81 needs to be smaller than the number of N-channel transistors 83 constituting the N-channel transistor stage 85, and is preferably set to two or less.

  FIG. 4 is a circuit diagram showing an example of the configuration of the delay circuit 21 of FIG. In this embodiment, the delay circuit 21 is obtained by replacing the P-channel transistor 81 and the N-channel 83 of the delay circuit 19. More specifically, three P-channel transistors 91 are employed to form a P-channel transistor stage 93, and one N-channel transistor 95 is employed. The P-channel transistor stage 93 and the N-channel transistor 95 are connected in parallel with their end points connected to each other, and one end 97 of the connected end points is connected to a connection line 39 to which the signal 39 is input to the delay circuit 21, The other end point 99 connected is connected to a connection line 51 that transmits the signal 51 delayed by the delay circuit 21 to the pre-driver 29 of the N-channel transistor 27.

  The gate length of the individual P-channel transistors 91 constituting the P-channel transistor stage 93 is substantially the same as the minimum value of the process, and in this embodiment is 0.5 μm. Here, the substantially same gate length is preferably the same gate length as the minimum value, but the present invention is not limited to this, and the length is more than the minimum value of the process and about 20 times the minimum value. Any length can be adopted as long as it is as follows. Here, the minimum value of the process is the minimum value of the gate length that can be taken at the time of manufacturing the semiconductor device, and is a value that depends on the technology for manufacturing the semiconductor device, for example, 0.34 μm. Therefore, the gate length of the P-channel transistor 91 is preferably 0.2 μm or more and 6 μm or less, more preferably 0.3 μm or more and 5 μm or less, but the present invention is not limited to this, and any value can be adopted. Is possible. Note that since the transistor forms a delay, it is preferable not to make it too long, but this is not restrictive. In this embodiment, the gate width of one P-channel transistor 91 is 1 μm.

  The gate length of one N-channel transistor 95 must be longer than the gate length of the P-channel transistor 91 described above. In this embodiment, the gate length of the N-channel transistor 95 is at least four times the gate length of the P-channel transistor 91. The length is 4.0 μm. The gate width of the N channel transistor 95 is 3 μm. In this embodiment, the gate length of the N channel transistor 95 is 4.0 μm, but the present invention is not limited to this, and the gate length of one P channel transistor 91 constituting the P channel transistor stage 93 is not limited to this. Any value can be employed as long as it is 2 to 30 times, more preferably 4 to 20 times. However, if the length is too long, the area occupied by the circuit increases, which is not practical. Therefore, it is preferably about 1 μm or more and 10 μm or less, but is not limited thereto.

  By configuring the delay circuit 21 as described above, the delay circuit 21 is configured to have a delay according to the signal transmission speed of the P-channel transistor stage 93, that is, the P-channel transistor 91. For example, even when the signal transmission speed of the N-channel transistor 95 is fast, the delay circuit 21 forms a delay due to the signal transmission speed of the P-channel transistor 91, so the delay by the delay circuit 21 does not change, and as a result The timing at which the N-channel transistor 27 transmits a logic level 0 current to the output terminal 13 does not substantially change. Conversely, when the signal transmission speed of the P-channel transistor 91 is high, the signal transmission speed of the P-channel transistor stage 93 of the delay circuit 21 is increased and the delay is reduced, and the signal 51 is sent to the pre-driver 29 of the N-channel transistor 27. Make the transmission timing faster. As a result, the timing at which the signal 53 is transmitted to the N-channel transistor 27 is accelerated, the timing at which the N-channel transistor 27 transmits the logic level 0 current to the output terminal 13 can be accelerated, and the cross point is used as a reference. It becomes possible to approach the potential. Therefore, by adopting a transistor having substantially the same signal transmission speed as the P-channel transistor 91 that constitutes the P-channel transistor 23 and the delay circuit 21, when the P-channel transistor 23 outputs a fast signal, the delay circuit 21 Since the delay becomes smaller and the timing at which the N-channel transistor 27 outputs can be made faster, it becomes possible to approach the potential with the cross point as a reference, and the fluctuation can be reduced. Similarly, when the signal transmission speed of the P-channel transistor 23 becomes slow, the delay of the delay circuit 21 becomes large and the timing at which the N-channel transistor 27 outputs can be accelerated, so that the fluctuation of the cross point is reduced. Is possible to do.

  In this embodiment, three P-channel transistors 91 are used in the P-channel transistor stage 93, but the present invention is not limited to this, and the number of P-channel transistors 91 is larger than the number of N-channel transistors 93. It is sufficient that at least two P-channel transistors 91 are employed. However, if the number of P-channel transistors 91 is too large, the area occupied by the circuit is increased by the P-channel transistor stage 93, and therefore preferably 2 or more and 7 or less, more preferably 3 or more and 5 or less. Good. Further, the number of N-channel transistors 95 needs to be smaller than the number of P-channel transistors 91 constituting the P-channel transistor stage 93, and is preferably set to two or less.

  In this embodiment, the P-type transistor and the N-type transistor constituting the differential output circuit are made the same type, but the present invention is not limited to this, and any type of transistor can be adopted. It is. For example, the type of transistor employed for each delay circuit can be changed. In addition, it is better to adopt a transistor manufactured at substantially the same time as the P-type transistor constituting the P-type transistor stage and the P-type transistor to which the signal delayed by the first delay circuit is input. Since the speed is substantially the same, the delay can be automatically changed according to each transistor signal transmission speed, and the fluctuation of the cross point can be reduced. This is not a limitation. The same applies to N-type transistors.

  In addition, since all the P-type transistors and N-type transistors that make up the differential output circuit are made to be transistors manufactured at substantially the same time, the signal transmission speed is substantially the same. Even when the signal transmission speed of the P-type transistor and the signal transmission speed of the N-type transistor are opposite, such as the signal transmission speed of the transistor is high and the signal transmission speed of the N-type transistor is low, it is automatically Although it is preferable because the fluctuation of the cross point can be reduced, the present invention is not limited to this. Here, the transistors manufactured at substantially the same time are preferably transistors of the same lot or transistors manufactured at the same time, but the present invention is not limited to this, and the manufacturing conditions are substantially the same. As long as they are the same transistor or a transistor that has been manufactured soon.

  FIG. 5 is a conceptual diagram of operation waveforms of the DP signal 13 and the DM signal 15 when the signal transmission speed of the P-channel transistors 23, 81, 91 is slow in the differential output circuit 1 of FIG. In FIG. 5, an operation waveform 111 is an operation waveform of the DP signal 13 output from the positive signal output circuit 3 of FIG. The operation waveform 113 is an operation waveform of the DM signal 15 output from the negative signal output circuit 5 of FIG. The operation waveform 111 and the operation waveform 113 are reference waveforms, for example, waveforms when there is no variation in the signal transmission speed or a change in the power supply voltage. In this embodiment, the waveform when the power supply voltage is 3.3 V Is shown. The cross point 115 at the intersection of the operation waveform 111 and the operation waveform 113 is a cross point set at the time of design, that is, a reference potential. In the present embodiment, the cross point 115 is 1/3 of the power supply voltage 3.3V. The potential of 2 is 1.65V.

  Here, in the conventional differential output circuit, when the signal transmission speed of the P-channel transistor included in the positive signal output circuit and the negative signal output circuit becomes slow, the DM signal output from the negative signal output circuit is affected, and the operation waveform Changes to a gentle rising waveform, that is, an operation waveform 119 which is a waveform inclined in the direction of the horizontal axis 117. This is due to the fact that a signal of logic level 1 is transmitted to the output terminal by the P-channel transistor that has transmitted the signal slowly. In addition, in the conventional differential output circuit, when the signal transmission speed of the P-channel transistor in the positive signal output circuit and the negative signal output circuit is slow, the falling waveform of the DP signal output from the positive signal output circuit hardly changes. The operation waveform 111 remains unchanged. This is because the DP signal output from the positive signal output circuit of the conventional differential output circuit has a large dependence on the signal transmission speed of the N-channel transistor, and even if the P-channel transistor transmits the signal slowly, This is because the delay formed in the conventional positive signal output circuit does not change. Therefore, in the conventional differential output circuit, when the P-channel transistor transmits the signal slowly, the cross point 121 has an operation waveform 111 that does not change and an operation waveform 119 that is a waveform inclined in the direction of the horizontal axis 117. Therefore, it is located further below the reference cross point 115.

  On the other hand, in the differential output circuit 1 of the present embodiment, when the signal transmission speed of the P-channel transistors 23, 81, 91 is slowed, the DM signal 15 output from the negative signal output circuit 3 is affected, and the conventional differential The waveform is substantially the same as the DM signal output from the negative signal output circuit of the output circuit, that is, the operation waveform 119 having a gentler slope than the operation waveform 113. This is because the delay of the delay circuit 19 of the differential output circuit 1 depends on the signal transmission speed of the N-channel transistor 83, so that the delay does not change even if the signal transmission speed of the P-channel transistors 23, 81, 91 changes, The reason is that the DM signal 15 of the logic level 1 is transmitted to the output terminal by the P-channel transistor 23 which has transmitted the signal late.

Further, in the differential output circuit 1 of this embodiment, when the signal transmission speed of the P-channel transistors 23, 81, 91 is slow, the falling waveform of the DP signal 13 output from the positive signal output circuit 3 of the differential output circuit 1 the fall time change, i.e., the slope of the variation of the waveform is small, falling timing delay time t ₁ becomes slow, operating waveform 123 as the shape of the waveform is substantially the same, the fall timing The waveform is delayed by the delay time t ₁ from the timing when the operation waveform 111 falls. This is because the delay circuit 21 included in the positive signal output circuit 3 of the differential output circuit 1 of the present invention forms a delay depending on the signal transmission speed of the P-channel transistor 91. That is, since the signal transmission speed of the P-channel transistor 91 is slow, the delay increases, and the timing for transmitting the signal 51 to the pre-driver 29 of the N-channel transistor 27 is delayed. As a result, the timing at which the signal 53 is transmitted from the pre-driver 29 of the N-channel transistor 27 to the N-channel transistor 27 is also delayed, and the timing at which the N-channel transistor 27 starts to transmit a logic level 0 current to the output terminal 13 is It becomes possible to delay the delay time t ₁ further. Therefore, the cross point 125 can be positioned above the cross point 121 by the conventional differential output circuit, and can be brought closer to the reference cross point 115.

In this embodiment, the delay time t ₁ is about 0.02 ns, but the present invention is not limited to this, and can be arbitrarily changed according to the variation of the cross point. For example, in the case of the delay circuit 21, the delay time t1 can be changed by changing the number of P-channel transistors 91 constituting the P-channel transistor stage 93. If the number of P-channel transistors 91 is increased by _one , the delay time t1 Becomes larger and the delay time t ₁ becomes about 0.05 ns.

  As a result, in the differential output circuit 1 of the present embodiment, the width 127 of the cross point variation due to the variation in the signal transmission speed of the P-channel transistors 23, 81, 91 is changed to the width of the cross point variation in the conventional differential output circuit. It is possible to make it smaller than 129. In particular, it is possible to reduce the width of fluctuations in the cross point due to variations only by delaying the signal by the delay circuits 19 and 21, so that extra elements such as when comparing the power supply voltage and the cross point are used. There is no need to use it. Therefore, it is possible to obtain a circuit with a simple configuration and reduced cross-point fluctuation due to variations in signal transmission speed, and it is possible to prevent an increase in manufacturing cost.

Although not shown, when the signal transmission speed of the P-channel transistors 23, 81, 91 is increased, the width of the cross-point variation can be reduced. Specifically, since the P-channel transistor 23 of the negative signal output circuit allows a logic level 1 current to flow quickly, the slope of the operation waveform of the DM signal 15 becomes steep. On the other hand, since the signal transmission speed of the P-channel transistor 91 of the positive signal output circuit is increased, the delay of the delay circuit 21 is reduced, and the falling waveform of the DP signal 13 is a change in the falling time, that is, the slope of the waveform. Although the change is small, the fall timing is delayed by a delay time t ₁ than the fall timing of the operation waveform 111. Therefore, it is possible to approach the cross point 115 with the cross point at this time as a reference. 5 illustrates the operation waveforms of the DP signal 13 and the DM signal 15 when the AP signal is at logic level 0 and the AM signal is at logic level 1, the AP signal is at logic level 1 and the AM signal is at logic level 0. When the DP signal 13 and the DM signal 15 are interchanged, that is, the DP signal rises and the DM signal falls, and the others are the same.

  Although not shown, the cross point can be brought closer to the cross point 115 when the signal transmission speed of the N-channel transistors 27, 83, and 95 is increased or decreased. Specifically, when the signal transmission speed of the N-channel transistors 27, 83, and 95 is increased, the DP signal 13 has a waveform with a steep slope, but the DM signal 15 does not change its slope. Since the rising timing is a waveform that is faster, the cross point at this time can be made closer to the cross point 115. If the signal transmission speed of the N-channel transistors 27, 83, and 95 is slow, the DP signal 13 has a waveform with a gentle slope, but the DM signal 15 rises slowly without changing its slope. Therefore, the cross point at this time can be brought close to the cross point 115.

  Although not shown in the figure, in this embodiment, even if the signal transmission speeds of the P-channel transistors 23, 81, 91 and the N-channel transistors 27, 83, 95 are opposite, It can be made smaller. For example, when the signal transmission speed of the P-channel transistors 23, 81, 91 is increased, and conversely, when the signal transmission speed of the N-channel transistors 27, 83, 95 is decreased, the DM signal 15 rises slowly. A steep rising waveform. Further, the DP signal 13 has a gentle falling waveform with a fast falling timing. Therefore, it becomes possible to approach the potential with the cross point as a reference, and the width of fluctuation of the cross point can be reduced. In addition, when the signal transmission speed of the P-channel transistors 23, 81, 91 is slow, and conversely, when the signal transmission speed of the N-channel transistors 27, 83, 95 is fast, the DM signal 15 rises quickly. The DP signal 13 has a gentle slope rising waveform and a falling waveform with a steep slope with a slow fall timing, and approaches a potential based on the cross point.

  FIG. 6 is a circuit diagram showing the configuration of another embodiment of the differential output circuit of the present invention. In FIG. 6, the same reference numerals as those in FIG. In FIG. 6, the differential output circuit 151 includes a positive signal output circuit 153 and a negative signal output circuit 155, and signals having a complementary relationship are input to the positive signal output circuit 153 and the negative signal output circuit 155, respectively. The positive signal output circuit 153 and the negative signal output circuit 155 output a pair of signals in a complementary relationship. The output pair of signals is transmitted to a differential input circuit (not shown), and a cross point of the pair of signals becomes an input signal of the differential input circuit.

  Both the positive signal output circuit 153 and the negative signal output circuit 155 have two input terminals 7, 9, 11, a tristate control circuit 17, a delay circuit 157 that is a first delay circuit, and a delay that is a second delay circuit. A circuit 159, a pre-driver 25 for the P-channel transistor 23, a P-channel transistor 23 that is a P-type transistor, a pre-driver 29 for an N-channel transistor 27, an N-channel transistor 27 that is an N-type transistor, and the output terminals 13 and 15, respectively They are connected as shown. The positive signal output circuit 153 and the negative signal output circuit 155 have the same signal slew rate. Hereinafter, since the positive signal output circuit 153 and the negative signal output circuit 155 have the same configuration, only the positive signal output circuit 153 will be described.

  The signal 37 whose state is determined by the tristate control circuit 17 is input to the delay circuit 157. The delay circuit 157 has a function of delaying the signal 37, and outputs a signal 161 obtained by delaying the signal 37. The signal 161 is input to the pre-driver 25 of the P-channel transistor 23. In this embodiment, the delay circuit 157 is a circuit that delays a signal generally used in a differential output circuit conventionally, and is a transistor in which one P-channel transistor 163 and one N-channel transistor 165 are stacked vertically. This is a circuit in which two vertical product stages 167 are connected. Here, “vertical stacking” refers to a connection form in which the source / drain path of one transistor is continuously connected to the power supply / ground of another transistor. In this embodiment, the delay circuit 157 is configured as described above. However, the present invention is not limited to this, and any circuit can be used as the delay circuit 157 as long as it is a circuit that delays a commonly used signal. Is possible.

  The signal 39 whose state is determined by the tristate control circuit 17 is input to the delay circuit 159. The delay circuit 159 has a function of delaying the signal 39, and outputs a signal 169 obtained by delaying the signal 39. The signal 169 is input to the pre-driver 29 of the N-channel transistor 27. Here, when the power supply voltage is changed, the delay circuit 159 forms a delay larger or smaller than the delay formed by the delay circuit 157, and determines the timing of the signal 169 transmitted to the pre-driver 29 of the N-channel transistor 27. The delay circuit 157 is slower or faster than the timing of the signal 161 transmitted to the pre-driver 25 of the P-channel transistor 23, and the timing at which the N-channel transistor 27 starts to flow a logic level 0 current to the output terminal 13, P It is later or faster than the timing at which 23 starts to flow a logic level 1 current than the channel transistor.

  FIG. 7 is a circuit diagram showing an example of the configuration of the delay circuit 159 of FIG. In FIG. 7, the delay circuit 159 includes an inverter delay circuit 171 and a bias circuit 173. The inverter delay circuit 171 exists in the delay circuit 159, and is a transistor vertical product in which P-channel transistors 175 and 177 that are P-type transistors and N-channel transistors 179 and 181 that are N-type transistors are connected in cascade. Two stages 183 and 185 are provided. Since the transistor vertical product stages 183 and 185 have the same configuration, only the transistor vertical product stage 183 will be described in detail. An N-channel transistor 181 is vertically stacked on the N-channel transistor 179, and further P Channel transistors 175 are stacked vertically, and further P-channel transistors 177 are stacked vertically. The N-channel transistor 179 is connected to the source of the N-channel transistor 181 whose source is grounded and whose drain is vertically stacked. The P-channel transistor 177 has a drain connected to the power source and a source connected to the drain of the P-channel transistor 175 that is stacked vertically. The N-channel transistor 181 has a drain connected to the source of the P-channel transistor 175. Furthermore, the N-channel transistors 179 and 181 and the P-channel transistors 175 and 177 are connected to each other on the gate side.

  Of the two transistor vertical product stages 183 and 185, the transistor vertical product stage 183 is located on the tristate control circuit 17 side in the delay circuit 159, and the transistor vertical product stage 185 is connected to the N in the delay circuit 159. It is located on the pre-driver 29 side of the channel transistor 27 and is connected at the center of each. Specifically, the connection point 187 between the P-channel transistor 175 and the N-channel transistor 181 in the transistor vertical product stage 183 and the substantially center 189 on the gate side of the transistor vertical product stage 185 are connected. It should be noted that substantially the center 191 on the gate side of the transistor vertical product stage 183 is connected to the connection line 39 connected to the tristate control circuit 17, and the P channel transistor 175 and the N channel of the transistor vertical product stage 185 are connected. A connection point 193 connected to the transistor 181 is connected to a connection line 169 connected to the pre-driver 29 of the N-channel transistor 27.

  In this embodiment, two transistor product stages are used. However, the present invention is not limited to this, and any number can be adopted according to the purpose of the differential output circuit. Further, the number of P-type transistors and the number of N-type transistors that constitute the transistor vertical product stage are not limited to this embodiment, and any number can be adopted. If too many transistors are stacked vertically, the area occupied by the circuit will increase, so the number of P-type transistors and N-type transistors to be used is preferably 5 or less, more preferably However, the present invention is not limited to this. Further, the order in which the transistors are vertically stacked is not limited to this embodiment, and any order can be adopted.

  The bias circuit 173 exists in the delay circuit 159, and is connected to the gate of an arbitrary transistor among the transistors included in the transistor vertical stages 183 and 185 of the inverter delay circuit 171 and controls the potential of the connected gate. Plays. In this embodiment, of the N-channel transistors 179 and 181 and the P-channel transistors 175 and 177 included in each of the transistor vertical stages 183 and 185, the gate 195 of the N-channel transistor 181 and the gate 197 of the P-channel transistor 173 are 2 Two gates and a bias circuit 173 are connected to each other, and the potential is controlled by the bias circuit 173. Note that the transistor whose potential is controlled by the bias circuit 173 is not limited to the present embodiment, and can be any transistor existing in the transistor cascade stage.

  The bias circuit 173 includes two resistors, a resistor 199 and a resistor 201. The resistors are divided so that the resistors 199 and 201 have substantially the same value, and are input to the operation output circuit 151. A potential corresponding to substantially half of the power supply voltage is generated and supplied to the gate 195 of the N-channel transistor 181 and the gate 197 of the P-channel transistor 173 connected to each other. For example, when the power supply voltage is 3.3V, the flowing voltage is a voltage of 1.65V.

  In the delay circuit 159 having such a configuration, the delay formed can be changed in accordance with the change in the power supply voltage, rather than the delay formed by the delay circuit 157, that is, the conventional delay circuit. Specifically, when the power supply voltage changes, the delay circuit 159 can form a delay that is approximately twice the delay that the delay circuit 157 forms or a delay that is approximately ½. As a result, even if the power supply voltage changes, it becomes possible to approach the potential with the cross point as a reference. When the power supply voltage is increased, for example, when the voltage is increased from 3.3 V to 3.6 V, the delay circuit 159 forms a delay approximately half the delay formed by the delay circuit 157, so that the signal 169 Is earlier than the timing at which the signal 161 is transmitted, and the timing at which the N-channel transistor 27 starts to flow a logic level 0 current is higher than the timing at which the P-channel transistor 23 starts to flow a logic level 1 current. Will also be faster. Therefore, it becomes possible to approach the potential with the cross point as a reference. Conversely, when the power supply voltage decreases, such as when the voltage decreases from 3.3 V to 3.0 V, the delay circuit 159 forms a delay approximately twice as large as the delay formed by the delay circuit 157, and the signal 169 Is transmitted later than the timing at which the signal 161 is transmitted. Therefore, the timing at which the N-channel transistor 27 starts to flow a logic level 0 current is later than the timing at which the P-channel transistor 23 starts to flow a logic level 1 current. become.

  FIG. 8 is a conceptual diagram of operation waveforms of the DP signal 13 and the DM signal 15 when the power supply voltage changes to the low potential side in the differential output circuit 151 of FIG. In FIG. 8, an operation waveform 211 is an operation waveform of the DP signal 13 output from the positive signal output circuit 153 of FIG. An operation waveform 213 is an operation waveform of the DM signal 15 output from the negative signal output circuit 155 of FIG. The operation waveform 211 and the operation waveform 213 are reference waveforms, and are waveforms when there is no change in the power supply voltage, for example, and in this embodiment, the waveforms when the power supply voltage is 3.3V are shown. Further, the cross point 215 at the intersection of the operation waveform 211 and the operation waveform 213 is a cross point set at the time of design, that is, a reference potential. In this embodiment, the cross point 215 is 1/3 of the power supply voltage 3.3V. The potential of 2 is 1.65V.

  Here, in the conventional differential output circuit, when the power supply voltage changes from 3.3V to 3.0V, the rising waveform of the DM signal output from the negative signal output circuit is that the logic level 1 changes to 3.0V. On the other hand, since the logic level 0 does not change, an operation waveform 217 having a gentler slope than the operation waveform 213 is obtained. Also, in the conventional differential output circuit, when the power supply voltage changes from 3.3V to 3.0V, the falling waveform of the DP signal output from the positive signal output circuit is also set to the logic level 1 like the rising waveform of the DM signal. Since the logic level 0 does not change while changing to 3.0 V, an operation waveform 219 having a gentler slope than the operation waveform 211 is obtained. Accordingly, the cross point 221 at this time is positioned below the cross point 215, and the potential changes from 1.65 to 1.5V.

  On the other hand, in the differential output circuit 151 of the present embodiment, when the power supply voltage changes from 3.3 V to 3.0 V, the operation waveform 217 of the DM signal 15 output from the negative signal output circuit 155 is the conventional differential output circuit. The waveform is substantially the same as that of the DM signal output from the negative signal output circuit, and an operation waveform 217 having a gentler slope than the operation waveform 213 is obtained. This is because, in the negative signal output circuit 155 of the differential output circuit 151 of the present invention, the logic level 1 does not change while the logic level 1 changes to 3.0 V, and the differential output circuit of this embodiment Since the delay circuit 157 in 151 is the same delay circuit as the conventional differential output circuit, the delay formed by the delay circuit 157 does not substantially change even when the power supply voltage changes.

In addition the differential output circuit 151 of the present invention, when the power supply voltage changes to 3.0V from 3.3V, DP signal 13 output from the positive signal output circuit 153, the delay time t ₂ is slower than DM signals 15. In other words, the falling timing of the DP signal 13 is delayed by the delay time t ₂ from the rising timing of the DM signal 15 by the delay circuit 159. This is because, in the delay circuit 159, when the power supply voltage decreases, the delay to be formed changes. That is, the delay circuit 159 forms a larger delay than the delay circuit 157 when the power supply voltage changes to the low potential side, and as a result, delays the timing of transmitting the signal 169 to the pre-driver 29 of the N-channel transistor 27. Therefore, the timing at which the N-channel transistor 27 starts to flow a logic level 0 current can be delayed by the delay time t ₂ from the timing at which the P-channel transistor 23 starts to flow a logic level 1 current. Therefore, the operation waveform 223 of the DP signal 13 in this case is substantially the same as the operation waveform 219 by the conventional differential output circuit, but the timing at which the falling starts is the delay time t than the operation waveform 219. _{2 Since} the waveform is delayed, the cross point 225 at this time can be positioned above the cross point 221 of the conventional differential output circuit, and can be brought closer to the reference cross point 215. become.

  After all, in the differential output circuit of the present invention, it becomes possible to position the cross point when the power supply voltage is changed from 3.3 V to 3.0 V above the cross point by the conventional differential output circuit, It is possible to get closer to the reference cross point. In particular, it is possible to reduce the width of fluctuation of the cross point due to the change of the power supply voltage only by delaying the signal by the delay circuit 159. Therefore, for example, when comparing the power supply voltage and the cross point, an extra element is added. There is no need to use it. Therefore, it is possible to obtain a circuit that has a simple configuration and reduces cross-point variation due to a change in power supply potential, and can prevent an increase in manufacturing cost.

  Although not shown, the delay formed by the delay circuit 159 is caused by the delay circuit 157 even when the power supply voltage changes to the high potential side, for example, when the voltage changes from 3.3 V to 3.6 V. Since the delay is smaller than the formed delay, the falling timing of the DP signal 13 becomes faster than the rising timing of the DM signal 15 and can be brought close to the potential based on the cross point.

  8 illustrates the operation waveforms of the DP signal 13 and the DM signal 15 when the AP signal is at logic level 0 and the AM signal is at logic level 1, the AP signal is at logic level 1 and the AM signal is at logic level 0. When the DP signal 13 and the DM signal 15 are interchanged, that is, the DP signal rises and the DM signal falls, and the others are the same. In this embodiment, the delay circuit 159 is configured to form a delay larger or smaller than the delay formed by the delay circuit 157. However, the present invention is not limited to this, and for example, the present embodiment Conversely, delay circuit 157 can be configured to create a delay that is greater or less than the delay formed by delay circuit 159.

It is a circuit diagram which shows the structure of the Example of the differential output circuit of this invention. It is a conceptual diagram of the operation waveform of AP signal and AM signal. FIG. 2 is a circuit diagram illustrating an example of a configuration of a delay circuit in FIG. 1. FIG. 2 is a circuit diagram illustrating an example of a configuration of a delay circuit in FIG. 1. FIG. 6 is a conceptual diagram of operation waveforms of a DP signal and a DM signal when a P-channel transistor is finished to transmit a signal late. It is a circuit diagram which shows the structure of the Example of another differential output circuit of this invention. FIG. 7 is a circuit diagram illustrating an example of a configuration of a delay circuit in FIG. 6. FIG. 6 is a conceptual diagram of operation waveforms of a DP signal and a DM signal when a power supply voltage is changed to a low potential side.

Explanation of symbols

1 Differential output circuit
3 Positive signal output circuit
5 Negative signal output circuit
7 AP signal
9 AM signal
11 EB signal
13 DP signal

Claims (11)

The first signal is input and the second signal is output, and the third signal that is complementary to the first signal is input and the fourth signal that is complementary to the second signal. In the differential output circuit including the other circuit that outputs the signal of
The differential output circuit, wherein the one circuit delays the first signal according to the characteristic of the fourth signal and outputs the second signal. The differential output circuit according to claim 1, wherein the one circuit is:
A speed of transmitting a signal of the first other conductivity type semiconductor element including the first one conductivity type semiconductor element and a first other conductivity type semiconductor element having a conductivity type opposite to the first one conductivity type semiconductor element A first delay circuit for delaying the first signal according to
A second one-conductivity-type semiconductor element that receives the signal delayed by the first delay circuit and transmits the second signal;
Speed of transmitting a signal of the third one-conductivity-type semiconductor element, including a third one-conductivity-type semiconductor element and a second other-conductivity-type semiconductor element having a conductivity type opposite to the third one-conductivity-type semiconductor element A second delay circuit for delaying the first signal according to
And a third other conductivity type semiconductor element having a conductivity type opposite to the second one conductivity type semiconductor element, which receives the signal delayed by the second delay circuit and transmits the second signal. Feature differential output circuit. 3. The differential output circuit according to claim 2, wherein the other circuit delays the third signal and outputs the fourth signal in accordance with characteristics of the second signal,
A speed including a fourth one-conductivity-type semiconductor element and a fourth other-conductivity-type semiconductor element having a conductivity type opposite to that of the fourth one-conductivity-type semiconductor element; A third delay circuit for delaying the third signal in response to
A fifth one-conductivity-type semiconductor element that receives the signal delayed by the third delay circuit and transmits the fourth signal;
A speed of transmitting a signal of the sixth one-conductivity-type semiconductor element, including a sixth one-conductivity-type semiconductor element and a fifth other-conductivity-type semiconductor element having a conductivity type opposite to that of the sixth one-conductivity-type semiconductor element A fourth delay circuit for delaying the third signal according to
And a sixth other conductivity type semiconductor element having a conductivity type opposite to the fifth one conductivity type semiconductor element, which receives the signal delayed by the fourth delay circuit and transmits the fourth signal. Feature differential output circuit. 4. The differential output circuit according to claim 3, wherein each of the first and fourth other conductivity type semiconductor elements has a gate length substantially the same as a minimum value of the process,
The first and fourth one-conductivity type semiconductor elements each have a gate length longer than the gate length of the first and fourth other-conductivity type semiconductor elements,
At least two first conductive semiconductor elements are connected in series to form a first conductive semiconductor element stage.
At least two fourth other conductivity type semiconductor elements are connected in series to form a second other conductivity type semiconductor element stage;
The first delay circuit delays the first signal according to the speed at which the signal of the first other conductivity type semiconductor element stage is transmitted,
3. The differential output circuit according to claim 3, wherein the third delay circuit delays the third signal in accordance with a speed at which the signal of the second other conductivity type semiconductor element stage is transmitted. 5. The differential output circuit according to claim 4, wherein the gate length of the first one-conductivity-type semiconductor element is at least four times the gate length of the first other-conductivity-type semiconductor element.
A differential output circuit characterized in that the gate length of the fourth one-conductivity-type semiconductor element is at least four times the gate length of the fourth other-conductivity-type semiconductor element. 6. The differential output circuit according to claim 3, wherein each of the third and sixth one-conductivity type semiconductor elements has a gate length substantially the same as a minimum value of the process,
The second and fifth other conductivity type semiconductor elements each have a gate length longer than that of the third and sixth one conductivity type semiconductor elements,
At least two third one-conductivity-type semiconductor elements are connected in series to form a first one-conductivity-type semiconductor element stage,
At least two sixth one-conductivity type semiconductor elements are connected in series to form a second one-conductivity type semiconductor element stage;
The second delay circuit delays the first signal according to the speed at which the signal of the first one-conductivity-type semiconductor element stage is transmitted,
4. The differential output circuit according to claim 4, wherein the fourth delay circuit delays the third signal in accordance with a speed at which the signal of the second one-conductivity-type semiconductor element stage is transmitted. 7. The differential output circuit according to claim 6, wherein the gate length of the second other-conductivity-type semiconductor element is at least four times the gate length of the third one-conductivity-type semiconductor element.
5. The differential output circuit according to claim 5, wherein the gate length of the fifth other conductivity type semiconductor element is at least four times the gate length of the sixth one conductivity type semiconductor element. The differential output circuit according to claim 1, wherein the one circuit is:
A first delay circuit including a first one-conductivity-type semiconductor element and a first other-conductivity-type semiconductor element having a conductivity type opposite to the first one-conductivity-type semiconductor element, and delaying the first signal;
A second one-conductivity-type semiconductor element that receives the signal delayed by the first delay circuit and transmits the second signal;
A second delay circuit including a third one-conductivity-type semiconductor element and a second other-conductivity-type semiconductor element having a conductivity type opposite to the third one-conductivity-type semiconductor element, and delaying the first signal;
A third other-conductivity-type semiconductor element having a conductivity type opposite to the second one-conductivity-type semiconductor element, which receives the signal delayed by the second delay circuit and transmits the second signal;
The differential output circuit, wherein the second delay circuit forms a delay larger or smaller than a delay formed by the first delay circuit when the power supply voltage changes. 9. The differential output circuit according to claim 8, wherein the other circuit delays the third signal and outputs the fourth signal according to the characteristics of the second signal,
A third delay circuit including a fourth one-conductivity-type semiconductor element and a fourth other-conductivity-type semiconductor element having a conductivity type opposite to the fourth one-conductivity-type semiconductor element, and delaying a third signal;
A fifth one-conductivity-type semiconductor element that receives the signal delayed by the third delay circuit and transmits the fourth signal;
A fourth delay circuit including a sixth one-conductivity-type semiconductor element and a fifth other-conductivity-type semiconductor element having a conductivity type opposite to the sixth one-conductivity-type semiconductor element, and delaying the third signal;
A sixth other-conductivity-type semiconductor element having a conductivity type opposite to the fifth one-conductivity-type semiconductor element that receives the signal delayed by the fourth delay circuit and transmits the fourth signal;
The fourth delay circuit forms a delay larger or smaller than a delay formed by the third delay circuit when the power supply voltage changes. 10. The differential output circuit according to claim 9, wherein the third one-conductivity-type semiconductor element and the second other-conductivity-type semiconductor element are connected in cascade to form a first inverter delay circuit,
The sixth one-conductivity-type semiconductor element and the fifth other-conductivity-type semiconductor element are connected in cascade to form a second inverter delay circuit,
The second delay circuit includes a first bias circuit connected to the gate of the third one-conductivity type semiconductor element and the gate of the second other-conductivity type semiconductor element, respectively.
The fourth delay circuit includes a second bias circuit connected to the gate of the sixth one-conductivity-type semiconductor element and the gate of the fifth other-conductivity-type semiconductor element, respectively.
The differential output circuit, wherein each of the first and second bias circuits generates a voltage substantially half the power supply voltage and controls the potential of the connected gate.   11. The differential output circuit according to claim 1, wherein the one conductivity type semiconductor element is a P-type transistor, and the other conductivity type semiconductor element is an N-type transistor. Dynamic output circuit.

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