JP3667447B2 - Output circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an output circuit for controlling a change in an output signal in an output circuit of a semiconductor integrated circuit device.
[0002]
[Prior art]
Generally, a large current is required for high-speed transmission on the output side of a semiconductor integrated circuit device (hereinafter referred to as “integrated circuit”). However, a sharp current change causes noise, which causes malfunction of an integrated circuit and a system in which the integrated circuit is incorporated. In order to avoid this, slew rate control is performed to intentionally suppress the time change of the output signal and suppress the generation of noise.
[0003]
FIG. 16 is a circuit diagram showing an example of a conventional output circuit that performs slew rate control. The prebuffer 200 receives an input signal from inside the integrated circuit, and the main buffer 300 receives the output of the prebuffer 200 and gives an output signal to the output terminal 1.
[0004]
The pre-buffer 2 includes an inverter 41 that receives an input signal and inverters 39 and 40 that invert the output of the inverter 41.
[0005]
The main buffer 300 includes a PMOS transistor 35 and an NMOS transistor 36 each including a gate that receives the output of the inverter 39, and both a PMOS transistor 37 and an NMOS transistor 38 that include a gate that receives the output of the inverter 40, and drains of the transistors 35 and 36. A PMOS transistor 5 including a gate connected in common and an NMOS transistor 6 including a gate connected in common to the drains of the transistors 37 and 38 are provided. The drains of the transistors 5 and 6 are connected to the output terminal 1 in common, the sources of the transistors 35 and 5 are both supplied with the potential Vdd (corresponding to logic “H”), and the sources of the transistors 38 and 6 are connected to In either case, the ground potential GND (corresponding to logic “L”) is applied.
[0006]
However, the channel widths of the transistors 5 and 6 are made larger than the channel widths of the transistors 35 to 38. The NMOS transistor 36 and the PMOS transistor 37 have a longer gate length than the PMOS transistor 35 and the NMOS transistor 38.
[0007]
Due to the difference in gate length, the time required for the gate potential of the PMOS transistor 5 to change from “L” to “H” is very long compared to the time required for the gate potential to change from “L” to “H”. . Similarly, as compared with the time required for the gate potential of the NMOS transistor 6 to change from “H” to “L”, the time required to change from “L” to “H” becomes very long. As a result, the transistors 5 and 6 are all turned off quickly and turned on slowly.
[0008]
FIG. 17 is a diagram showing the operation of each part of the output circuit shown in FIG. 16 when the output signal changes from “L” to “H”. FIGS. 9A to 9G are respectively an input signal from the integrated circuit, an output of the inverter 39 (the output of the inverter 40 also exhibits the same waveform), a gate potential of the PMOS transistor 5, a gate potential of the NMOS transistor 6, The potential of the output terminal 1, the output current (current flowing to the output terminal 1), and the on / off states of the transistors 36, 5, 38, 6, 35, and 37 are shown.
[0009]
When the input signal changes from “L” to “H” at time T1, the outputs of the inverters 39 and 40 change from “L” to “H” in response thereto. The PMOS transistor 37 and the NMOS transistor 38 are turned off and on, respectively. As a result, the NMOS transistor 6 is turned on. This is due to the on-state of the transistor 38 having a short gate length, so that the operation is quick. That is, the NMOS transistor 6 is turned off at about time T1.
[0010]
However, since the PMOS transistor 5 is turned on because the transistor 36 having a long gate length is turned on, its operation is slow. That is, the transistor 5 is not completely turned on at the time T1, and the NMOS transistor 6 is finally completely turned on at the time T2 delayed from the time T1. From the above, the output signal changes slowly as a result when viewed over the entire changing time.
[0011]
The generated noise becomes larger as the causative of the current causing the current becomes larger, but since the change time required for the output circuit to reach the maximum current is determined according to the standard, it is desirable that the current value is small. If the potential output from the output circuit changes abruptly, the current flowing at that time increases, so it is desirable that the potential of the output terminal 1 change linearly.
[0012]
In the conventional technique shown in FIG. 16, a desired slew rate is realized by making the change time necessary for turning on and off the transistors 5 and 6 asymmetrical.
[0013]
[Problems to be solved by the invention]
In the conventional technique, the change is large at the initial stage (time T1 to T2) when the output signal changes, and conversely, the change becomes very gradual at the end of the change (after time T2). In other words, it has not been possible to suppress the change of the output signal from changing greatly at the initial stage, and accordingly, the generation of noise could not be sufficiently suppressed.
[0014]
In addition, in a master slice type integrated circuit, all usable transistors must be arranged and prepared in advance. In order to make it possible to design an output circuit with improved slew rate using conventional techniques, it is necessary to prepare a plurality of transistors having different gate lengths. However, the area that the output circuit can occupy on the integrated circuit is limited, and in order to prepare transistors other than the standard gate length, the number of transistors having the standard gate length must be reduced. When standard gate length transistors are employed as the transistors 35 and 38 in FIG. 16, in order to form the transistors 36 and 37, it is necessary to provide a transistor having a gate length longer than that of the standard. As a result, there is a problem that the degree of freedom of design, which is an advantage of the master slice method, is significantly impaired.
[0015]
The present invention has been made to solve the above-described problems, and provides an output circuit with improved slew rate without changing the gate length of a transistor to be used. The purpose is to suppress the noise by controlling the time change of the output signal.
[0016]
[Means for Solving the Problems]
A first aspect of the present invention includes an input terminal to which an input signal in accordance with binary logic is given, and an output terminal that outputs an output signal that transitions in response to the logic transition of the input signal. This is an output circuit. (A) (a-1) a first electrode to which a first potential corresponding to a first logic value that is one of the binary logics is applied, a second electrode connected to the output terminal, A first main transistor having a control electrode for receiving a main control signal; and (a-2) a second potential corresponding to a second logic value complementary to the first logic value of the binary logic. A second main transistor having one electrode, a second electrode connected to the output terminal, and a control electrode for receiving a second main control signal; and (a-3) a first to which the first potential is applied. A first sub-transistor having an electrode, a second electrode connected to the output terminal, and a control electrode for receiving a first sub-control signal; and (a-4) a first electrode to which the second potential is applied. And a second sub-transistor having a second electrode connected to the output terminal and a control electrode for receiving a second sub-control signal. (B) a pre-buffer that generates the first and second main control signals based on the input signal, and (c) (c-1) the second threshold value that exceeds the first threshold value. The first main control signal is output as the first sub control signal when the output signal reaches the first threshold value during the transition from the value close to the potential toward the first potential. And (c-2) the output signal is transferred to the second threshold value during the transition from the value closer to the first potential to the second potential than the second threshold value. And a control circuit having a second logic gate that outputs the second main control signal as the second sub-control signal.
[0017]
According to a second aspect of the present invention, there is provided the output circuit according to the first aspect, wherein the first and second thresholds with respect to an intermediate value between the first potential and the second potential. The values are close to the first and second potentials, respectively.
[0018]
According to a third aspect of the present invention, there is provided the output circuit according to the second aspect, wherein the first main transistor is configured such that the first main control signal corresponds to the second logic value. The second main transistor is used when the second main control signal corresponds to the first logic value, and the first sub-transistor is used when the first sub control signal corresponds to the second logic value. The second sub-transistors are turned on when the second sub-control signal corresponds to the first logic value. The first logic gate includes: (c-1-1) an inverter that inverts the output signal with the first threshold value; and (c-1-2) the inverter of the first logic gate. An output and a logic element that outputs the second logic value as the first sub-control signal when both of the first main control signals take the second logic value. The second logic gate includes: (c-2-1) an inverter that inverts the output signal with the second threshold; and (c-2-2) the inverter of the second logic gate. And a logic element that outputs the first logic value as the second sub-control signal when both the output and the second main control signal take the first logic value.
[0019]
According to a fourth aspect of the present invention, there is provided the output circuit according to the second aspect, wherein the first and second logic gates are configured such that the output signal is set to the second potential with respect to the first threshold value. When the output signal reaches the first threshold value during the transition from a close value toward the first potential, the second logic is set, and the output signal exceeds the second threshold value. A hysteresis circuit that outputs the first logic when the output signal reaches the second threshold value during the transition from a value close to one potential toward the second potential is shared. The first logic gate outputs the second logic value as the first sub-control signal when the output of the hysteresis circuit and the first main control signal both take the second logic value. And a logic element. The second logic gate outputs the first logic value as the second sub-control signal when the output of the hysteresis circuit and the second main control signal both take the first logic value. And a logic element.
[0020]
A fifth aspect of the present invention is the output circuit according to the first aspect, wherein the first threshold value and the second threshold value are equal.
[0021]
According to a sixth aspect of the present invention, in the output circuit according to any one of the first to fifth aspects, the prebuffer inputs the input signal and the state control signal, and When the control signal is inactive, the logic based only on the input signal is output in common as the first and second main control signals, and when the control signal is inactive, the logic is related to the input signal. First, both the first main control signal and the second main control signal are deactivated, and both the first and second main transistors are turned off.
[0022]
A seventh aspect of the present invention is the output circuit according to the first aspect, wherein the main buffer is connected to the first electrode to which the first potential is applied and the output terminal. A third sub-transistor having a second electrode and a control electrode for receiving a third sub-control signal; (a-6) a first electrode to which the second potential is applied; and the output terminal. A fourth sub-transistor having a second electrode and a control electrode for receiving a fourth sub-control signal; And (c-3) the output signal reaches the third threshold value during the transition from the value closer to the second potential than the third threshold value toward the first potential. A third logic gate that outputs the first main control signal as the third sub-control signal, and (c-4) a value closer to the first potential than a fourth threshold value. A fourth logic gate that outputs the second main control signal as the fourth sub-control signal when the output signal reaches the fourth threshold value during the transition toward the second potential. It has further.
[0023]
According to an eighth aspect of the present invention, in the output circuit according to the seventh aspect, the third threshold value is equal to the second threshold value, and the fourth threshold value is the first threshold value. Equal to threshold.
[0024]
According to a ninth aspect of the present invention, there is provided an input terminal to which an input signal in accordance with a binary logic is given, and an output terminal for outputting an output signal that transitions in response to the logic transition of the input signal. This is an output circuit. And a first end to which a first potential corresponding to a first logic value of the binary logic is applied, and a second end connected to the output terminal. A main switching element that conducts / non-conducts between the ends, a first end to which the first potential is applied, and a second end connected to the output terminal. And a sub-switching element that conducts / non-conducts between the two ends. Here, when the main switching element is turned on from the state where both the main switching element and the sub switching element are non-conductive due to the transition of the input signal, the sub switching element is turned on after the main switching element is turned on. Also conduct.
[0025]
A tenth aspect of the present invention is the output circuit according to the ninth aspect, wherein the main switching element has a smaller current flow than the sub-switching element.
[0026]
According to an eleventh aspect of the present invention, in the output circuit according to the ninth aspect, the main switching element and the sub-switching element are constituted by transistors.
[0027]
According to a twelfth aspect of the present invention, in the output circuit according to the ninth aspect, the potential of the output signal is complementary to the first logic value of the binary logic due to the conduction of the main switching element. When the potential of the output signal reaches a predetermined threshold value due to the transition, the sub switching element starts to conduct. .
[0028]
In the present application, “threshold” means not a threshold of a gate voltage for controlling on / off of a transistor but a logical threshold for discriminating “L” / “H”.
[0029]
DETAILED DESCRIPTION OF THE INVENTION
Basic thought.
In order to achieve an ideal slew rate, in order to moderate the initial change in which the output signal changes, the main drive means is first driven to change the output signal. The driving means may be driven so as to change the output signal in the same direction.
[0030]
FIG. 1 is a circuit diagram showing a basic configuration of an output circuit according to the present invention. The prebuffer 2 receives an input signal from the integrated circuit, and the main buffer 3 receives the output of the prebuffer 2 and outputs a signal to the output terminal 1 of the integrated circuit.
[0031]
The feedback circuit 4 detects the potential of the output terminal 1, compares it with the output of the prebuffer 2, and controls the main buffer 3. Specifically, by positively feeding back the potential of the output terminal 1, it is possible to control the current flowing into (or flowing out) the output terminal 1 in accordance with the gradual change of the time.
[0032]
Embodiment 1 FIG.
FIG. 2 is a circuit diagram showing the configuration of the output circuit according to the first embodiment of the present invention. The pre-buffer 201 is composed of inverters 9 and 10 that receive input signals inside the integrated circuit. The feedback circuit 401 receives the potential of the output terminal 1 and inverts and outputs the first and second thresholds, respectively, and the two-input NOR that receives the output of the inverter 11 and the output of the inverter 9. The gate 13, the inverter 14 that inverts the output of the NOR gate 13, the two-input NAND gate 15 that receives the output of the inverter 12 and the output of the inverter 10, and the inverter 16 that inverts the output of the NAND gate 15.
[0033]
In the main buffer 301, the source is supplied with the potential Vdd, the drain is connected to the output terminal 1, the output of the inverter 9 is input to the gate of the PMOS transistor 5, the source is supplied with the ground potential GND, and the drain is connected to the output terminal 1. NMOS transistor 6 to which the output of the inverter 10 is inputted to the gate, the potential Vdd is given to the source, the drain is connected to the output terminal 1, and the PMOS transistor 7 to which the output of the inverter 14 is inputted to the gate, the source Is connected to the output terminal 1 and the output of the inverter 16 is input to the gate of the NMOS transistor 8.
[0034]
The first and second threshold values are set to 2 Vdd / 3 and Vdd / 3, respectively.
[0035]
The transistors 5 and 6 correspond to the main driving means described in the “basic idea” in the previous section, and the transistors 7 and 8 correspond to the sub driving means. Transistors 7 and 8 have a wider channel width than transistors 5 and 6, respectively.
[0036]
The output of the inverter 9 functions as a first main control signal M1 that controls the conduction of the transistor 5, and the output of the inverter 10 functions as a second main control signal M2 that controls the conduction of the transistor 6. The output of the inverter 14 functions as a first sub-control signal S1 that controls the conduction of the transistor 7, and the output of the inverter 10 functions as a second sub-control signal S2 that controls the conduction of the transistor 6.
[0037]
FIG. 3 is a diagram showing the operation of each part when the output signal changes from “L” to “H” at the output terminal 1. 4A to 4H are respectively an input signal from the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the NAND gate 15, and an inverter 11. , The output of the NOR gate 13, the potential of the output terminal 1, the output current (current flowing to the output terminal 1), and the on / off states of the transistors 5-8.
[0038]
First, since the input signal is “L”, the first main control signal M1 is “H”, and the PMOS transistor 5 is in the OFF state. Since the first main control signal M1 is applied to one of its input terminals, the NOR gate 13 outputs "L" regardless of the output value of the inverter 11. Therefore, the first sub control signal S1 is “H”, and the PMOS transistor 7 is also in the OFF state.
[0039]
On the other hand, the second main control signal M2 is “H”, and the NMOS transistor 6 is in the ON state. Since the PMOS transistors 5 and 7 are in the off state, the potential of the output terminal 1 is at the ground potential GND regardless of whether the NMOS transistor 8 is on or off. Accordingly, since the second main control signal M2 is “H” and the output of the inverter 12 that has inverted the potential of the output terminal 1 is “H”, the input of the NAND gate 15 is “L”. Become. Therefore, the second sub control signal S2 obtained by inverting this by the inverter 16 becomes "H", and the NMOS transistor 8 is also in the ON state.
[0040]
From this state, when the input signal from the integrated circuit changes from “L” to “H” at time T1, both the first main control signal M1 and the second main control signal M2 are “H”. From "L" to "L", the PMOS transistor 5 is immediately turned on and the NMOS transistor 6 is turned off. Since the second main control signal M2 becomes “L”, the output of the NAND gate 15 changes from “L” to “H” regardless of the output of the inverter 12, so that the second sub control signal S2 Becomes “L”, and the NMOS transistor 8 is turned off at approximately the same time as the time T1.
[0041]
As described above, when the input signal changes from “L” to “H” at time T1, the NMOS transistors 6 and 8 are turned off and the PMOS transistor 5 is turned on regardless of the potential of the output terminal 1. Therefore, the potential of the output terminal 1 rises from the ground potential GND toward the potential Vdd. However, until the potential reaches the first threshold value 2Vdd / 3, the inverter 11 determines that the potential of the output terminal 1 is “L”, and the output remains “H”. Therefore, the output of the NOR gate 13 maintains “L”, and the PMOS transistor 7 remains off.
[0042]
When the PMOS transistor 5 is turned on, the potential of the output terminal 1 continues to rise. When the potential of the output terminal 1 becomes the first threshold value 2Vdd / 3 at time T2, the output of the inverter 11 becomes “H”. To “L”. As a result, since all inputs of the NOR gate 13 are “L”, the output is changed from “L” to “H”, and the first sub control signal S1 is changed from “H” to “L”. As a result, the PMOS transistor 7 which has been turned off is turned on.
[0043]
As a result, at time T2, the output terminal 1 is connected to the potential Vdd via the two PMOS transistors 5 and 7, so that the current supplied to the output terminal 1 is increased and the rate of increase in the potential of the output terminal 1 is increased. Becomes larger. Since the output of the NAND gate 15 does not depend on the output of the inverter 12 and is “H” as long as the second main control signal M 2 is “L”, the second sub control signal S 2 is output from the output terminal 1. It remains “L” regardless of the potential. Therefore, the NMOS transistors 6 and 8 remain off even at time T2, and they do not affect the potential of the output terminal 1.
[0044]
FIG. 4 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from “H” to “L”. FIGS. 7A to 7H are respectively an input signal from the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the NAND gate 15, and an inverter 12. , The output of the NOR gate 13, the potential of the output terminal 1, the output current (current flowing from the output terminal 1 to the ground), and the on / off states of the transistors 5-8.
[0045]
First, since the input signal is “H”, both the first main control signal M1 and the second main control signal M2 are “L”, and the NMOS transistor is the same as after the time T2 shown in FIG. 5 and 7 are turned on, and the PMOS transistors 6 and 8 are turned off. The potential of the output terminal 1 is Vdd. Both the inverters 11 and 12 output “L”.
[0046]
From this state, when the input signal changes from “H” to “L” at time T3, both the first main control signal M1 and the second main control signal M2 change from “L” to “H”. The NMOS transistor 6 is immediately turned on and the PMOS transistor 5 is turned off. Further, since the output of the NOR gate 13 changes from “H” to “L” regardless of the output of the inverter 11 when the first main control signal M1 becomes “H”, the first sub control signal S1 Becomes “H”, and the PMOS transistor 7 is turned off at approximately the same time as time T3.
[0047]
As described above, when the input signal changes from “H” to “L” at time T 3, the PMOS transistors 5 and 7 are turned off and the NMOS transistor 6 is turned on regardless of the potential of the output terminal 1. Therefore, the potential of the output terminal 1 drops from the potential Vdd toward the ground potential GND. However, until the potential reaches the second threshold value Vdd / 3, the inverter 12 determines that the potential of the output terminal 1 is “H”, and the output remains “L”. Therefore, the output of the NAND gate 15 maintains “H”, and the NMOS transistor 8 remains off.
[0048]
When the NMOS transistor 6 is turned on, the potential of the output terminal 1 continues to decrease. When the potential of the output terminal 1 reaches the second threshold value Vdd / 3 at time T4, the output of the inverter 12 is “L”. To “H”. As a result, all inputs of the NAND gate 15 become “H”, so that the output changes from “H” to “L”, and the second sub-control signal S2 changes from “L” to “H”. As a result, the NMOS transistor 8 that has been turned off is turned on.
[0049]
As a result, at time T4, the output terminal 1 is connected to the ground potential GND via the two NMOS transistors 6 and 8, so that the current flowing out from the output terminal 1 increases and the rate of decrease in the potential of the output terminal 1 increases. growing. Since the output of the NOR gate 13 does not depend on the output of the inverter 11 and is “L” as long as the first main control signal M1 is “H”, the first sub control signal S1 is output from the output terminal 1. It remains “H” regardless of the potential. Accordingly, the PMOS transistors 5 and 7 remain off even at time T4, and they do not affect the potential of the output terminal 1.
[0050]
The configuration of the main buffer 3 is divided into two stages of transistors 5 and 6 as main driving means and transistors 7 and 8 as sub driving means that operate by applying positive feedback. By controlling with a control signal and a sub control signal delayed from the main control signal, the current flowing into (or flowing out) the output terminal 1 can be controlled.
[0051]
In particular, by setting the channel widths of the transistors 5 and 6 to be narrower than those of the transistors 7 and 8, the former current driving capability is small. Accordingly, it is possible to alleviate the potential change particularly at the rise and fall times of the output signal.
[0052]
Furthermore, by designing the inverters 11 and 12 that detect the potential of the output terminal 1 to have different threshold values, positive feedback can be applied at the end of the change of the potential of the output terminal 1. Accordingly, the rate of change in potential can be increased when the change in potential at the output terminal 1 has become gradual, and the change in current at the output terminal 1 can be brought closer to a straight line during the change period, thereby suppressing noise. Can do.
[0053]
Further, in the layout, it is not necessary to use a transistor having a channel length different from that of the transistors 36 and 37 in the prior art, and only a standard gate length transistor is provided on the master in the master slice type integrated circuit. Should be placed. Thereby, the freedom degree of the circuit design of an output circuit can be improved.
[0054]
Embodiment 2. FIG.
FIG. 5 is a circuit diagram showing a configuration of an output circuit according to Embodiment 2 of the present invention. Compared with the output circuit shown in the first embodiment, the feedback circuit 401 is replaced with a feedback circuit 402.
[0055]
The feedback circuit 402 includes inverters 19 and 21 that invert the first main control signal M1 and the second main control signal M2, respectively, and an inverter 17 that inverts and outputs the same with the same threshold value, for example, Vdd / 2. , 18 in series and the outputs of the inverters 18 and 19 and the two-input NAND gate 20 that outputs the first sub-control signal S1 and the outputs of the inverters 18 and 21 and the second sub-control signal S2 It comprises a 2-input NOR gate 22 for output. The input terminal of the inverter 17 is connected to the output terminal 1.
[0056]
The feedback circuit 402 has a configuration in which the first threshold value and the second threshold value in the feedback circuit 401 are equal. In other words, the series circuit of the NOR gate 13 and the inverter 14 in the feedback circuit 401 is replaced logically equivalently by the inverters 18 and 19 and the NAND gate 20 in the feedback circuit 402. Similarly, the series circuit of the NAND gate 15 and the inverter 16 in the feedback circuit 401 is logically equivalently replaced by the inverters 18 and 21 and the NOR gate 22 in the feedback circuit 402. The inverters 11 and 12 in the feedback circuit 401 are both logically equivalently replaced by the inverter 17 in the feedback circuit 402.
[0057]
Comparing the feedback circuits 401 and 402 with each other, there is no difference in that each of the feedback circuits 401 and 402 includes one NOR gate and one NAND gate and four inverters. However, it is necessary to form logic elements having the same threshold value as inverters 17 and 18 as compared with the case of forming logic elements having different threshold values such as inverters 11 and 12. The layout area can be reduced.
[0058]
For example, in order to form a logic element having a threshold value of 2 Vdd / 3 as in the inverter 11 shown in the first embodiment, the ratio of the channel width of the PMOS transistor to the channel width of the NMOS transistor is set to 4-8. It needs to be about. On the other hand, in order to form a logic element having a threshold value of Vdd / 2 as in the inverters 17 and 18 shown in the second embodiment, it is sufficient to set the above ratio to about 2. That is, the inverter 17 has an advantage that the area occupied by the PMOS transistor can be suppressed more than the inverter 11.
[0059]
FIG. 6 is a diagram showing the operation of each part when the output signal changes from “L” to “H” at the output terminal 1. FIGS. 7A to 7H are respectively an input signal from the inside of the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the inverter 18, a first The sub control signal S1, the second sub control signal S2, the potential of the output terminal 1, the output current (current flowing to the output terminal 1), and the on / off states of the transistors 5 to 8 are shown.
[0060]
First, since the input signal is “L”, the first main control signal M1 is “H”, and the PMOS transistor 5 is in the OFF state. Since the NAND gate 20 receives at one of its input terminals “L” obtained by inverting the first main control signal M 1 as the output of the inverter 19, the first sub control signal S 1 does not depend on the output value of the inverter 18. “H” is output. As a result, the PMOS transistor 7 is also off.
[0061]
On the other hand, the second main control signal M2 is “H”, and the NMOS transistor 6 is in the ON state. Since the PMOS transistors 5 and 7 are in the off state, the potential of the output terminal 1 is at the ground potential GND regardless of whether the NMOS transistor 8 is on or off. At each input of the NOR gate 22, the inverter 21 inverts and outputs the inversion of the second main control signal M2 to “L”, and the output of the inverter 18 inverts the logic of the potential of the output terminal 1 twice (accordingly). Therefore, the NOR gate 22 outputs “H” as the second sub control signal S2, and the NMOS transistor 8 is also in the ON state.
[0062]
From this state, when the input signal from the integrated circuit changes from “L” to “H” at time T1, both the first main control signal M1 and the second main control signal M2 are “H”. From "L" to "L", the PMOS transistor 5 is immediately turned on and the NMOS transistor 6 is turned off. Further, when the second main control signal M2 becomes “L”, the second sub control signal S2 becomes “L” regardless of the output of the inverter 18, and the NMOS transistor 8 is turned off at substantially the same time as the time T1. .
[0063]
As described above, when the input signal changes from “L” to “H” at time T1, the NMOS transistors 6 and 8 are turned off and the PMOS transistor 5 is turned on regardless of the potential of the output terminal 1. Therefore, the potential of the output terminal 1 rises from the ground potential GND toward the potential Vdd. However, until the potential reaches the threshold value Vdd / 2, the inverter 17 determines that the potential of the output terminal 1 is “L”, and the output of the inverter 18 remains “L”. Therefore, the first sub control signal S1 maintains “H”, and the PMOS transistor 7 remains off.
[0064]
When the PMOS transistor 5 is turned on, the potential of the output terminal 1 continues to rise. When the potential of the output terminal 1 reaches the threshold value Vdd / 2 at time T2, the output of the inverter 18 changes from “L” to “H”. ”. As a result, all inputs of the NAND gate 20 become “H”, so that the first sub control signal S1 changes from “H” to “L”. As a result, the PMOS transistor 7 which has been turned off is turned on.
[0065]
As a result, at time T2, the output terminal 1 is connected to the potential Vdd via the two PMOS transistors 5 and 7, so that the current supplied to the output terminal 1 is increased and the rate of increase in the potential of the output terminal 1 is increased. Becomes larger. As long as the second main control signal M2 is “H”, the second sub-control signal S2 does not depend on the potential of the output terminal 1 and remains “L”. Therefore, the NMOS transistors 6 and 8 remain off even at time T2, and they do not affect the potential of the output terminal 1.
[0066]
FIG. 7 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from “H” to “L”. FIGS. 7A to 7H are respectively an input signal from the inside of the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the inverter 18, a first The sub control signal S1, the second sub control signal S2, the potential of the output terminal 1, the output current (current flowing from the output terminal 1 to the ground), and the on / off states of the transistors 5 to 8 are shown.
[0067]
First, since the input signal is “H”, both the first main control signal M1 and the second main control signal M2 are “L”, and the NMOS transistor is the same as after the time T2 shown in FIG. 5 and 7 are turned on, and the PMOS transistors 6 and 8 are turned off. The potential of the output terminal 1 is Vdd. The inverter 18 outputs “H”.
[0068]
From this state, when the input signal changes from “H” to “L” at time T3, both the first main control signal M1 and the second main control signal M2 change from “L” to “H”. The NMOS transistor 6 is immediately turned on and the PMOS transistor 5 is turned off. Further, when the first main control signal M1 becomes “H”, the first sub control signal S1 becomes “H” regardless of the output of the inverter 18, and the PMOS transistor 7 is turned off at substantially the same time as time T3. .
[0069]
As described above, when the input signal changes from “H” to “L” at time T 3, the PMOS transistors 5 and 7 are turned off and the NMOS transistor 6 is turned on regardless of the potential of the output terminal 1. Therefore, the potential of the output terminal 1 drops from the potential Vdd toward the ground potential GND. However, until the potential reaches the threshold value Vdd / 2, the inverter 17 determines that the potential of the output terminal 1 is “H”, and the output of the inverter 18 remains “H”. Therefore, the second sub control signal S2 maintains “L”, and the NMOS transistor 8 remains off.
[0070]
When the NMOS transistor 6 is turned on, the potential at the output terminal 1 continues to decrease. When the potential at the output terminal 1 reaches the threshold value Vdd / 2 at time T4, the output of the inverter 18 changes from “H” to “L”. ”. As a result, since all inputs of the NOR gate 22 become “L”, the second sub control signal S2 changes from “L” to “H”. As a result, the NMOS transistor 8 that has been turned off is turned on.
[0071]
As a result, at time T4, the output terminal 1 is connected to the ground potential GND via the two NMOS transistors 6 and 8, so that the current flowing out from the output terminal 1 increases and the rate of decrease in the potential of the output terminal 1 increases. growing. Regardless of the output of the inverter 18, as long as the first main control signal M1 is “H”, the first sub-control signal S1 remains “H”. Accordingly, the PMOS transistors 5 and 7 remain off even at time T4, and they do not affect the potential of the output terminal 1.
[0072]
With the circuit configuration as described above, substantially the same effect as that of the first embodiment can be obtained, and a necessary layout area can be reduced.
[0073]
Embodiment 3 FIG.
In the first embodiment and the second embodiment, the potential of the output terminal 1 is applied to the inverters 11, 12, and 17. Therefore, the potential fluctuation of the output terminal 1 in the vicinity of these threshold values is reflected in these outputs, and there is a possibility that malfunction occurs when noise occurs in the output terminal 1. Therefore, in the third embodiment, noise resistance is achieved by using a circuit having hysteresis (hereinafter referred to as “hysteresis circuit”) as an element for detecting the potential of the output terminal 1 instead of an inverter having a single threshold value. Disclose technology to strengthen
[0074]
FIG. 8 is a circuit diagram showing a configuration of an output circuit according to Embodiment 3 of the present invention. Compared with the output circuit shown in Embodiment Mode 1, the feedback circuit 401 is replaced with a feedback circuit 403.
[0075]
The feedback circuit 403 has a configuration in which the inverters 11 and 12 of the feedback circuit 401 are replaced with the hysteresis circuit 23. The hysteresis circuit 23 includes an input terminal connected to the output terminal 1, a first output terminal connected to one of the input terminals of the NOR gate 13, and a second output terminal connected to one of the input terminals of the NAND gate 15. And have.
[0076]
FIG. 9 is a graph showing the hysteresis property of the hysteresis circuit 23. When the potential of the output terminal 1 changes from “L” to “H”, the higher threshold value Vth2 is used. On the other hand, when changing from “H” to “L”, the lower threshold value Vth1 is used. Based on these threshold values, the hysteresis circuit 23 inverts the output signal and outputs it to the first and second output terminals.
[0077]
In the following description of the operation, the case where the same output is applied to both the first and second output terminals is shown for the sake of simplicity, but the output signal is inverted and output at the first output terminal with threshold values Vth1 and Vth2. The hysteresis circuit 23 may be configured so that the output signal is inverted and output at the second output terminal with threshold values Vth3 (≠ Vth1) and Vth4 (> Vth3).
[0078]
If the hysteresis circuit 23 shown in FIG. 9 is used, the main buffer 301 operates in the same manner as in the first embodiment. In the first embodiment, the first threshold value corresponds to Vth2, the second threshold value corresponds to Vth1, and when the first main control signal M1 is "H", the output signal state is set. Regardless, the first sub control signal S1 is also “H”, and when the second main control signal M2 is “L”, the second sub control signal S2 is also “L” regardless of the state of the output signal. Yes, even if the NOR gate 13 and the NAND gate 15 receive the output of the hysteresis circuit 23 in common, the logical values of the first sub control signal S1 and the second sub control signal S2 are not different from those of the first embodiment. is there.
[0079]
Therefore, according to the third embodiment, the effect of the first embodiment can be obtained while enhancing noise resistance.
[0080]
Embodiment 4 FIG.
Although the output circuits shown in Embodiments 1 to 3 output an output signal that changes due to the transition of the input signal, the present invention can be used even when a signal for controlling the output circuit is also input to control the output signal. Is applicable. Hereinafter, a case where the present invention is applied to a tristate output circuit will be described as an example.
[0081]
10 is a circuit diagram showing a configuration of an output circuit according to Embodiment 4 of the present invention. Compared with the output circuit shown in the first embodiment, the pre-buffer 201 is replaced with the pre-buffer 202.
[0082]
The pre-buffer 202 inverts the output of the inverter 24 that receives the control signal for controlling the operation state of the output circuit, the inverter 25 that receives the input signal, the NAND gate 28 that receives the outputs of the inverters 24 and 25, and the output of the NAND gate 28. The inverter 10, the inverter 26 that inverts the output of the inverter 24, the NOR gate 27 that receives the outputs of the inverters 25 and 26, and the inverter 9 that inverts the output of the NOR gate 27.
[0083]
When the control signal is “L”, the outputs of the inverters 24 and 26 are “H” and “L”, respectively, and both the NAND gate 28 and the NOR gate 27 function as inverters. On the other hand, since the input signal is once inverted by the inverter 25, the inverters 9 and 10 both output a value obtained by inverting the input signal. That is, when the control signal is “L”, the same function as the pre-buffer 201 is achieved.
[0084]
When the control signal is “H”, the outputs of the inverters 24 and 26 are “L” and “H”, respectively, and the NOR gate 27 and the NAND gate 28 are respectively “ L "and" H "are output. Therefore, the first main control signal M1 and the second main control signal M2 output “H” and “L”, respectively.
[0085]
Since the first main control signal M1 and the second main control signal M2 are “H” and “L”, respectively, the outputs of the NOR gate 13 and the NAND gate 15 do not depend on the logic state of the output terminal 1, respectively. “L”, “H”. Therefore, the first sub control signal S1 and the second sub control signal S2 are “H” and “L”, respectively. As a result, all the transistors 5 to 8 in the main buffer 3 are turned off. That is, the output circuit gives a high impedance state to the output terminal 1.
[0086]
As described above, by replacing the prebuffer 201 shown in the first embodiment with the prebuffer 202, the present invention is also applied to an output circuit whose operation is changed by a control signal, such as a tristate output circuit. And the effect of Embodiment 1 can also be acquired.
[0087]
Embodiment 5 FIG.
FIG. 11 is a circuit diagram showing a configuration of an output circuit according to the fifth embodiment of the present invention. Compared with the output circuit shown in the second embodiment, the prebuffer 201 is replaced with a prebuffer 202. Therefore, the output circuit shown in the present embodiment is a tristate output circuit, and the effects of the second embodiment can be obtained.
[0088]
Embodiment 6 FIG.
12 is a circuit diagram showing a configuration of an output circuit according to Embodiment 6 of the present invention. Compared with the output circuit shown in the third embodiment, the pre-buffer 201 is replaced with the pre-buffer 202. Therefore, the output circuit shown in the present embodiment is a tristate output circuit, and the effects of the third embodiment can be obtained.
[0089]
Embodiment 7 FIG.
13 is a circuit diagram showing a configuration of an output circuit according to Embodiment 7 of the present invention. Compared with the output circuit shown in the first embodiment, the feedback circuit 401 is replaced with a feedback circuit 404, and the main buffer 301 is replaced with a main buffer 302.
[0090]
The feedback circuit 404 inverts the output of the inverter 12 and the first main control signal M1 to the configuration of the feedback circuit 401 and inverts the output of the NOR gate 31 and the third sub control signal S3. Are added, inverter 32 that receives the output of inverter 11 and second main control signal M2, inverter 34 that inverts the output of NAND gate 33 and outputs fourth sub-control signal S4 is added. It has a configuration.
[0091]
The main buffer 302 has a configuration in which a PMOS transistor 29 and an NMOS transistor 30 are added to the configuration of the main buffer 301. The PMOS transistor 29 receives the third sub-control signal S3 at its gate, is supplied with the potential Vdd, and has its drain connected to the output terminal 1. Further, the NMOS transistor 30 has the gate supplied with the fourth sub-control signal S4, the source supplied with the ground potential GND, and the drain connected with the output terminal 1.
[0092]
The transistors 29 and 30 are set to have a larger channel width than the transistors 5 and 6 and smaller than the transistors 7 and 8.
[0093]
FIG. 14 is a diagram showing the operation of each part when the output signal changes from “L” to “H” at the output terminal 1. FIGS. 9A to 9J are respectively an input signal from the inside of the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the inverter 11, and an inverter 12 Output, output of NOR gate 31, output of NOR gate 13, output potential of output terminal 1 of NAND gates 15 and 33, output current (current flowing to output terminal 1), ON / OFF of transistors 5-8, 29, 30 Indicates the off state.
[0094]
First, since the input signal is “L”, the first main control signal M1 is “H”, and the PMOS transistor 5 is in the OFF state. Since both the NOR gates 13 and 31 have the first main control signal M1 applied to one of their input terminals, they output "L" regardless of the output values of the inverters 11 and 12. Therefore, the first sub control signal S1 and the third sub control signal S3 are both “H”, and the PMOS transistors 7 and 29 are also in the off state.
[0095]
On the other hand, the second main control signal M2 is “H”, and the NMOS transistor 6 is in the ON state. Since the PMOS transistors 5, 7, and 29 are in the off state, the potential of the output terminal 1 is at the ground potential GND regardless of whether the NMOS transistors 8 and 30 are on or off. Accordingly, each input of the NAND gate 15 is “H” for the second main control signal M2 and “H” for the output of the inverter 12 that inverts the potential of the output terminal 1, so that the output of the NAND gate 15 is “L”. Become. Therefore, the second sub control signal S2 obtained by inverting this by the inverter 16 becomes "H", and the NMOS transistor 8 is also in the ON state. Each input of the NAND gate 33 is “H” for the second main control signal M2 and “H” for the output of the inverter 11 that inverts the potential of the output terminal 1, so that the output of the NAND gate 33 is also “L”. Become. Therefore, the fourth sub control signal S4 obtained by inverting this by the inverter 34 becomes "H", and the NMOS transistor 30 is also in the ON state.
[0096]
From this state, when the input signal from the integrated circuit changes from “L” to “H” at time T1, both the first main control signal M1 and the second main control signal M2 are “H”. From "L" to "L", the PMOS transistor 5 is immediately turned on and the NMOS transistor 6 is turned off. Since the second main control signal M2 becomes “L”, the outputs of the NAND gates 15 and 33 change from “L” to “H” regardless of the outputs of the inverters 11 and 12, so that the second The sub control signal S2 and the fourth sub control signal S4 become “L”, and the NMOS transistors 8 and 30 are turned off at substantially the same time as the time T1.
[0097]
As described above, when the input signal changes from “L” to “H” at time T1, the NMOS transistors 6, 8, and 30 are turned off regardless of the potential of the output terminal 1, and the PMOS transistor 5 is turned on. Since it is turned on, the potential of the output terminal 1 rises from the ground potential GND toward the potential Vdd. However, until the potential reaches the second threshold value Vdd / 3, both the inverters 11 and 12 determine that the potential of the output terminal 1 is “L”, and the output remains “H”. Therefore, the outputs of the NOR gates 13 and 31 both maintain “L”, and the PMOS transistors 7 and 29 remain off.
[0098]
When the PMOS transistor 5 is turned on, the potential of the output terminal 1 continues to rise. When the potential of the output terminal 1 becomes the second threshold value Vdd / 3 at time T2, the output of the inverter 12 is “H”. To “L”. As a result, since all inputs of the NOR gate 31 are “L”, the output is changed from “L” to “H”, and the third sub-control signal S3 is changed from “H” to “L”. As a result, the PMOS transistor 29 that has been turned off is turned on. However, until the potential of the output terminal 1 reaches the first threshold value 2Vdd / 3, the output of the inverter 11 remains “H”, and the first sub-control signal S1 also remains “H”. The PMOS transistor 7 is not turned on.
[0099]
At time T2, the output terminal 1 is connected to the potential Vdd via the two PMOS transistors 5 and 29, so that the current supplied to the output terminal 1 increases and the rate of increase in the potential of the output terminal 1 increases. . When the potential at the output terminal 1 reaches the first threshold value 2Vdd / 3 at time T3, the output of the inverter 11 changes from "H" to "L". As a result, since all inputs of the NOR gate 13 are “L”, the output is changed from “L” to “H”, and the first sub control signal S1 is changed from “H” to “L”. As a result, the PMOS transistor 7 which has been turned off is turned on.
[0100]
Since the outputs of the NAND gates 15 and 33 do not depend on the outputs of the inverters 11 and 12, both are “H” as long as the second main control signal M2 is “L”. Both S2 and the fourth sub-control signal S4 remain “L” regardless of the potential of the output terminal 1. Accordingly, the NMOS transistors 6, 8, and 30 remain off at time T2 and at time T3, and they do not affect the potential of the output terminal 1.
[0101]
By dividing the current addition time into two stages as described above, smoother slew rate control than that of the first embodiment can be realized.
[0102]
FIG. 15 is a diagram showing the operation of each part when the output signal changes from “H” to “L” at the output terminal 1. FIGS. 9A to 9J are respectively an input signal from the inside of the integrated circuit, a first main control signal M1 (the second main control signal M2 also exhibits the same waveform), an output of the inverter 11, and an inverter 12 Output, output of NAND gate 33, output of NAND gate 15, output of NOR gates 13 and 31, potential of output terminal 1, output current (current flowing from output terminal 1 to ground), transistors 5 to 8, 29, 30 Indicates the on / off state of.
[0103]
First, since the input signal is “H”, both the first main control signal M1 and the second main control signal M2 are “L”, and the NMOS transistor is the same as after the time T3 shown in FIG. 5, 7, 29 are turned on, and the PMOS transistors 6, 8, 30 are turned off. The potential of the output terminal 1 is Vdd. Both the inverters 11 and 12 output “L”.
[0104]
From this state, when the input signal changes from “H” to “L” at time T4, both the first main control signal M1 and the second main control signal M2 change from “L” to “H”. The NMOS transistor 6 is immediately turned on and the PMOS transistor 5 is turned off. Further, since the first main control signal M1 becomes “H”, the outputs of the NOR gates 13 and 31 change from “H” to “L” regardless of the outputs of the inverters 11 and 12, respectively. Both the sub-control signal S1 and the third sub-control signal S3 become “H”, and the PMOS transistors 7 and 29 are turned off at substantially the same time as time T4.
[0105]
As described above, when the input signal changes from “H” to “L” at time T4, the PMOS transistors 5, 7, and 29 are turned off regardless of the potential of the output terminal 1, and the NMOS transistor 6 is turned on. Since it is turned on, the potential of the output terminal 1 drops from the potential Vdd toward the ground potential GND. However, until the potential reaches the first threshold value 2Vdd / 3, the inverters 11 and 12 determine that the potential of the output terminal 1 is “H”, and the output remains “L”. Therefore, the outputs of the NAND gates 15 and 33 both maintain “H”, and the NMOS transistors 8 and 30 remain off.
[0106]
When the NMOS transistor 6 is turned on, the potential of the output terminal 1 continues to decrease. When the potential of the output terminal 1 becomes the first threshold value 2Vdd / 3 at time T5, the output of the inverter 11 is “L”. To “H”. As a result, all inputs of the NAND gate 33 become “H”, so that its output changes from “H” to “L”, and the fourth sub-control signal S4 changes from “L” to “H”. As a result, the NMOS transistor 30 that has been turned off is turned on. However, until the potential of the output terminal 1 reaches the second threshold value Vdd / 3, the output of the inverter 12 remains “L”, and the second sub-control signal S2 also remains “L”. The NMOS transistor 8 is not turned on.
[0107]
At time T5, the output terminal 1 is connected to the ground potential GND via two NMOS transistors 6 and 30, so that the current flowing out from the output terminal 1 increases and the rate of decrease in the potential of the output terminal 1 increases. When the potential of the output terminal 1 reaches the second threshold value Vdd / 3 at time T6, the output of the inverter 12 changes from “L” to “H”. As a result, all inputs of the NAND gate 15 become “H”, so that the output changes from “H” to “L”, and the second sub-control signal S2 changes from “L” to “H”. As a result, the NMOS transistor 8 that has been turned off is turned on.
[0108]
Since the outputs of the NOR gates 13 and 31 do not depend on the outputs of the inverters 11 and 12, and are “L” as long as the first main control signal M1 is “H”, the first sub-control signal S1 and The third sub control signal S3 remains “H” without depending on the potential of the output terminal 1. Accordingly, the PMOS transistors 5, 7, and 29 remain off at time T5 and at time T6, and they do not affect the potential of the output terminal 1.
[0109]
As described above, in this embodiment, the slew rate control smoother than that of the first embodiment can be realized by dividing the timing of adding the current into two stages.
[0110]
Of course, it is also possible to determine the logic of the output signal with different threshold values depending on whether the potential of the output terminal rises or falls. However, as in this embodiment, it is easier to determine the logic with the same threshold value (2Vdd / 3, Vdd / 3) when the potential of the output terminal rises and falls. There is a merit that
[0111]
By using this embodiment, a tristate output circuit can be configured as in Embodiments 4 to 6.
[0112]
【The invention's effect】
According to the output circuit of the present invention, after the first main transistor is turned on, the second sub-transistor is turned on so that positive feedback is applied to the output signal. The same applies to the second main transistor and the second sub-transistor. Therefore, it is not necessary to prepare transistors having different gate lengths in the output circuit for suppressing a sudden change in the output signal. Therefore, the degree of freedom in designing with the master slice method can be increased.
[0113]
According to the output circuit of the second aspect of the present invention, the first or second signal is output at a timing at which the potential change becomes gradual whether the output signal goes from the first potential to the second potential or vice versa. Since the sub-transistor is turned on, the potential change can be made closer to a straight line.
[0114]
According to the output circuit of the third aspect of the present invention, two different first and second threshold values can be realized.
[0115]
According to the output circuit according to the fourth aspect of the present invention, since the change of the output signal is determined by a circuit having hysteresis, noise tolerance can be increased.
[0116]
According to the output circuit of the present invention, positive feedback can be applied to the output signal with a simple configuration.
[0117]
According to the output circuit of the sixth aspect of the present invention, the effects of the first to fifth aspects can be obtained while functioning as a tri-state buffer.
[0118]
According to the output circuit of the seventh aspect of the present invention, the number of sub-transistors can be increased, and the potential change of the output signal can be made closer to a straight line.
[0119]
According to the output circuit of the eighth aspect of the present invention, the effect of the seventh aspect can be obtained without complicating the circuit configuration.
[0120]
According to the output circuit of the ninth aspect of the present invention, when the output signal transitions to the first potential due to the transition of the input signal, the main switching element is turned on first, and then the sub switching element is turned on. As described above, since the potential of the output signal goes to the first potential through a plurality of stages, generation of noise can be suppressed without abrupt change.
[0121]
According to the output circuit of the tenth aspect of the present invention, the initial change of the output signal, particularly the potential, can be suppressed, and the generation of noise can be further effectively suppressed.
[0122]
According to the output circuit of the eleventh aspect of the present invention, even if the output circuit is configured using transistors, it is not necessary to prepare transistors having different gate lengths in order to suppress an abrupt change in the output signal. . Therefore, the degree of freedom in designing with the master slice method can be increased.
[0123]
According to the output circuit of the twelfth aspect of the present invention, the potential of the output signal first starts to shift from the second potential toward the first potential due to the conduction of the main switching element, and in the middle of the predetermined threshold, Reach value. Since the sub-switching element is turned on only after the potential of the output signal reaches a predetermined threshold value, the sub-switching element can be turned on after the main switching element is turned on.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a basic configuration of an output circuit according to the present invention.
FIG. 2 is a circuit diagram showing a configuration of an output circuit according to the first embodiment of the present invention.
FIG. 3 is a diagram showing an operation of the output circuit according to the first embodiment of the present invention.
FIG. 4 is a diagram showing an operation of the output circuit according to the first embodiment of the present invention.
FIG. 5 is a circuit diagram showing a configuration of an output circuit according to a second embodiment of the present invention.
FIG. 6 is a diagram showing an operation of the output circuit according to the second embodiment of the present invention.
FIG. 7 is a diagram showing an operation of the output circuit according to the second embodiment of the present invention.
FIG. 8 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.
FIG. 9 is a graph showing the hysteresis characteristic of the hysteresis circuit.
FIG. 10 is a circuit diagram showing a configuration of an output circuit according to a fourth embodiment of the present invention.
FIG. 11 is a circuit diagram showing a configuration of an output circuit according to a fifth embodiment of the present invention.
FIG. 12 is a circuit diagram showing a configuration of an output circuit according to a sixth embodiment of the present invention.
FIG. 13 is a circuit diagram showing a configuration of an output circuit according to a seventh embodiment of the present invention.
FIG. 14 is a diagram showing an operation of the output circuit according to the seventh embodiment of the present invention.
FIG. 15 is a diagram showing an operation of the output circuit according to the seventh embodiment of the present invention.
FIG. 16 is a circuit diagram showing an example of a conventional output circuit.
FIG. 17 is a diagram showing the operation of a conventional output circuit.
[Explanation of symbols]
1 output terminal, 2, 201, 202 pre-buffer, 3, 301-302 main buffer, 4, 401-404 feedback circuit, 5, 7, 29 PMOS transistor, 6, 8, 30 NMOS transistor, 11, 12, 14, 16-19, 21 Inverter, 13, 22, 31 NOR gate, 15, 20, 33 NAND gate, 23 Hysteresis circuit.

Claims (12)

An output circuit comprising an input terminal to which an input signal in accordance with binary logic is given, and an output terminal for outputting an output signal that transitions in response to a logic transition of the input signal,
(a) (a-1) a first electrode to which a first potential corresponding to a first logic value which is one of the binary logics is applied, a second electrode connected to the output terminal, and a first main A first main transistor having a control electrode for receiving a control signal;
(a-2) a first electrode to which a second potential corresponding to a second logic value complementary to the first logic value of the binary logic is applied; a second electrode connected to the output terminal; A second main transistor having a control electrode for receiving a main control signal of
(a-3) a first sub-transistor having a first electrode to which the first potential is applied, a second electrode connected to the output terminal, and a control electrode for receiving a first sub-control signal;
(a-4) a second sub-transistor having a first electrode to which the second potential is applied, a second electrode connected to the output terminal, and a control electrode for receiving a second sub-control signal The main buffer,
(b) a pre-buffer that generates the first and second main control signals based on the input signal;
(c) (c-1) When the output signal reaches the first threshold value during the transition from the value closer to the second potential than the first threshold value toward the first potential. A first logic gate that outputs the first main control signal as the first sub-control signal;
(c-2) When the output signal reaches the second threshold value during the transition from the value closer to the first potential than the second threshold value toward the second potential, And a control circuit having a second logic gate that outputs the second main control signal as the second sub control signal. 2. The output circuit according to claim 1, wherein the first and second threshold values are close to the first and second potentials, respectively, with respect to an intermediate value between the first potential and the second potential. In the first main transistor, the first main control signal corresponds to the second logic value, and in the second main transistor, the second main control signal corresponds to the first logic value. In addition, when the first sub-control signal corresponds to the second logic value, the second sub-transistor corresponds to the first logic value of the second sub-transistor. When you do, each conducts,
The first logic gate is
(c-1-1) an inverter that inverts the output signal with the first threshold;
(c-1-2) When the output of the inverter of the first logic gate and the first main control signal both take the second logic value, the second logic value is changed to the first sub-control. Logic elements that output as signals,
The second logic gate is
(c-2-1) an inverter that inverts the output signal with the second threshold value;
(c-2-2) When the output of the inverter of the second logic gate and the second main control signal both take the first logic value, the first logic value is changed to the second sub-control. The output circuit according to claim 2, further comprising a logic element that outputs the signal. The first and second logic gates are configured such that the output signal is the first signal while the output signal transitions from a value closer to the second potential than the first threshold value toward the first potential. When the threshold value is reached, the second logic is used to change the output signal in the middle of the transition from the value closer to the first potential to the second potential than the second threshold value. Including a first hysteresis circuit that outputs the first logic when a second threshold value is reached;
The first logic gate outputs the second logic value as the first sub-control signal when both the output of the hysteresis circuit and the first main control signal take the second logic value. Further comprising an element,
The second logic gate outputs the first logic value as the second sub-control signal when both the output of the hysteresis circuit and the second main control signal take the first logic value. The output circuit according to claim 2, further comprising an element. The output circuit according to claim 1, wherein the first threshold value and the second threshold value are equal. The pre-buffer receives the input signal and the state control signal,
When the control signal is inactive, the logic based only on the input signal is output in common as the first and second main control signals,
When the control signal is inactive, both the first main control signal and the second main control signal are deactivated regardless of the input signal, and the first and second The output circuit according to claim 1, wherein any of the main transistors is turned off. The main buffer is
(a-5) a third sub-transistor having a first electrode to which the first potential is applied, a second electrode connected to the output terminal, and a control electrode for receiving a third sub-control signal;
(a-6) a fourth sub-transistor having a first electrode to which the second potential is applied, a second electrode connected to the output terminal, and a control electrode for receiving a fourth sub-control signal; Have
The control circuit is
(c-3) When the output signal reaches the third threshold value during the transition from the value closer to the second potential than the third threshold value toward the first potential, A third logic gate that outputs one main control signal as the third sub-control signal;
(c-4) When the output signal reaches the fourth threshold value during the transition from the value closer to the first potential than the fourth threshold value toward the second potential, The output circuit according to claim 1, further comprising a fourth logic gate that outputs two main control signals as the fourth sub control signal. 8. The output circuit according to claim 7, wherein the third threshold value is equal to the second threshold value, and the fourth threshold value is equal to the first threshold value. An output circuit comprising an input terminal to which an input signal in accordance with binary logic is given, and an output terminal for outputting an output signal that transitions in response to a logic transition of the input signal,
A first end to which a first potential corresponding to a first logic value of the binary logic is applied; and a second end connected to the output terminal; the first end and the second end of the first end A main switching element conducting / non-conducting between;
A sub-switching element having a first end to which the first potential is applied and a second end connected to the output terminal, wherein the sub-switching element is conductive / non-conductive between the first end and the second end of the first end; Further comprising
When the main switching element conducts from the state where both the main switching element and the sub switching element are non-conducting due to the transition of the input signal, the sub switching element is also conducted after the main switching element is conducted. Output circuit. The output circuit according to claim 9, wherein the main switching element has a smaller flowing current than the sub switching element. The output circuit according to claim 9, wherein the main switching element and the sub switching element are constituted by transistors. Due to the conduction of the main switching element, the potential of the output signal shifts in a direction from the second potential corresponding to the second logic value complementary to the first logic value of the binary logic to the first potential. ,
The output circuit according to claim 9, wherein the sub-switching element starts to conduct when the potential of the output signal reaches a predetermined threshold value due to the transition.

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