JPH1013206A - Output circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the degree of design freedom in the master slice system and to suppress noise by controlling a time change in an output signal. SOLUTION: A pre-buffer 2 receives an input signal from the inside of an integrated circuit, and a main buffer 3 receives an output of the pre-buffer 2 to provide an output of a signal to an output terminal 1 of the integrated circuit. A feedback circuit 4 detects a potential of the output terminal 1 and compares it with an output of the pre-buffer 2, to control the main buffer 3. Specifically, the level of the output terminal 1 is positively fed back to control a current flowing to (or flowing out of) the output terminal 1, depending on the steepness of the time change.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output circuit for controlling a change in an output signal in an output circuit of a semiconductor integrated circuit device.

[0002]

2. Description of the Related Art Generally, a large current is required for high-speed transmission on the output side of a semiconductor integrated circuit device (hereinafter, "integrated circuit"). However, a steep change in current causes noise, which causes malfunction of the integrated circuit and a system in which the integrated circuit is incorporated. In order to avoid this, a slew rate control that intentionally suppresses a time change of an output signal and suppresses generation of noise is performed.

FIG. 16 is a circuit diagram showing an example of a conventional output circuit for performing a slew rate control. The prebuffer 200 receives an input signal from inside the integrated circuit, and the main buffer 300 receives an output of the prebuffer 200 and provides an output signal to the output terminal 1.

[0004] The pre-buffer 2 has an inverter 41 for receiving an input signal, and inverters 39 and 40 for inverting the output of the inverter 41.

The main buffer 300 includes a PMOS transistor 35 and an NMOS transistor 36 each including a gate receiving the output of the inverter 39, a PMOS transistor 37 and an NMOS transistor 38 each including a gate receiving the output of the inverter 40, and transistors 35 and 36. , PMOS transistors 5 and 37 including a gate commonly connected to the drains of transistors
Including a gate commonly connected to the drain of the NMOS
The transistor 6 is provided. The drains of the transistors 5 and 6 are commonly connected to the output terminal 1, and the sources of the transistors 35 and 5 are all connected to the potential Vdd (logic "H").
, And the sources of the transistors 38 and 6 are both supplied with the ground potential GND (corresponding to logic "L").

However, the channel width of the transistors 5 and 6 is made larger than the channel width of the transistors 35 to 38. The NMOS transistor 36 and the PMOS transistor 37 are the same as the PMOS transistor 35 and the NMO
The gate length is longer than that of the S transistor 38.

Due to the difference in the gate length, the time required for the gate potential of the PMOS transistor 5 to change from "H" to "L" is extremely longer than the time required for the gate potential of the PMOS transistor 5 to change from "L" to "H". Become longer. Similarly, the time required for the gate potential of the NMOS transistor 6 to change from "L" to "H" becomes extremely longer than the time required for the gate potential to change from "H" to "L". As a result, all of the transistors 5 and 6 turn off quickly and turn on slowly.

FIG. 17 is a diagram showing the operation of each part of the output circuit shown in FIG. 16 when the output signal changes from "L" to "H". 14A to 14G show an input signal from inside the integrated circuit and an inverter 39, respectively.
(The output of the inverter 40 also has the same waveform), the gate potential of the PMOS transistor 5, the NMOS
The gate potential of the transistor 6, the potential of the output terminal 1, the output current (current flowing to the output terminal 1), the transistor 3
6, ON, OFF states of 6, 5, 38, 6, 35 and 37 are shown.

When the input signal changes from "L" to "H" at time T1, the outputs of inverters 39 and 40 change from "L" to "H" in response to this. PMOS
The transistor 37 and the NMOS transistor 38 are turned off and on, respectively. As a result, the NMOS transistor 6 is turned on. This is caused by the turning on of the transistor 38 having a short gate length, so that the operation is prompt.
That is, the NMOS transistor 6 is turned off substantially at time T1.

However, the turning on of the PMOS transistor 5 is caused by the turning on of the transistor 36 having a long gate length, so that its operation is slow. That is, at time T1, transistor 5 is not completely turned on, and at time T1
At time T2, which is later than the time T1, the NMOS transistor 6 is finally completely turned on. From the above, the output signal gradually changes over the entire changing time.

The generated noise increases as the derivative of the current that causes the noise increases. However, the output circuit has a fixed change time required to reach the maximum current according to the standard. . If the potential output from the output circuit changes abruptly, the current flowing at that time increases, so that the potential of the output terminal 1 desirably changes linearly.

In the prior art shown in FIG. 16, a desired slew rate is realized by asymmetrical change time required for turning on / off the transistors 5 and 6.

[0013]

In the prior art, the change is large at the initial stage (time T1 to T2) when the output signal changes, and conversely at the end of the change (after time T2), the change is very gentle. Become. In other words, it was not possible to suppress a large change in the output signal at the initial stage, and thus it was not possible to sufficiently suppress the generation of noise.

In a master slice type integrated circuit, all usable transistors need to be arranged and prepared in advance. In order to be able to design an output circuit with improved slew rate using conventional technology,
It is necessary to prepare a plurality of transistors having different gate lengths. However, the area occupied by the output circuit on the integrated circuit is limited, and the number of transistors having the standard gate length must be reduced in order to prepare transistors other than the standard gate length. Transistor 3 in FIG.
When standard gate length transistors are used for the transistors 5 and 38, it is necessary to provide transistors having gate lengths longer than the standard in order to form the transistors 36 and 37. As a result, there is a problem that the degree of freedom in design, which is an advantage of the master slice method, is significantly impaired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and provides a design circuit using a master slice system by providing an output circuit having an improved slew rate without changing the gate length of a transistor to be used. It is intended to increase the degree of freedom and control the time change of the output signal to suppress noise.

[0016]

Means for Solving the Problems Claim 1 of the present invention
Is an output circuit that includes an input terminal to which an input signal conforming to binary logic is supplied, and an output terminal that outputs an output signal that transitions in accordance with the transition of the logic of the input signal. And (a) (a-1) a first electrode to which a first potential corresponding to a first logical value which is one of the binary logics is provided;
A first main transistor having a second electrode connected to the output terminal, and a control electrode receiving a first main control signal; and (a-2) a first logical value complementary to the first logical value of the binary logic. A second main transistor having a first electrode provided with a second potential corresponding to a second logical value, a second electrode connected to the output terminal, and a control electrode receiving a second main control signal; (a
-3) a first sub-transistor having a first electrode to which the first potential is applied, a second electrode connected to the output terminal, and a control electrode receiving a first sub-control signal; 4) a main buffer having a first electrode to which the second potential is applied, a second electrode connected to the output terminal, and a second sub-transistor having a control electrode receiving a second sub-control signal. (B) a pre-buffer for generating the first and second main control signals based on the input signal; (c) (c-
1) when the output signal reaches the first threshold during a transition from a value closer to the second potential than the first threshold toward the first potential, A first logic gate that outputs a control signal as the first sub-control signal, and (c-2) a transition from a value closer to the first potential than a second threshold to the second potential. And a second logic gate for outputting the second main control signal as the second sub-control signal when the output signal reaches the second threshold value on the way.

According to a second aspect of the present invention,
2. The output circuit according to claim 1, wherein said first and second thresholds are respectively equal to said first and second potentials with respect to an intermediate value between said first potential and said second potential. Close to.

According to the third aspect of the present invention,
3. The output circuit according to claim 2, wherein said first main transistor is said second main control signal when said first main control signal corresponds to said second logical value. If the signal corresponds to the first logical value, the first
The sub-transistors of the first and second sub-transistors respectively correspond to the case where the first sub-control signal corresponds to the second logical value and the case where the second sub-control signal corresponds to the first logical value. Conduct. And the first logic gate comprises: (c-1-1) an inverter for inverting the output signal with the first threshold value; and (c-1-2) an inverter for the first logic gate. A logic element that outputs the second logical value as the first sub-control signal when both the output and the first main control signal take the second logical value. Further, the second logic gate outputs (c-2-1) the output signal,
An inverter that inverts with the second threshold, (c-2-
2) a logic that outputs the first logic value as the second sub-control signal when both the output of the inverter of the second logic gate and the second main control signal take the first logic value. Element.

According to a fourth aspect of the present invention,
3. The output circuit according to claim 2, wherein the first and second logic gates transition from a value of the output signal closer to the second potential than the first threshold to the first potential. When the output signal reaches the first threshold during the operation, the second logic is changed from a value closer to the first potential than the second threshold to the second potential. A hysteresis circuit sharing the first logic when the output signal reaches the second threshold during the transition toward the second threshold is included. The first logic gate outputs the second logic value as the first sub control signal when both the output of the hysteresis circuit and the first main control signal take the second logic value. The logic element further includes: Also, the second logic gate outputs the first logic value as the second sub-control signal when both the output of the hysteresis circuit and the second main control signal take the first logic value. The logic element further includes:

According to a fifth aspect of the present invention, there is provided:
2. The output circuit according to claim 1, wherein said first threshold value and said second threshold value are equal.

According to a sixth aspect of the present invention, there is provided:
6. The output circuit according to claim 1, wherein the pre-buffer receives the input signal and a state control signal, and the input signal when the control signal is inactive. And outputs the first and second main control signals in common as logic based on only the first main control signal and the second main control signal regardless of the input signal when the control signal is inactive. The second main control signal is deactivated, and both the first and second main transistors are turned off.

According to a seventh aspect of the present invention,
2. The output circuit according to claim 1, wherein the main buffer comprises: (a-5) a first electrode to which the first potential is applied, a second electrode connected to the output terminal, and a third sub-control signal. A third sub-transistor having a control electrode receiving
6) The semiconductor device further includes a fourth sub-transistor having a first electrode to which the second potential is applied, a second electrode connected to the output terminal, and a control electrode receiving a fourth sub-control signal. The control circuit may further include: (c-3) when the output signal reaches the third threshold during a transition from a value closer to the second potential than the third threshold toward the first potential. A third logic gate that outputs the first main control signal as the third sub-control signal,
When the output signal reaches the fourth threshold during a transition from a value closer to the first potential than the threshold to the second potential, the second main control signal is set to the second threshold. A fourth logic gate that outputs a fourth sub-control signal.

According to the eighth aspect of the present invention,
8. The output circuit according to claim 7, wherein said third threshold is equal to said second threshold, and said fourth threshold is equal to said first threshold.

According to a ninth aspect of the present invention, there is provided:
An output circuit including an input terminal to which an input signal conforming to binary logic is provided, and an output terminal that outputs an output signal that changes in accordance with a transition of the logic of the input signal. And
It has a first end to which a first potential corresponding to a first logical value of the binary logic is applied, and a second end connected to the output terminal. A main switching element that conducts / non-conducts between them, a first end to which the first potential is applied, and a second end connected to the output terminal, and the first end and the second end of itself. And a sub-switching element for conducting / non-conducting between them. Here, when the main switching element becomes conductive from a state where both the main switching element and the sub-switching element are non-conductive due to the transition of the input signal, the sub-switching element is turned on after the main switching element becomes conductive. Also conducts.

According to a tenth aspect of the present invention, in the output circuit according to the ninth aspect, a current flowing through the main switching element is smaller than that of the sub-switching element.

According to an eleventh aspect of the present invention, there is provided the output circuit according to the ninth aspect, wherein the main switching element and the sub switching element are constituted by transistors.

According to a twelfth aspect of the present invention, there is provided the output circuit according to the ninth aspect, wherein the electric potential of the output signal is increased by the conduction of the main switching element.
A transition is made from a second potential corresponding to a second logic value complementary to the first logic value of the value logic to the first potential, and the transition causes the potential of the output signal to reach a predetermined threshold value Then, the sub-switching element starts to conduct.

In the present application, the "threshold" does not mean a threshold of a gate voltage for controlling ON / OFF of a transistor but a logical threshold for discriminating "L" / "H".

[0029]

BEST MODE FOR CARRYING OUT THE INVENTION

Basic idea. To achieve the ideal slew rate,
In order to moderate the initial change of the output signal, first drive the main drive means to change the output signal, and when the output signal changes to some extent, further change the output signal in the same direction with the sub drive means What is necessary is just to drive so that it may be performed.

FIG. 1 is a circuit diagram showing a basic configuration of an output circuit according to the present invention. The prebuffer 2 receives an input signal from inside the integrated circuit, and the main buffer 3 receives an output of the prebuffer 2 and outputs a signal to an output terminal 1 of the integrated circuit.

The feedback circuit 4 detects the potential of the output terminal 1 and
The output of pre-buffer 2 is compared with that of main buffer 3
Control. Specifically, by positively feeding back the potential of the output terminal 1, it is possible to control the current flowing into (or flowing out of) the output terminal 1 in accordance with the speed of the time change.

Embodiment 1 FIG. 2 is a circuit diagram showing a configuration of the output circuit according to the first embodiment of the present invention. The pre-buffer 201 is composed of inverters 9 and 10 each receiving an input signal inside the integrated circuit. Feedback circuit 401
Inputs the potential of the output terminal 1 and outputs the first and second
Inverters 1 and 1 that invert and output the inverted values with the threshold value of
2, a two-input NOR gate 13 receiving the output of the inverter 11 and the output of the inverter 9, an inverter 14 inverting the output of the NOR gate 13, a two-input NAND gate 15 receiving the output of the inverter 12 and the output of the inverter 10. , And an inverter 16 for inverting the output of the NAND gate 15.

The main buffer 301 has a source connected to the potential Vd.
d, the drain is connected to the output terminal 1, the output of the inverter 9 is input to the gate of the PMOS transistor 5, the source is supplied with the ground potential GND, the drain is connected to the output terminal 1, An NMOS transistor 6 whose output is input to the gate, a potential Vdd is applied to the source, the drain is connected to the output terminal 1, and the output of the inverter 14 is input to the gate.
The ground potential GND is applied to the source of the S transistor 7 and the drain is connected to the output terminal 1.
Is constituted by an NMOS transistor 8 whose gate is input to the output.

The first and second thresholds are each 2 Vd
d / 3 and Vdd / 3 are set.

Transistors 5 and 6 are referred to in the previous section "Basic idea".
Corresponds to the main driving means described in
Reference numeral 8 corresponds to the sub-driving means. Transistors 7, 8
Have wider channel widths than the transistors 5 and 6, respectively.

The output of the inverter 9 functions as a first main control signal M1 for controlling the conduction of the transistor 5,
The output of the inverter 10 functions as a second main control signal M2 for controlling the conduction of the transistor 6. The output of the inverter 14 functions as a first sub-control signal S1 for controlling conduction of the transistor 7, and the output of the inverter 10 functions as a second sub-control signal S2 for controlling conduction of the transistor 6.

FIG. 3 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from "L" to "H". 3A to 3H respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
Output of NAND gate 15, output of inverter 11, N
It shows the output of the OR gate 13, the potential of the output terminal 1, the output current (current flowing to the output terminal 1), and the on / off states of the transistors 5 to 8.

First, since the input signal is "L", the first main control signal M1 is "H", and the PMOS transistor 5 is off. The NOR gate 13 receives the first main control signal M1 at one of its input terminals.
“L” is output irrespective of the output value of the inverter 11. Therefore, the first sub-control signal S1 is "H" and P
MOS transistor 7 is also off.

On the other hand, the second main control signal M2 is "H".
And the NMOS transistor 6 is in the ON state. P
Since MOS transistors 5 and 7 are off, NM
Output terminal 1 regardless of ON / OFF of OS transistor 8
Is at the ground potential GND. Therefore, as for each input of the NAND gate 15, since the second main control signal M2 is "H" and the output of the inverter 12 which inverts the potential of the output terminal 1 is "H", the output of the NAND gate 15 is "L". Become. Therefore, the second sub-control signal S2 obtained by inverting this signal by the inverter 16 becomes "H", and the NMOS transistor 8 is also in the ON state.

When the input signal from the inside of the integrated circuit changes from "L" to "H" at time T1 from such a state, both the first main control signal M1 and the second main control signal M2 are changed. "H" changes to "L" and immediately P
The MOS transistor 5 turns on and the NMOS transistor 6 turns off. When the second main control signal M2 is "L"
Irrespective of the output of the inverter 12,
Since the output of the AND gate 15 changes from "L" to "H", the second sub-control signal S2 becomes "L" and the NMOS transistor 8 is turned off at substantially the same time as the time T1.

As described above, when the input signal changes from "L" to "H" at time T1, the NMOS transistors 6 and 8 are turned off regardless of the potential of the output terminal 1, and the PMOS transistor 5 is turned off. Is turned on, the potential of the output terminal 1 rises from the ground potential GND toward the potential Vdd. However, the potential is equal to the first threshold value 2Vdd.
Until // 3, the inverter 11 determines that the potential of the output terminal 1 is "L", and the output remains at "H". Therefore, the output of the NOR gate 13 maintains “L” and the PMO
The S transistor 7 remains off.

Since the PMOS transistor 5 is turned on, the potential of the output terminal 1 keeps rising, and at time T2, the potential of the output terminal 1 becomes the first threshold value 2Vdd / 3.
Then, the output of the inverter 11 changes from “H” to “L”. As a result, the inputs of the NOR gate 13 all become "L", so that the output changes from "L" to "H", and the first sub-control signal S1 changes from "H" to "L". As a result, the PMOS transistor 7 that has been turned off is turned on.

As a result, at time T2, the potential Vd is applied to the output terminal 1 via the two PMOS transistors 5 and 7.
As a result, the current supplied to the output terminal 1 increases, and the rate of increase in the potential of the output terminal 1 increases. NAN
Since the output of the D gate 15 is "H" as long as the second main control signal M2 is "L" without depending on the output of the inverter 12, the second sub control signal S2 is output from the output terminal 1. It remains at "L" irrespective of the potential. Therefore, N
The MOS transistors 6 and 8 remain off even at time T2, and do not affect the potential of the output terminal 1.

FIG. 4 is a diagram showing the operation of each unit when the output signal at the output terminal 1 changes from "H" to "L". 3A to 3H respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
Output of NAND gate 15, output of inverter 12, N
The output of the OR gate 13, the potential of the output terminal 1, the output current (current flowing from the output terminal 1 to the ground), and the on / off states of the transistors 5 to 8 are shown.

First, since the input signal is "H", both the first main control signal M1 and the second main control signal M2 are "L", similar to the time after the time T2 shown in FIG. , NMOS transistors 5 and 7 are on, and PMOS transistors 6 and 8 are off. The potential of the output terminal 1 is Vdd. Each of the inverters 11 and 12 outputs “L”.

When the input signal changes from "H" to "L" at time T3 from such a state, both the first main control signal M1 and the second main control signal M2 become "L".
Changes from “H” to “H” and the NMOS transistor 6
Turns on, and the PMOS transistor 5 turns off. Further, when the first main control signal M1 becomes "H", the output of the NOR gate 13 changes from "H" to "L" regardless of the output of the inverter 11, so that the first sub-control signal S1 Becomes “H”, and at about the same time as time T3, PM
The OS transistor 7 turns off.

As described above, when the input signal changes from "H" to "L" at time T3, the PMOS transistors 5 and 7 are turned off and the NMOS transistor 6 is turned off regardless of the potential of the output terminal 1. Is turned on, the potential of the output terminal 1 falls from the potential Vdd toward the ground potential GND. However, the potential is equal to the second threshold value Vdd /
Until the voltage reaches 3, the inverter 12 determines that the potential of the output terminal 1 is "H", and the output remains at "L". Therefore, the output of NAND gate 15 maintains "H" and NMO
The S transistor 8 remains off.

Since the NMOS transistor 6 is on, the potential of the output terminal 1 continues to decrease. When the potential of the output terminal 1 reaches the second threshold value Vdd / 3 at time T4, the output of the inverter 12 becomes low. The state changes from "L" to "H". As a result, the inputs of the NAND gate 15 all become "H", so that the output changes from "H" to "L", and the second sub-control signal S2 changes from "L" to "H". As a result, the NMOS transistor 8 that has been turned off is turned on.

As a result, at time T4, the output terminal 1 is connected to the ground potential GND via the two NMOS transistors 6 and 8, so that the current flowing from the output terminal 1 increases, and the potential of the output terminal 1 The descending rate increases. N
Since the output of the OR gate 13 is "L" as long as the first main control signal M1 is "H" without depending on the output of the inverter 11, the first sub-control signal S1 is It remains at "H" irrespective of the potential. Therefore, P
MOS transistors 5 and 7 remain off even at time T4, and do not affect the potential of output terminal 1.

The configuration of the main buffer 3 is divided into two stages, namely, transistors 5 and 6 as main driving means and transistors 7 and 8 as sub driving means operated by applying positive feedback. The current flowing into (or flowing out of) the output terminal 1 can be controlled by controlling with a main control signal and a sub-control signal delayed from the main control signal.

In particular, by setting the channel widths of the transistors 5 and 6 to be narrower than those of the transistors 7 and 8, the former has a smaller current driving capability. Accordingly, it is possible to reduce a potential change particularly at the time of rising and falling of the output signal.

Further, by designing the threshold values of the inverters 11 and 12 for detecting the potential of the output terminal 1 to be different from each other, positive feedback can be applied at the final stage when the potential of the output terminal 1 changes. Therefore, the rate of change of the potential at the time when the change in the potential of the output terminal 1 becomes gentle can be increased, and the change in the current at the output terminal 1 can be made closer to a linear shape during the changing period, thereby suppressing noise. Can be.

Further, in terms of layout, there is no need to use transistors having channel lengths different from those of the other transistors such as the transistors 36 and 37 in the prior art, and all the standard gate lengths are provided on the master in the master slice type integrated circuit. Need only be arranged. Thus, the degree of freedom in circuit design of the output circuit can be improved.

Embodiment 2 FIG. 5 is a circuit diagram showing a configuration of an output circuit according to Embodiment 2 of the present invention. Compared with the output circuit shown in the first embodiment, the feedback circuit 401
Is replaced with a feedback circuit 402.

The feedback circuit 402 and the inverters 19 and 21 for inverting the first main control signal M1 and the second main control signal M2, respectively, are both inverted with the same threshold value, for example, Vdd / 2 and output. Inverter 17,
18 and a two-input NAND which receives the outputs of inverters 18 and 19 and outputs a first sub-control signal S1
Gate 20 and a two-input NOR gate 2 receiving outputs of inverters 18 and 21 and outputting a second sub-control signal S2
And 2. The input terminal of the inverter 17 is connected to the output terminal 1.

The feedback circuit 402 has a configuration in which the first threshold value and the second threshold value in the feedback circuit 401 are equal. That is, the series circuit of the NOR gate 13 and the inverter 14 in the feedback circuit 401
Inverters 18 and 19 and NAND gate 2
It is logically equivalently replaced by 0. Similarly, the series circuit of the NAND gate 15 and the inverter 16 in the feedback circuit 401 is logically equivalently replaced by the inverters 18 and 21 and the NOR gate 22 in the feedback circuit 402. The inverters 11 and 12 in the feedback circuit 401 are both logically equivalently replaced by the inverter 17 in the feedback circuit 402.

When the feedback circuits 401 and 402 are compared with each other, there is no difference in that each of them has one NOR gate and one NAND gate and four inverters. However, it is more necessary to form logic elements having the same threshold value as the inverters 17 and 18 than to form logic elements having different threshold values such as the inverters 11 and 12. Layout area can be reduced.

For example, in order to form a logic element having a threshold value of 2 Vdd / 3 like the inverter 11 shown in the first embodiment, the ratio of the channel width of the PMOS transistor to the channel width of the NMOS transistor is required. It needs to be about 4 to 8. On the other hand, as in inverters 17 and 18 shown in the second embodiment, the threshold value is Vd.
In order to form a logic element of d / 2, it is sufficient to make the above ratio approximately 2. That is, the inverter 17 has an advantage that the area occupied by the PMOS transistor can be suppressed more than the inverter 11.

FIG. 6 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from "L" to "H". 3A to 3H respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
The output of the inverter 18, the first sub-control signal S1, the second
, The output current (current flowing to the output terminal 1), and the on / off states of the transistors 5 to 8.

First, since the input signal is "L", the first main control signal M1 is "H" and the PMOS transistor 5 is in the off state. The NAND gate 20 has one of its input terminals to which "L" which is an inverted version of the first main control signal M1 is added as an output of the inverter 19, so that the first sub-control signal S is independent of the output value of the inverter 18.
"H" is output as "1". As a result, the PMOS transistor 7 is also off.

On the other hand, the second main control signal M2 is "H".
And the NMOS transistor 6 is in the ON state. P
Since MOS transistors 5 and 7 are off, NM
Output terminal 1 regardless of ON / OFF of OS transistor 8
Is at the ground potential GND. The respective inputs of the NOR gate 22 are inverted by the inverter 21 to output the inversion of the second main control signal M2 and output "L", and the output of the inverter 18 inverts the logic of the potential of the output terminal 2 twice (accordingly. , The same logic as the output terminal) is "L", so that the NOR gate 22 outputs "H" as the second sub-control signal S2,
The S transistor 8 is also on.

When the input signal from the inside of the integrated circuit changes from "L" to "H" at time T1 from such a state, both of the first main control signal M1 and the second main control signal M2 are changed. "H" changes to "L" and immediately P
The MOS transistor 5 turns on and the NMOS transistor 6 turns off. When the second main control signal M2 is "L"
, The second sub-control signal S2 becomes "L" regardless of the output of the inverter 18, and the NMOS transistor 8 is turned off at substantially the same time as the time T1.

As described above, when the input signal changes from "L" to "H" at time T1, the NMOS transistors 6 and 8 are turned off and the PMOS transistor 5 is turned on regardless of the potential of the output terminal 1. Is turned on, the potential of the output terminal 1 rises from the ground potential GND toward the potential Vdd. However, the inverter 17 keeps the potential of the output terminal 1 at “L” until the potential reaches the threshold value Vdd / 2.
And the output of the inverter 18 remains at "L". Therefore, the first sub control signal S1 maintains “H”,
PMOS transistor 7 remains off.

Since the PMOS transistor 5 is on, the potential of the output terminal 1 continues to rise. When the potential of the output terminal 1 reaches the threshold value Vdd / 2 at time T2, the output of the inverter 18 becomes "L". To "H". As a result, the inputs of the NAND gate 20 are all "H".
Therefore, the first sub-control signal S1 changes from “H” to “L”. As a result, the PMOS transistor 7 that has been turned off is turned on.

As a result, at time T2, the potential Vd is applied to the output terminal 1 via the two PMOS transistors 5 and 7.
As a result, the current supplied to the output terminal 1 increases, and the rate of increase in the potential of the output terminal 1 increases. As long as the second main control signal M2 is at "H", the second sub-control signal S2 remains at "L" regardless of the potential of the output terminal 1. Therefore, the NMOS transistors 6 and 8 remain off even at the time T2, and they do not affect the potential of the output terminal 1.

FIG. 7 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from "H" to "L". 3A to 3H respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
The output of the inverter 18, the first sub-control signal S1, the second
Sub-control signal S2, the potential of the output terminal 1, the output current (current flowing from the output terminal 1 to the ground),
8 shows an on / off state.

First, since the input signal is at "H", both the first main control signal M1 and the second main control signal M2 are at "L", similar to the time after time T2 shown in FIG. , NMOS transistors 5 and 7 are on, and PMOS transistors 6 and 8 are off. The potential of the output terminal 1 is Vdd. The inverter 18 outputs "H".

When the input signal changes from "H" to "L" at time T3 from such a state, both the first main control signal M1 and the second main control signal M2 become "L".
Changes from “H” to “H” and the NMOS transistor 6
Turns on, and the PMOS transistor 5 turns off. When the first main control signal M1 becomes “H”, the first sub-control signal S1 becomes independent of the output of the inverter 18.
Becomes "H", and the PMOS transistor 7 is turned off at substantially the same time as the time T3.

As described above, when the input signal changes from “H” to “L” at time T3, the PMOS transistors 5 and 7 are turned off and the NMOS transistor 6 is turned off regardless of the potential of the output terminal 1. Is turned on, the potential of the output terminal 1 falls from the potential Vdd toward the ground potential GND. However, the inverter 17 keeps the potential of the output terminal 1 at “H” until the potential reaches the threshold value Vdd / 2.
And the output of the inverter 18 remains at "H". Therefore, the second sub control signal S2 maintains "L",
The NMOS transistor 8 remains off.

Since the NMOS transistor 6 is on, the potential of the output terminal 1 continues to decrease. When the potential of the output terminal 1 reaches the threshold value Vdd / 2 at time T4, the output of the inverter 18 becomes "H". To "L". As a result, the inputs of the NOR gate 22 all become "L", and the second sub-control signal S2 changes from "L" to "H".
Changes to As a result, the NMO that was off until then
The S transistor 8 turns on.

As a result, at time T4, the output terminal 1 is connected to the ground potential GND via the two NMOS transistors 6 and 8, so that the current flowing out of the output terminal 1 increases, and the potential of the output terminal 1 decreases. The descending rate increases. Regardless of the output of the inverter 18, the first sub control signal S1 remains "H" as long as the first main control signal M1 is "H". Therefore, the PMOS transistors 5 and 7 remain off even at the time T4, and they do not affect the potential of the output terminal 1.

With the above circuit configuration,
Almost the same effects as in the first embodiment can be obtained, and the required layout area can be reduced.

Embodiment 3 In the first and second embodiments, the potential of the output terminal 1 is
12 and 17. Therefore, potential fluctuations of the output terminal 1 near these thresholds are reflected on these outputs, and there is a possibility that a malfunction may occur when noise occurs at the output terminal 1. Therefore, in the third embodiment, a circuit having hysteresis (hereinafter, referred to as a “hysteresis circuit”) is used as an element for detecting the potential of the output terminal 1 instead of an inverter having a single threshold value, thereby reducing noise immunity. Disclose the technology that strengthens.

FIG. 8 is a circuit diagram showing a configuration of an output circuit according to the third embodiment of the present invention. Compared with the output circuit shown in the first embodiment, the feedback circuit 401
3 is replaced.

The feedback circuit 403 has a configuration in which the inverters 11 and 12 of the feedback circuit 401 are replaced with a hysteresis circuit 23. The hysteresis circuit 23 is connected to the output terminal 1
, A first output terminal connected to one of the input terminals of the NOR gate 13, and a second output terminal connected to one of the input terminals of the NAND gate 15.

FIG. 9 is a graph showing the hysteresis of the hysteresis circuit 23. The potential of the output terminal 1 is “L”
When the threshold value changes from "H" to "H", the higher threshold value Vth2 is used. Conversely, when changing from "H" to "L", the lower threshold value Vth1 is used. Then, based on these threshold values, the hysteresis circuit 23 inverts the output signal and outputs the inverted signal to the first and second output terminals.

In the following description of the operation, the case where the same output is applied to both the first and second output terminals is shown for simplicity.
The output signal is inverted and output at the second output terminal, and the threshold value Vth3 (≠ Vth1), Vth4 (>
The hysteresis circuit 23 may be configured to invert the output signal with Vth3) and output the inverted signal.

When the hysteresis circuit 23 shown in FIG. 9 is used, the main buffer 301 operates in the same manner as in the first embodiment. In the first embodiment, the first threshold value corresponds to Vth2, the second threshold value corresponds to Vth1, and when the first main control signal M1 is "H", the state of the output signal is changed. Regardless of the state of the output signal, the first sub-control signal S1 is also "H" and the second main control signal M2 is "L" regardless of the state of the output signal.
Is also “L”, and the output of the hysteresis circuit 23 is set to NOR.
This is because the logic values of the first sub-control signal S1 and the second sub-control signal S2 are not different from those of the first embodiment even if the gate 13 and the NAND gate 15 receive the signal in common.

Therefore, according to the third embodiment, the effect of the first embodiment can be obtained while improving the noise resistance.

Embodiment 4 Although the output circuits described in Embodiments 1 to 3 output an output signal which changes according to a transition of an input signal, the present invention is applicable to a case where a signal for controlling an output circuit is also input to control an output signal. Is applicable. Hereinafter, a case where the present invention is applied to a tri-state output circuit will be described as an example.

FIG. 10 is a circuit diagram showing a configuration of an output circuit according to the fourth embodiment of the present invention. Compared with the output circuit described in the first embodiment, the output circuit has a configuration in which the pre-buffer 201 is replaced with a pre-buffer 202.

Prebuffer 202 receives an inverter 24 for receiving a control signal for controlling the operation state of the output circuit, an inverter 25 for receiving an input signal, a NAND gate 28 for receiving the outputs of inverters 24 and 25, and inverts an output of NAND gate 28. Inverter 10 and inverter 2 for output
4, the inverter 26 inverting the output of the inverter 4, the inverter 25,
NOR gate 27, NOR gate 2 receiving output of 26
7 comprises an inverter 9 for inverting the output.

When the control signal is "L", the outputs of the inverters 24 and 26 become "H" and "L", respectively.
Each of the AND gate 28 and the NOR gate 27 functions as an inverter. On the other hand, since the input signal is once inverted by the inverter 25, each of the inverters 9 and 10 outputs a value obtained by inverting the input signal. That is, when the control signal is “L”, the same function as the pre-buffer 201 is performed.

When the control signal is "H", the outputs of the inverters 24 and 26 become "L" and "H", respectively.
The OR gate 27 and the NAND gate 28 are “L”,
"H" is output. Therefore, the first main control signal M1,
The second main control signal M2 outputs "H" and "L", respectively.

Since the first main control signal M1 and the second main control signal M2 are "H" and "L", respectively, the outputs of the NOR gate 13 and the NAND gate 15 change to the logic state of the output terminal 1 respectively. Regardless, "L",
It becomes "H". Therefore, the first sub-control signal S1 and the second sub-control signal S2 become "H" and "L", respectively. As a result, all the transistors 5 to 8 of the main buffer 3
Turns off. That is, the output circuit gives the output terminal 1 a high impedance state.

As described above, by replacing the pre-buffer 201 shown in the first embodiment with the pre-buffer 202, an output circuit whose operation is changed by a control signal, such as a tri-state output circuit, can be used. Apply the invention,
The effect of the first embodiment can also be obtained.

Embodiment 5 FIG. 11 is a circuit diagram showing a configuration of an output circuit according to Embodiment 5 of the present invention. Compared with the output circuit described in the second embodiment, the output circuit has a configuration in which pre-buffer 201 is replaced with pre-buffer 202. Therefore, the output circuit described in this embodiment is a tri-state output circuit, and the effects of the second embodiment can be obtained.

Embodiment 6 FIG. 12 is a circuit diagram showing a configuration of an output circuit according to Embodiment 6 of the present invention. Compared with the output circuit described in the third embodiment, the output circuit has a configuration in which pre-buffer 201 is replaced with pre-buffer 202. Therefore, the output circuit described in this embodiment is a tri-state output circuit, and the effects of the third embodiment can be obtained.

Embodiment 7 FIG. 13 is a circuit diagram showing a configuration of an output circuit according to Embodiment 7 of the present invention. Compared with the output circuit shown in the first embodiment, the feedback circuit 40
1 is replaced with a feedback circuit 404, and the main buffer 301 is replaced with a main buffer 302, respectively.

The feedback circuit 404 is different from the configuration of the feedback circuit 401 in that the two-input NOR gate 31 that receives the output of the inverter 12 and the first main control signal M1 inverts the output of the NOR gate 31, and the third An inverter 32 that outputs a control signal S3; a NAND gate 33 that receives an output of the inverter 11 and a second main control signal M2;
The output of the D gate 33 is inverted and the fourth sub-control signal S4
Is output to the inverter 34.

The main buffer 302 is the main buffer 3
01, the PMOS transistor 29 and the NMO
It has a configuration in which an S transistor 30 is added. P
The MOS transistor 29 has a gate receiving the third sub-control signal S3, a source supplied with the potential Vdd, and a drain connected to the output terminal 1. The NMOS transistor 30 has a gate supplied with the fourth sub-control signal S4, a source supplied with the ground potential GND, and a drain connected to the output terminal 1.

The transistors 29 and 30 have a larger channel width than the transistors 5 and 6 and the transistors 7 and 8
The channel width is set smaller than the channel width.

FIG. 14 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from "L" to "H". FIGS. 3A to 3J respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
Output of inverter 11, output of inverter 12, NOR
Output of gate 31, output of NOR gate 13, NAND
The potential of the output terminal 1 of the gates 15 and 33, the output current (current flowing to the output terminal 1), the transistors 5 to 8,
29 shows the on / off state of 29 and 30.

First, since the input signal is "L", the first main control signal M1 is "H", and the PMOS transistor 5 is off. Each of the NOR gates 13 and 31 has a first main control signal M1 at one of its input terminals.
Is added, "L" is output regardless of the output values of the inverters 11 and 12. Therefore, the first sub control signal S1
And the third sub-control signal S3 is both "H",
The PMOS transistors 7 and 29 are also off.

On the other hand, the second main control signal M2 is "H".
And the NMOS transistor 6 is in the ON state. P
Since the MOS transistors 5, 7, and 29 are off, the potential of the output terminal 1 is at the ground potential GND regardless of whether the NMOS transistors 8, 30 are on or off. Therefore, as for each input of the NAND gate 15, since the second main control signal M2 is "H" and the output of the inverter 12 which is the inverted potential of the output terminal 1 is "H", the output of the NAND gate 15 is "L". Become. Therefore, the second sub-control signal S2 obtained by inverting this signal by the inverter 16 is "H".
And the NMOS transistor 8 is also in the ON state. In addition, since the second main control signal M2 is "H" and the output of the inverter 11 whose output terminal 1 is inverted is "H", the output of the NAND gate 33 is also "L". Become. Therefore, the fourth sub-control signal S4 obtained by inverting this signal by the inverter 34 is "H".
And the NMOS transistor 30 is also in the ON state.

When the input signal from the inside of the integrated circuit changes from "L" to "H" at time T1 from such a state, both the first main control signal M1 and the second main control signal M2 are changed. "H" changes to "L" and immediately P
The MOS transistor 5 turns on and the NMOS transistor 6 turns off. When the second main control signal M2 is "L"
, The outputs of the NAND gates 15 and 33 change from "L" to "H" regardless of the outputs of the inverters 11 and 12, so that the second sub-control signal S2 and the fourth sub-control signal S4 Becomes "L", and the NMOS transistors 8 and 30 are turned off at substantially the same time as the time T1.

As described above, when the input signal changes from "L" to "H" at time T1, the NMOS transistors 6, 8, 3 regardless of the potential of the output terminal 1.
0 turns off and the PMOS transistor 5 turns on.
The potential of the output terminal 1 increases from the ground potential GND toward the potential Vdd. However, the potential is equal to the second threshold V
Until dd / 3, both of the inverters 11 and 12 determine that the potential of the output terminal 1 is "L", and the output remains "H". Therefore, the outputs of the NOR gates 13 and 31 both maintain “L”, and the PMOS transistors 7 and 29 remain off.

Since the PMOS transistor 5 is turned on, the potential of the output terminal 1 keeps increasing. When the potential of the output terminal 1 reaches the second threshold value Vdd / 3 at time T2, the output of the inverter 12 becomes low. The state changes from “H” to “L”. As a result, the inputs of the NOR gate 31 all become "L", so that the output changes from "L" to "H", and the third sub-control signal S3 changes from "H" to "L". As a result, the PMOS transistor 29 which has been turned off is turned on. However, output terminal 1
Until the potential of the inverter 11 reaches the first threshold value 2Vdd / 3, the output of the inverter 11 remains at "H", the first sub-control signal S1 also remains at "H", and the PMOS transistor 7 is turned on. do not do.

At time T2, the output terminal 1 has a PMOS
Since the transistor is connected to the potential Vdd via the two transistors 5 and 29, the current supplied to the output terminal 1 increases, and the rate of increase in the potential of the output terminal 1 increases. And time T3
, The potential of the output terminal 1 becomes the first threshold value 2Vdd /
3, the output of the inverter 11 changes from "H" to "L".
Turn to. As a result, the inputs of the NOR gate 13 all become "L", so that the output changes from "L" to "H", and the first sub-control signal S1 changes from "H" to "L". As a result, the PMOS transistor 7 that has been turned off is turned on.

The outputs of the NAND gates 15 and 33 are both "H" as long as the second main control signal M2 is "L" without depending on the outputs of the inverters 11 and 12, so that the second Sub-control signal S2 and fourth sub-control signal S
4 remain “L” irrespective of the potential of the output terminal 1. Therefore, the NMOS transistors 6, 8, 30
Remains off even at time T2 or at time T3, and these do not affect the potential of the output terminal 1.

By dividing the time for adding the current into two stages, smoother slew rate control than in the first embodiment can be realized.

FIG. 15 is a diagram showing the operation of each part when the output signal at the output terminal 1 changes from "H" to "L". FIGS. 3A to 3J respectively show an input signal from inside the integrated circuit and a first main control signal M1.
(The second main control signal M2 also has the same waveform)
Output of inverter 11, output of inverter 12, NAN
Output of D gate 33, output of NAND gate 15, NO
It shows the outputs of the R gates 13 and 31, the potential of the output terminal 1, the output current (current flowing from the output terminal 1 to the ground), and the on / off states of the transistors 5 to 8, 29, and 30.

First, since the input signal is "H", both the first main control signal M1 and the second main control signal M2 are "L", similar to the time after time T3 shown in FIG. , NMOS transistors 5, 7, 29 are turned on, and PM
The OS transistors 6, 8, and 30 are off. The potential of the output terminal 1 is Vdd. Inverter 11,1
2 output “L”.

In this state, when the input signal changes from “H” to “L” at time T4, both the first main control signal M1 and the second main control signal M2 become “L”.
Changes from “H” to “H” and the NMOS transistor 6
Turns on, and the PMOS transistor 5 turns off. Also, when the first main control signal M1 becomes “H”, the NOR gate 1 is turned on regardless of the outputs of the inverters 11 and 12.
Since the outputs of the signals 3 and 31 change from “H” to “L”, both the first sub-control signal S1 and the third sub-control signal S3 become “H”, which is almost the same as the time T4. At the time, the PMOS transistors 7 and 29 are turned off.

As described above, at time T4, when the input signal changes from "H" to "L", the PMOS transistors 5, 7, 2
9 turns off and the NMOS transistor 6 turns on.
The potential of the output terminal 1 decreases from the potential Vdd to the ground potential GND. However, the potential is the first threshold 2
Until the voltage reaches Vdd / 3, the inverters 11 and 12 determine the potential of the output terminal 1 to be "H", and both outputs remain at "L". Therefore, NAND gates 15, 33
Keeps "H", and the NMOS transistors 8 and 30 remain off.

Since the NMOS transistor 6 is turned on, the potential of the output terminal 1 keeps decreasing, and at time T5, the potential of the output terminal 1 becomes the first threshold value 2Vdd / 3.
Then, the output of the inverter 11 changes from "L" to "H". As a result, the inputs of the NAND gate 33 all become "H", so that the output of the NAND gate 33 changes from "H" to "L", and the fourth sub-control signal S4 changes from "L" to "H". As a result, the NMOS transistor 30 that has been turned off is turned on. However, output terminal 1
Until the potential of the inverter 12 reaches the second threshold value Vdd / 3, the output of the inverter 12 remains at "L", the second sub-control signal S2 also remains at "L", and the NMOS transistor 8 is turned on. do not do.

At time T5, the output terminal 1 has an NMOS
Since it is connected to the ground potential GND via the two transistors 6 and 30, the current flowing from the output terminal 1 increases, and the rate of decrease in the potential of the output terminal 1 increases. Then, at time T6, the potential of the output terminal 1 becomes the second threshold Vd.
When d / 3 is reached, the output of the inverter 12 changes from "L" to "H". As a result, the inputs of the NAND gate 15 all become "H", so that the output changes from "H" to "L", and the second sub-control signal S2 changes from "L" to "H". As a result, the NMOS transistor 8 that has been turned off is turned on.

The outputs of the NOR gates 13 and 31 are "L" as long as the first main control signal M1 is "H" without depending on the outputs of the inverters 11 and 12, so that the first sub control The signal S1 and the third sub-control signal S3 remain "H" irrespective of the potential of the output terminal 1. Therefore,
The PMOS transistors 5, 7, and 29 remain off regardless of the time T5 or the time T6, and do not affect the potential of the output terminal 1.

As described above, in this embodiment, by dividing the timing of adding the current into two stages, it is possible to realize a smoother slew rate control than in the first embodiment.

Of course, it is also possible to determine the logic of the output signal with different threshold values when the potential of the output terminal rises and falls. However, as in the present embodiment, the same threshold value (2Vdd / 3, Vdd / 3) is used when the potential of the output terminal rises and when the potential of the output terminal falls.
There is an advantage that the configuration is simplified when the logic is determined by using the above.

Using this embodiment, a tristate output circuit can be formed as in the fourth to sixth embodiments.

[0112]

According to the output circuit of the present invention, after the first main transistor is turned on, the second sub-transistor is turned on so that a positive feedback is applied to the output signal. The same applies to the second main transistor and the second sub-transistor. Therefore, it is not necessary to prepare transistors having different gate lengths in an output circuit for suppressing an abrupt change in an output signal. Therefore, the degree of freedom of design in the master slice method can be increased.

According to the output circuit according to the second aspect of the present invention, in the case where the output signal goes from the first potential to the second potential and vice versa, the first or the second signal is generated at the timing when the potential change becomes gentle. Since the second sub-transistor is turned on, the potential change can be made closer to a straight line.

According to the output circuit of the present invention, two different first and second threshold values can be realized.

According to the output circuit of the present invention, the change in the output signal is determined by the circuit having hysteresis, so that the noise resistance can be enhanced.

According to the output circuit of the present invention, positive feedback can be applied to the output signal with a simple configuration.

According to the output circuit of the sixth aspect of the present invention, the effects of the first to fifth aspects can be obtained while functioning as a tri-state buffer.

According to the output circuit of the present invention, the number of sub-transistors can be increased to make the potential change of the output signal closer to a straight line.

According to the output circuit according to the eighth aspect of the present invention, the effect of the seventh aspect can be obtained without complicating the circuit configuration.

According to the output circuit of the ninth aspect of the present invention, when the output signal transitions to the first potential due to the transition of the input signal, first the main switching element is turned on, and then the sub-switching element is turned on. I do. As described above, since the potential of the output signal goes to the first potential through a plurality of stages, generation of noise can be suppressed without abrupt change.

According to the output circuit of the tenth aspect of the present invention, it is possible to suppress the output signal, particularly the beginning of the potential change, and to more effectively suppress the generation of noise.

According to the output circuit of the present invention, even if the output circuit is formed using transistors, transistors having different gate lengths are prepared in order to suppress a rapid change in the output signal. No need. Therefore, the degree of freedom of design in the master slice method can be increased.

According to the output circuit of the twelfth aspect of the present invention, first, the potential of the output signal starts to shift from the second potential to the first potential due to conduction of the main switching element, and the predetermined potential is determined in the middle of the transition. Threshold is reached. Since the sub-switching element is turned on only after the potential of the output signal reaches the predetermined threshold value, the sub-switching element can be turned on later than the main switching element.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a basic configuration of an output circuit according to the present invention.

FIG. 2 is a circuit diagram showing a configuration of an output circuit according to the first embodiment of the present invention.

FIG. 3 is a diagram showing an operation of the output circuit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an operation of the output circuit according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of an output circuit according to a second embodiment of the present invention.

FIG. 6 is a diagram showing an operation of the output circuit according to the second embodiment of the present invention.

FIG. 7 is a diagram showing an operation of the output circuit according to the second embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of an output circuit according to a third embodiment of the present invention.

9 is a graph showing a hysteresis property of the hysteresis circuit 23. FIG.

FIG. 10 is a circuit diagram showing a configuration of an output circuit according to a fourth embodiment of the present invention.

FIG. 11 is a circuit diagram showing a configuration of an output circuit according to a fifth embodiment of the present invention.

FIG. 12 is a circuit diagram showing a configuration of an output circuit according to a sixth embodiment of the present invention.

FIG. 13 is a circuit diagram showing a configuration of an output circuit according to a seventh embodiment of the present invention.

FIG. 14 is a diagram showing an operation of the output circuit according to the seventh embodiment of the present invention.

FIG. 15 is a diagram showing an operation of the output circuit according to the seventh embodiment of the present invention.

FIG. 16 is a circuit diagram showing an example of a conventional output circuit.

FIG. 17 is a diagram showing the operation of a conventional output circuit.

[Explanation of symbols]

1 output terminal, 2,201,202 prebuffer,
3,301-302 main buffer, 4,401-4
04 feedback circuit, 5,7,29 PMOS transistor, 6,8,30 NMOS transistor, 11,1
2,14,16-19,21 Inverter, 13,2
2,31 NOR gate, 15,20,33 NAND
Gate, 23 hysteresis circuit.

Claims (12)

[Claims] 1. An output circuit comprising: an input terminal to which an input signal conforming to binary logic is supplied; and an output terminal to output an output signal that changes in accordance with a transition of the logic of the input signal. a) (a-1) a first electrode to which a first potential corresponding to a first logic value which is one of the binary logic is applied, a second electrode connected to the output terminal, and a first main control A first main transistor having a control electrode receiving a signal; and (a-2) a first electrode to which a second potential corresponding to a second logical value complementary to the first logical value of the binary logic is applied. A second main transistor having a second electrode connected to the output terminal, and a control electrode receiving a second main control signal; (a-3) a first electrode to which the first potential is applied; A first sub-transistor having a second electrode connected to the output terminal and a control electrode receiving a first sub-control signal; (A-4) a second sub-transistor having a first electrode to which the second potential is applied, a second electrode connected to the output terminal, and a control electrode to receive a second sub-control signal (B) a pre-buffer that generates the first and second main control signals based on the input signal; and (c) (c-1) a first threshold value higher than a first threshold value. When the output signal reaches the first threshold value during the transition from a value close to the second potential to the first potential, the first main control signal is changed to the first sub control signal. Output as the first
(C-2) the output signal reaches the second threshold value during the transition from the value closer to the first potential to the second potential than the second threshold value. A second logic gate that outputs the second main control signal as the second sub-control signal. 2. The method according to claim 1, wherein the first and second thresholds are close to the first and second potentials, respectively, for an intermediate value between the first potential and the second potential. Output circuit as described. 3. The first main transistor is configured such that when the first main control signal corresponds to the second logical value, the second main transistor determines that the second main control signal is equal to the first logical value.
When the first sub-transistor corresponds to a logical value, the first sub-transistor is connected to the second sub-control signal when the first sub-control signal corresponds to the second logical value. In the case of the first logical value, each conducts,
(C-1-1) an inverter that inverts the output signal with the first threshold value, and (c-1-2) an output of the inverter of the first logic gate. The first
And a logic element that outputs the second logical value as the first sub-control signal when any of the main control signals takes the second logical value. 1) an inverter for inverting the output signal with the second threshold value, and (c-2-2) both the output of the inverter of the second logic gate and the second main control signal 3. The output circuit according to claim 2, further comprising: a logic element that outputs said first logical value as said second sub-control signal when taking one logical value. 4. The output signal of the first and second logic gates during the transition of the output signal from a value closer to the second potential than the first threshold toward the first potential. When the first threshold value is reached, the second
Logic, when the output signal reaches the second threshold while the output signal transitions from a value closer to the first potential than the second threshold toward the second potential. The first logic includes a hysteresis circuit that outputs the first logic in common. The first logic gate is provided when both the output of the hysteresis circuit and the first main control signal take the second logic value. A logic element that outputs the second logic value as the first sub-control signal, wherein the second logic gate is configured such that both the output of the hysteresis circuit and the second main control signal are the first logic value. 3. The output circuit according to claim 2, further comprising a logic element that outputs the first logical value as the second sub-control signal when taking a value. 5. The output circuit according to claim 1, wherein said first threshold value is equal to said second threshold value. 6. The pre-buffer inputs the input signal and a state control signal, and when the control signal is inactive, the pre-buffer shares a logic based on only the input signal with the first and second signals. Output as a main control signal, and when the control signal is inactive, regardless of the input signal, deactivate both the first main control signal and the second main control signal, The output circuit according to any one of claims 1 to 5, wherein both the first and second main transistors are turned off. 7. The main buffer includes: (a-5) a first electrode to which the first potential is applied, a second electrode connected to the output terminal, and a control electrode for receiving a third sub-control signal. (A-6) a first electrode supplied with the second potential, a second electrode connected to the output terminal, and a control electrode receiving a fourth sub-control signal. A fourth sub-transistor; and (c-3) the output signal during a transition from a value closer to the second potential than a third threshold toward the first potential. A third logic gate for outputting the first main control signal as the third sub-control signal when the third threshold value is reached, (c-4) During the transition from a value close to the first potential to the second potential, the output signal When it reaches the threshold, the second main control signal further comprises a fourth logic gate output as the fourth sub-control signal, the output circuit of claim 1, wherein. 8. The output circuit according to claim 7, wherein said third threshold value is equal to said second threshold value, and said fourth threshold value is equal to said first threshold value. 9. An output circuit comprising: an input terminal to which an input signal conforming to a binary logic is provided; and an output terminal to output an output signal that changes in accordance with a logic transition of the input signal. A first terminal to which a first potential corresponding to a first logical value of binary logic is applied; and a second terminal connected to the output terminal, between the first terminal and the second terminal thereof. A main switching element for conducting / non-conducting the first terminal, a first end to which the first potential is applied, and a second end connected to the output terminal. A sub-switching element that conducts / non-conducts between them, wherein the main switching element conducts from a state in which both the main switching element and the sub-switching element are non-conducting due to the transition of the input signal. The main switching element is An output circuit in which the sub-switching element is also turned on after passing through. 10. The output circuit according to claim 9, wherein a current flowing through the main switching element is smaller than that of the sub switching element. 11. The output circuit according to claim 9, wherein said main switching element and said sub-switching element are constituted by transistors. 12. The conduction of the main switching element changes the potential of the output signal from a second potential corresponding to a second logic value complementary to a first logic value of the binary logic to the first potential.
The sub-switching element starts conducting when the potential of the output signal reaches a predetermined threshold value by the transition;
The output circuit according to claim 9.