CN114006612A - High-voltage side gate drive circuit - Google Patents

High-voltage side gate drive circuit Download PDF

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CN114006612A
CN114006612A CN202111169545.1A CN202111169545A CN114006612A CN 114006612 A CN114006612 A CN 114006612A CN 202111169545 A CN202111169545 A CN 202111169545A CN 114006612 A CN114006612 A CN 114006612A
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pulse generating
generating circuit
circuit
input end
output end
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张允武
陆扬扬
禹阔
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State Silicon Integrated Circuit Technology Wuxi Co ltd
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements

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Abstract

The application discloses high-voltage side grid driving circuit belongs to high-voltage power integrated circuit technical field. The circuit comprises: the circuit comprises a dynamic pulse generating circuit, a high-voltage level shifting circuit, a common-mode filter circuit, an RS trigger and an output stage buffer circuit which are connected in sequence; when the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the high-voltage side in a floating way. This application can avoid output signal by the mistake latch-up, promotes the reliability of chip.

Description

High-voltage side gate drive circuit
Technical Field
The embodiment of the application relates to the technical field of high-voltage power integrated circuits, in particular to a high-voltage side gate driving circuit.
Background
In a high-voltage floating gate driving chip, a high-voltage level shift circuit is needed to transfer a low-voltage domain signal to a high-voltage domain, as shown in fig. 1, MHIs a high side switching device in a half-bridge topology, MLIs a low side switching device in a half bridge topology. High-side switching device M is typically driven efficiently using floating gate driver chipsHThe floating gate drive chip comprises low-voltage input logic, a high-voltage region gate drive circuit and a low-voltage region gate drive circuit, LIN is an input signal of a low-side channel, HIN is an input signal of a high-side channel, both LIN and HIN are connected to the low-voltage input logic, and lowThe voltage input logic outputs two signals, i.e., IN _ L and IN _ H, wherein IN _ L is output to the low voltage region gate driving circuit, and IN _ H is output to the high voltage region gate driving circuit. LO is the output signal of the low-side channel, connected to MLHO is the output signal of the high-side channel, connected to MHA gate electrode of (1). VCC-to-GND voltage domain supplies power to the low voltage region circuit, VB-to-VS floating voltage domain supplies power to the high voltage region circuit, and VS terminal is connected to MHSource and MLOf the substrate. Using bootstrap diodes DBAnd a bootstrap capacitor CBSupply power to VB, when MLWhen turned on, VCC passes through DBIs a bootstrap capacitor CBCharging and supplying power for the grid drive circuit in the high-voltage area; when M isHAt turn-on, bootstrap capacitor CBAnd the task of supplying power to the high-voltage area grid driving circuit is carried out, and the steps are repeated. An inductor L with one end connected to the VS end and the other end connected to the output voltage Vout, a capacitor C and a resistor R0And one end of the parallel connection is connected to Vout, and the other end is connected to GND. In the high-voltage floating gate driving chip, it is necessary to transmit the low-voltage domain signals from VCC to GND to the high-voltage domain between VB to VS, and therefore a high-voltage level shift circuit is needed to achieve the above purpose. The traditional single-channel LDMOS (Laterally Diffused Metal Oxide Semiconductor) level shift circuit can lead the LDMOS to be conducted for a long time when being turned on, has extremely high requirement on the reliability of an integrated high-voltage lateral field effect transistor, and can cause great power consumption and reliability problems while limiting the highest working voltage of a chip.
In order to solve the above problems, a conventional signal transmission method is shown in fig. 2, in which a rising edge and a falling edge of an input wide pulse signal are respectively converted into a narrow pulse signal, and the two narrow pulse signals are restored to signals having the same width as the original signals by an RS flip-flop after the signals are transmitted to a high voltage region. The scheme greatly reduces the turn-on time of the LDMOS, reduces the power consumption of the whole chip and enables the LDMOS to work reliably and stably. With the rise of the current third-generation semiconductor, the switching frequency of the power device made of the third-generation semiconductor, especially the power device made of the gallium nitride material, is extremely high, and higher requirements are put on the minimum pulse width to which the chip can respond.
Fig. 3 shows the output response of the chip when a wider input pulse and a narrower input pulse are input. When the input signal IN is a relatively wide pulse (left half IN FIG. 3), the pulse generating circuit generates a rising edge and a falling edge of the input signal at t1Time t and4a narrow pulse signal is formed at the PG _ S and PG _ R ports at any moment, the PG _ S signal is transmitted to a high-voltage area HD _ S port through a high-voltage level shift circuit to form a low-level narrow pulse, and meanwhile, a driven MOS device of the high-voltage area is delayed for a period of time and then is subjected to t2The moment is conducted and the potential of the VS port is raised, the raising process can cause the drain terminal potential of the LDMOS to be represented as a logic low potential (taking VS as a reference zero point), and therefore, at t2To t3In the time period, the HD _ S and HD _ R ports are both logic low, and the common mode low of the HD _ R and HD _ S is filtered by the common mode filter circuit, so that the voltages at the S and R ports are both logic low in the time period. t is t4At the moment, the PG _ R signal is transmitted to a high-voltage HD _ R port through a high-voltage level shift circuit, a high-level narrow pulse signal is formed at an R end after the PG _ R signal passes through a common mode filter circuit, HO is converted into a low-level signal after a period of time delay, and then the voltage at a VS end gradually drops to zero level. When the input signal IN is a narrower pulse (right half IN FIG. 3), t6At the moment, the rising edge of the input signal IN forms a narrow pulse signal at the PG _ S port, the signal is transmitted to a high-voltage region through a high-voltage level shift circuit to enable an HD _ S signal to be converted into a low-level signal, and after a period of time delay, the signal is delayed at t7At time HO, it turns to high level and turns on the power device of the high voltage bridge wall, and then the VS voltage starts rising, as can be seen from the above description, the LDMOS drain potential appears as a logic low signal when the VS voltage rises, therefore, at t7To t10In the time period, the voltages of the HD _ R end and the HD _ S end are both presented as logic low potential, and all signals in the time period are filtered by the common mode filter circuit. At t8Time to t9Falling edge pulses caused by input signals during the rising period of VS between momentsThen, the reset pulse signal will be lost, and further the output signal HO of the high voltage region is in a latch state after going high, and cannot be turned off until the next falling edge pulse is effectively transmitted to the high voltage region. If the low-side signal outputs high level at this stage and the low-side power device is turned on, the upper and lower bridge arms are directly connected to damage the power device. Similarly, when the input signal IN appears as a high duty cycle, i.e., as a narrow negative pulse, the HD _ S signal will be drowned out during the VS dip phase, appearing as a HO output drop.
Disclosure of Invention
The embodiment of the application provides a high-voltage side gate driving circuit, which can solve the problems that an output signal is mistakenly latched in a constant high state and a low-side power device is damaged in a VS (voltage VS) rising stage due to a falling edge pulse of a high-level narrow pulse, and can also solve the problems that an output signal is mistakenly latched in a constant low state and output wave loss exists in a VS rising stage due to a rising edge pulse of a low-level narrow pulse. The technical scheme is as follows:
on one hand, the high-voltage side gate driving circuit is provided and comprises a dynamic pulse generating circuit, a high-voltage level shifting circuit, a common mode filter circuit, an RS trigger and an output stage buffer circuit;
the input end of the dynamic pulse generating circuit is used as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected with the first input end of the high-voltage level shifting circuit, and the second output end of the dynamic pulse generating circuit is connected with the second input end of the high-voltage level shifting circuit;
two output ends of the high-voltage level shift circuit are respectively connected with two input ends of the common-mode filter circuit, and two output ends of the common-mode filter circuit are respectively connected with a set end and a reset end of the RS trigger;
the output end of the RS trigger is connected with the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit is used as the output end of the high-voltage side gate driving circuit;
the high-voltage level shift circuit, the common-mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected with a high-voltage side power supply and a high-voltage side floating ground;
when the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the high-voltage side in a floating mode.
In one possible implementation, the high voltage level shifting circuit includes: the power supply comprises a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode and a second diode;
the grid electrode of the first LDMOS is used as a first input end of the high-voltage level shift circuit, the grid electrode of the second LDMOS is used as a second input end of the high-voltage level shift circuit, and the source electrodes of the first LDMOS and the second LDMOS are grounded;
the drain electrode of the first LDMOS, the first port of the first resistor and the cathode of the first diode are connected to a first connecting point, and the first connecting point is used as a first output end of the high-voltage level shift circuit;
the drain of the second LDMOS, the first port of the second resistor and the cathode of the second diode are connected to a second connection point, and the second connection point is used as a second output end of the high-voltage level shift circuit;
and the second port of the first resistor and the second port of the second resistor are respectively connected with the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected with the high-voltage side in a floating mode.
In one possible implementation form of the method,
when the input signal comprises a high-level narrow pulse, the dynamic pulse generating circuit is used for controlling the falling edge pulse width of the high-level narrow pulse; or the like, or, alternatively,
when the input signal comprises a low-level narrow pulse, the dynamic pulse generating circuit is used for controlling the pulse width of the rising edge of the low-level narrow pulse; or the like, or, alternatively,
when the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generation circuit is configured to control a falling edge pulse width of the high-level narrow pulse and a rising edge pulse width of the low-level narrow pulse.
In one possible implementation, when the dynamic pulse generating circuit is used for controlling the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source, and a falling edge pulse generating circuit;
the input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then is used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the falling edge pulse generating circuit;
and the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit.
In one possible implementation, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter, a second inverter, a first nor gate, a second nor gate, a third nor gate, and a fourth nor gate;
the input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is respectively connected with the first input ends of the first NOR gate and the second NOR gate at a third connection point;
the output end of the falling edge pulse generating circuit is respectively connected with the input end of the first inverter and the second input end of the fourth NOR gate at a fourth connection point; the output end of the first inverter is connected with the second input end of the first NOR gate; the output end of the first NOR gate is connected with the second input end of the second NOR gate; the output end of the second NOR gate is connected with the first input end of the third NOR gate; the output end of the third NOR gate is connected with the first input end of the fourth NOR gate; the output end of the fourth nor gate is respectively connected with the input end of the second inverter and the second input end of the third nor gate; and the output end of the second inverter is used as the second output end of the dynamic pulse generating circuit.
In one possible implementation form of the method,
when the third connection point is at a high level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at a high level;
when the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output end of the dynamic pulse generating circuit is the same as the last state;
when the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at an effective high level;
when the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is at an invalid low level.
In one possible implementation, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit, and a controlled current source;
the first input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the falling edge pulse generating circuit is used as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the rising edge pulse generating circuit;
and the output end of the rising edge pulse generating circuit is used as a first output end of the dynamic pulse generating circuit.
In one possible implementation manner, when the dynamic pulse generation circuit is used for controlling the falling edge pulse width and the rising edge pulse width, the dynamic pulse generation circuit includes a rising edge pulse generation circuit, a falling edge pulse generation circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source;
the first input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the first delay circuit; the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the second delay circuit;
the output end of the first delay circuit is connected with the input end of the first controlled current source, and the output end of the first controlled current source is connected with the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected with the input end of the second controlled current source, and the output end of the second controlled current source is connected with the second input end of the rising edge pulse generating circuit.
In one possible implementation form of the method,
the rising edge pulse generating circuit comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate, and when the rising edge pulse generating circuit comprises one input end, the input end of the third inverter is used as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit comprises two input ends, the two input ends of the third inverter are respectively used as a first input end and a second input end of the rising edge pulse generating circuit; the output end of the third inverter is connected with the input end of the fourth inverter and the second input end of the fifth nor gate respectively, the output end of the fourth inverter is connected with the anode of the first capacitor and the input end of the fifth inverter respectively, the cathode of the first capacitor is grounded, the output end of the fifth inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the fifth nor gate, and the output end of the fifth nor gate is used as the output end of the rising edge pulse generating circuit;
when the falling edge pulse generating circuit comprises one input end, the input end of the seventh inverter is used as the input end of the falling edge pulse generating circuit, and the input end of the falling edge pulse generating circuit is connected with the second input end of the sixth NOR gate; when the falling edge pulse generating circuit comprises two input ends, the two input ends of the seventh inverter are respectively used as a first input end and a second input end of the falling edge pulse generating circuit, and the first input end of the falling edge pulse generating circuit is connected with the second input end of the sixth nor gate; an output end of the seventh inverter is connected with an anode of the second capacitor and an input end of the eighth inverter respectively, a cathode of the second capacitor is grounded, an output end of the eighth inverter is connected with an input end of the ninth inverter, an output end of the ninth inverter is connected with a first input end of the sixth nor gate, and an output end of the sixth nor gate is used as an output end of the falling edge pulse generating circuit;
the delay circuit comprises a tenth inverter, an eleventh inverter and a third capacitor, wherein the input end of the tenth inverter is used as the input end of the delay circuit, the output end of the tenth inverter is respectively connected with the anode of the third capacitor and the input end of the eleventh inverter, the cathode of the third capacitor is grounded, and the output end of the eleventh inverter is used as the output end of the delay circuit;
when the dynamic pulse generating circuit further comprises the controlled current source, the controlled current source comprises a current source and a PMOS (P-channel metal oxide semiconductor) tube, the current source is connected between a power supply and a source stage of the PMOS tube, a grid electrode of the PMOS tube is used as an input end of the controlled current source, and a drain electrode of the PMOS tube is used as an output end of the controlled current source.
In one possible implementation, the delay value of the delay circuit is according to the formula tP+(ΔVS× RL×CDS) (VB-Vth), where VB is the high side power supply and R isLIs a load resistance of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and DeltaVSIs the variation of the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
The technical scheme provided by the application has the beneficial effects that:
1. the high-voltage side gate driving circuit can dynamically adjust the pulse width of the rising edge and/or the falling edge of the narrow pulse, and prevent output signals from being locked in a constant-high or constant-low state by mistake, so that the reliability of a chip is ensured.
2. The maximum delay value of the pulse width comes from the minimum speed of charge leakage of the LDMOS drain terminal, and the pulse signal is ensured not to be submerged in the VS voltage change stage.
3. Simple structure avoids bringing extra cost.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a half-bridge topology using a high voltage floating gate driver chip;
FIG. 2 is a prior art high voltage level shift circuit employing a dual path LDMOS;
FIG. 3 is a waveform diagram illustrating normal operation and fault operation of the double pulse circuit shown in FIG. 2;
FIG. 4 is a circuit diagram of a high side gate driving circuit according to the present application;
FIG. 5 is a circuit diagram of a dynamic pulse generating circuit;
FIG. 6 is a waveform diagram illustrating operation of the circuit of FIG. 5;
FIG. 7 is a circuit diagram of the circuit of FIG. 5;
FIG. 8 is a circuit diagram of another dynamic pulse generating circuit;
FIG. 9 is a waveform diagram illustrating operation of the circuit of FIG. 8;
FIG. 10 is a circuit diagram of another dynamic pulse generating circuit;
fig. 11 is a circuit diagram of another dynamic pulse generating circuit.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present application more clear, the embodiments of the present application will be further described in detail with reference to the accompanying drawings.
Referring to fig. 4, a high-side gate driving circuit according to an embodiment of the present disclosure is shown, which includes a dynamic pulse generating circuit, a high-voltage level shifting circuit, a common mode filter circuit, an RS flip-flop, and an output stage Buffer circuit (Buffer).
The input end of the dynamic pulse generating circuit is used as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected with the first input end of the high-voltage level shifting circuit, and the second output end of the dynamic pulse generating circuit is connected with the second input end of the high-voltage level shifting circuit. The input signal IN _ H of the dynamic pulse generating circuit is from the input signal of the high-voltage side channel, the output signal of the first output end of the dynamic pulse generating circuit is PG _ S, and the output signal of the second output end of the dynamic pulse generating circuit is PG _ R.
Two output ends of the high-voltage level shift circuit are respectively connected with two input ends of the common mode filter circuit, and two output ends of the common mode filter circuit are respectively connected with a set end S and a reset end R of the RS trigger.
The output end of the RS trigger is connected with the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit is used as the output end of the high-voltage side gate driving circuit. Wherein, the output end of the output stage buffer circuit is the output end of the high-side channel.
The high-voltage level shift circuit, the common mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected with a high-voltage side power supply VB and a high-voltage side floating ground VS. Namely, a high voltage level shift circuit, a common mode filter circuit, an RS flip-flop, and an output stage buffer circuit are connected between VB and VS.
When the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the floating ground VS on the high-voltage side. That is, when the input pulse width is narrow, the pulse widths of the rising edge and/or the falling edge of the input signal can be adaptively adjusted to obtain the pulse block widths of PG _ S and PG _ R.
The narrow pulse is a pulse having a pulse width smaller than a predetermined threshold. The predetermined threshold value here is according to the formula tP+(ΔVS×RL×CDS) V (VB-Vth), where VB is the high side power supply, RLIs a load resistor of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and is Delta VSIs the amount of change in the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
As shown in fig. 4, the high voltage level shifting circuit includes: first LDMOS LD3A second LDMOS LD4A first resistor R1A second resistor R2A first diode D3And a second diode D4；
First LDMOS LD3A gate of the first LDMOS LD serving as a first input terminal of the high-voltage level shift circuit4The first LDMOS LD as the second input terminal of the high-voltage level shift circuit3And a second LDMOS LD4The source of (2) is grounded; first LDMOS LD3And the first resistor R1First port, first diode D3The cathode of the high-voltage level shift circuit is connected with a first connecting point HD _ S which is used as a first output end of the high-voltage level shift circuit; second LDMOS LD4And the second resistor R2First port, second diode D4The cathode of the first connection point HD _ R is connected with a second connection point HD _ R which is used as a second output end of the high-voltage level shift circuit; a first resistor R1Second port and second resistor R2Respectively connected to a high-voltage side power supply VB, a first diode D3And a second diode D4Are connected to the high-side floating ground VS, respectively.
Wherein the input of the first input terminal of the high voltage level shift circuit is PG _ S, which acts on LD3A gate electrode of (1); the input of the second input terminal of the high voltage level shift circuit is PG _ R, which acts on LD4A gate electrode of (1). First diode D3And a second diode D4The function of the common-mode filter circuit is to clamp the voltage of two points HD _ S, HD _ R and protect the grid in the common-mode filter circuit.
The form of the dynamic pulse generating circuit may include the following three types:
1) when the input signal includes a high-level narrow pulse, the dynamic pulse generating circuit is used for controlling the falling edge pulse width of the high-level narrow pulse.
2) When the input signal includes a low-level narrow pulse, the dynamic pulse generating circuit is used for controlling the rising edge pulse width of the low-level narrow pulse. Wherein the content of the first and second substances,
3) when the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generating circuit is configured to control a falling edge pulse width of the high-level narrow pulse and a rising edge pulse width of the low-level narrow pulse.
Wherein, the high-level narrow pulse has a low duty cycle, for example, the duty cycle is close to 0%. The low-level narrow pulses have a high duty cycle, for example, close to 100%.
The circuit structures of these three types of dynamic pulse generating circuits will be described below.
In a first implementation form of the first form, when the dynamic pulse generating circuit is used to control the width of the falling edge pulse, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a controlled current source, and a falling edge pulse generating circuit, as shown in fig. 5.
The input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit. The input end of the rising edge pulse generating circuit and the first input end of the falling edge pulse generating circuit are input with IN _ H, and the output end of the rising edge pulse generating circuit outputs PG _ S.
The output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit; the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the falling edge pulse generating circuit so as to control the width of the falling edge pulse. And the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit. Wherein, the output end of the falling edge pulse generating circuit outputs PG _ R.
Fig. 6 is a waveform diagram of the operation of the dynamic pulse generating circuit in fig. 5, which is similar to fig. 2, and the waveform diagram can be divided into a left half portion and a right half portion, where the left half portion shows an input signal with a wider pulse width, and the rising edge pulse signal and its delay signal do not overlap with the falling edge pulse signal, so that the circuit can operate normally; the right half shows the input signal with narrower pulse width, and in order to prevent the falling edge pulse from being drowned by dV/dt noise, the falling edge pulse signal is delayed for a period of time, the delay time is determined by equation 2, and assuming that the threshold value of the response generated by the common mode filter circuit is Vth, the expression of dV/dt that can make the common mode filter circuit generate the response can be obtained as follows:
Figure RE-GDA0003445235120000111
where VB is the high side power supply, RLIs a load resistance of the high level shift circuit, CDSIs the drain-source parasitic capacitance of the LDMOS. As can be seen from equation 1, when the dV/dt value is smaller than this value, the common mode filter circuit will not respond, and therefore, the delay value of the delay circuit can be obtained:
Figure RE-GDA0003445235120000112
wherein, tPThe delay time of the LDMOS to the high side output HO.
As shown in fig. 7, the structures of the rising edge pulse generating circuit, the falling edge pulse generating circuit, the delay circuit, and the controlled current source will be described below.
The rising edge pulse generation circuit comprises a third inverter INV8And a fourth inverter INV9The fifth inverter INV10And a sixth inverter INV11A first capacitor C1And a fifth NOR gate NOR3Third inverter INV8The input terminal of the rising edge pulse generating circuit is used as the input terminal of the rising edge pulse generating circuit; third inverter INV8Output ends of the first and second inverters INV9And a fifth NOR gate NOR3Is connected to the second input terminal of the fourth inverter INV9Respectively with the first capacitor C1Positive electrode of (2) and fifth inverter INV10Is connected to the input terminal of a first capacitor C1Negative electrode of the fifth inverter INV is grounded10And the output end of the sixth inverter INV11Is connected to the input terminal of the sixth inverter INV11And the output terminal of the fifth NOR gate NOR3Is connected to the first input terminal of the fifth NOR gate NOR3As the output of the rising edge pulse generating circuit.
The falling edge pulse generation circuit comprises a seventh inverter INV14An eighth inverter INV15And a ninth inverter INV16A second capacitor C2And a sixth NOR gate NOR4Seventh inverter INV14Respectively as a first input terminal and a second input terminal of a falling edge pulse generating circuit, the first input terminal of the falling edge pulse generating circuit and a sixth NOR gate NOR4Is connected with the second input end; seventh inverter INV14Respectively with the second capacitor C2Positive electrode of (2) and eighth inverter INV15Is connected to the input terminal of a second capacitor C2Negative electrode of (1) is grounded, and an eighth inverter INV15And the ninth inverter INV16Is connected to the input terminal of the ninth inverter INV16And the output terminal of the sixth NOR gate NOR4Is connected to the first input terminal of the sixth NOR gate NOR4As an output of the falling edge pulse generating circuit.
The delay circuit comprises a tenth inverter INV12And an eleventh inverter INV13And a third capacitance C3The tenth inverter INV12The input end of the delay circuit is used as the input end of the delay circuit, and the tenth inverter INV12Respectively with the third capacitor C3Positive electrode of (2) and eleventh inverter INV13Is connected to the input terminal of a third capacitor C3Negative electrode of (1) is grounded, and an eleventh inverter INV13As the output of the delay circuit.
The controlled current source comprises a current source I1And PMOS transistor M1Current source I1Is connected to a power supply and a PMOS tube M1Between the source and the drain of the PMOS transistor M1The grid of the PMOS transistor M is used as the input end of the controlled current source1As the output of a controlled current sourceAnd (4) outputting.
In a second implementation form of the first form, when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter INV, as shown in fig. 817A second inverter INV18NOR of first NOR gate5NOR, second NOR gate6NOR, third NOR gate7And a fourth NOR gate NOR8。
The input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit. The input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit are input with IN _ H, and the output end of the rising edge pulse generating circuit outputs with PG _ S. The output ends of the delay circuits are respectively NOR-connected with the first NOR gates5And a second NOR gate NOR6Is connected to a third connection point IN 1. The output end of the falling edge pulse generation circuit is respectively connected with the first inverter INV17And a fourth NOR gate NOR8Is connected to a fourth connection point IN 2; first inverter INV17And the output terminal of the first NOR gate NOR5Is connected with the second input end; first NOR gate NOR5And the output terminal of the second NOR gate NOR6Is connected with the second input end; second NOR gate NOR6And the output terminal of the third NOR gate NOR7Is connected with the first input end of the first input end; third NOR gate NOR7And the output terminal of the fourth NOR gate NOR8Is connected with the first input end of the first input end; NOR of fourth NOR gate8Respectively with the second inverter INV18And a third NOR gate NOR7Is connected with the second input end; second inverter INV18As a second output terminal of the dynamic pulse generating circuit. Wherein, the second inverter INV18Output of PG _ R is.
The rising edge pulse generating circuit and the delay circuit may refer to the implementation in fig. 6. In addition, the falling edge pulse generating circuit in fig. 6 has two input terminals, and the falling edge pulse generating circuit in fig. 8 has one input terminal, and therefore, a modification can be made on the basis of the falling edge pulse generating circuit shown in fig. 6. After modification, an input terminal of the seventh inverter INV14 serves as an input terminal of the falling edge pulse generating circuit, the input terminal of the falling edge pulse generating circuit is connected to the second input terminal of the sixth NOR gate NOR4, and the rest of the structure is unchanged.
IN this embodiment, when the third connection point IN1 is at a high level and the fourth connection point IN2 is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at a high level; when the third connection point IN1 is at a high level and the fourth connection point IN2 is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is the same as the previous state; when the third connection point IN1 is at a low level and the fourth connection point IN2 is at a high level, the output of the second output terminal of the dynamic pulse generating circuit is at an active high level; when the third connection point IN1 is low and the fourth connection point IN2 is low, the output of the second output terminal of the dynamic pulse generating circuit is inactive low.
IN brief, IN a state where IN1 is 1 and IN2 is 1, the reset pulse PG _ R outputs a high level; IN the state where IN1 is 1 and IN2 is 0, the PG _ R signal remains unchanged from the previous state; IN a state where IN1 is 0 and IN2 is 1, PG _ R outputs an active high potential; IN a state where IN1 is 0 and IN2 is 0, PG _ R outputs an inactive low potential. In this way, PG _ R can be made to maintain the active signal to the end time of the rising edge pulse delay signal all the time when the end time of the rising edge pulse delay signal is later than the end time of the falling edge pulse.
FIG. 9 is a waveform diagram illustrating the operation of the circuit shown in FIG. 8, wherein the left half shows the input signal with wider pulse width, and it can be seen that the delay circuit has no influence on the operation of the circuit, and the circuit operates normally; the right half part shows the input signal with narrower pulse width, IN1 is the delay signal of the rising edge pulse signal PG _ S, and the falling edge signal falls according to the timing rule of the logic circuitThe edge is held until the IN1 signal goes from high to low starting from the time when the IN2 goes high, effectively preventing the chip from false triggering. Wherein, the delay value of the delay circuit is according to the formula tP+(ΔVS×RL×CDS) V (VB-Vth), where VB is the high side power supply, RLIs a load resistor of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and is Delta VSIs the amount of change in the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
In the second form, when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit and a controlled current source, as shown in fig. 10.
The first input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; and the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit. Wherein, the first input end of the rising edge pulse generating circuit and the input end of the falling edge pulse generating circuit input IN _ H, and the output end of the falling edge pulse generating circuit output PG _ R.
The output end of the falling edge pulse generating circuit is connected with the input end of the delay circuit; the output end of the controlled current source is connected with the second input end of the rising edge pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit. Wherein, PG _ S is output by the output end of the rising edge pulse generating circuit.
The delay circuit and the controlled current source may refer to the implementation in fig. 6, and the falling edge pulse generating circuit may refer to the implementation in fig. 8. In addition, the rising edge pulse generating circuit in fig. 6 has one input terminal, and the rising edge pulse generating circuit in fig. 10 has two input terminals, and therefore, a modification can be made on the basis of the rising edge pulse generating circuit shown in fig. 6. Improvement ofAfter-action, third inverter INV8As a first input terminal and a second input terminal of the rising edge pulse generating circuit, respectively.
Wherein, the delay value of the delay circuit is according to the formula tP+(ΔVS×RL×CDS) V (VB-Vth), where VB is the high side power supply, RLIs a load resistor of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and is Delta VSIs the amount of change in the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
As shown in fig. 11, in the third form, when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit includes a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source.
The first input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as a first output end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is connected with the input end of the first delay circuit; the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the second delay circuit. The first input end of the rising edge pulse generating circuit and the first input end of the falling edge pulse generating circuit input IN _ H, the output end of the rising edge pulse generating circuit outputs PG _ S, and the output end of the falling edge pulse generating circuit outputs PG _ R.
The output end of the first delay circuit is connected with the input end of a first controlled current source, and the output end of the first controlled current source is connected with the second input end of the falling edge pulse generating circuit; the output end of the second time delay circuit is connected with the input end of a second controlled current source, and the output end of the second controlled current source is connected with the second input end of the rising edge pulse generating circuit.
The rising edge pulse generating circuit may refer to an implementation of the rising edge pulse generating circuit in fig. 10, the falling edge pulse generating circuit may refer to an implementation of the falling edge pulse generating circuit in fig. 6, the first delay circuit and the second delay circuit may refer to an implementation of the delay circuit in fig. 6, and the first controlled current source and the second controlled current source may refer to an implementation of the controlled current source in fig. 6.
Wherein, the delay value of the delay circuit is according to the formula tP+(ΔVS×RL×CDS) V (VB-Vth), where VB is the high side power supply, RLIs a load resistor of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and is Delta VSIs the amount of change in the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The above description should not be taken as limiting the embodiments of the present application, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the embodiments of the present application should be included in the scope of the embodiments of the present application.

Claims (10)

1. A high-voltage side gate drive circuit is characterized by comprising a dynamic pulse generation circuit, a high-voltage level shift circuit, a common mode filter circuit, an RS trigger and an output stage buffer circuit;
the input end of the dynamic pulse generating circuit is used as the input end of the high-voltage side gate driving circuit, the first output end of the dynamic pulse generating circuit is connected with the first input end of the high-voltage level shifting circuit, and the second output end of the dynamic pulse generating circuit is connected with the second input end of the high-voltage level shifting circuit;
two output ends of the high-voltage level shift circuit are respectively connected with two input ends of the common-mode filter circuit, and two output ends of the common-mode filter circuit are respectively connected with a set end and a reset end of the RS trigger;
the output end of the RS trigger is connected with the input end of the output stage buffer circuit, and the output end of the output stage buffer circuit is used as the output end of the high-voltage side gate driving circuit;
the high-voltage level shift circuit, the common-mode filter circuit, the RS trigger and the output stage buffer circuit are respectively connected with a high-voltage side power supply and a high-voltage side floating ground;
when the input signal is a narrow pulse, the dynamic pulse generating circuit is used for adjusting the pulse width of the rising edge and/or the falling edge of the narrow pulse, so that the end time of the adjusted pulse is later than the end time of the sudden change of the high-voltage side in a floating mode.
2. The circuit of claim 1, wherein the high voltage level shifting circuit comprises: the power supply comprises a first LDMOS, a second LDMOS, a first resistor, a second resistor, a first diode and a second diode;
the grid electrode of the first LDMOS is used as a first input end of the high-voltage level shift circuit, the grid electrode of the second LDMOS is used as a second input end of the high-voltage level shift circuit, and the source electrodes of the first LDMOS and the second LDMOS are grounded;
the drain electrode of the first LDMOS, the first port of the first resistor and the cathode of the first diode are connected to a first connecting point, and the first connecting point is used as a first output end of the high-voltage level shift circuit;
the drain of the second LDMOS, the first port of the second resistor and the cathode of the second diode are connected to a second connection point, and the second connection point is used as a second output end of the high-voltage level shift circuit;
and the second port of the first resistor and the second port of the second resistor are respectively connected with the high-voltage side power supply, and the anodes of the first diode and the second diode are respectively connected with the high-voltage side in a floating mode.
3. The circuit of claim 1,
when the input signal comprises a high-level narrow pulse, the dynamic pulse generating circuit is used for controlling the falling edge pulse width of the high-level narrow pulse; or the like, or, alternatively,
when the input signal comprises a low-level narrow pulse, the dynamic pulse generating circuit is used for controlling the pulse width of the rising edge of the low-level narrow pulse; or the like, or, alternatively,
when the input signal includes a high-level narrow pulse and a low-level narrow pulse, the dynamic pulse generation circuit is configured to control a falling edge pulse width of the high-level narrow pulse and a rising edge pulse width of the low-level narrow pulse.
4. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a delay circuit, a controlled current source, and a falling edge pulse generating circuit;
the input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then is used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the falling edge pulse generating circuit;
and the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit.
5. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a delay circuit, a falling edge pulse generating circuit, a first inverter, a second inverter, a first NOR gate, a second NOR gate, a third NOR gate, and a fourth NOR gate;
the input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then used as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is respectively connected with the first input ends of the first NOR gate and the second NOR gate at a third connection point;
the output end of the falling edge pulse generating circuit is respectively connected with the input end of the first inverter and the second input end of the fourth NOR gate at a fourth connection point; the output end of the first inverter is connected with the second input end of the first NOR gate; the output end of the first NOR gate is connected with the second input end of the second NOR gate; the output end of the second NOR gate is connected with the first input end of the third NOR gate; the output end of the third NOR gate is connected with the first input end of the fourth NOR gate; the output end of the fourth nor gate is respectively connected with the input end of the second inverter and the second input end of the third nor gate; and the output end of the second inverter is used as the second output end of the dynamic pulse generating circuit.
6. The circuit of claim 5,
when the third connection point is at a high level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at a high level;
when the third connection point is at a high level and the fourth connection point is at a low level, the output of the second output end of the dynamic pulse generating circuit is the same as the last state;
when the third connection point is at a low level and the fourth connection point is at a high level, the output of the second output end of the dynamic pulse generating circuit is at an effective high level;
when the third connection point is at a low level and the fourth connection point is at a low level, the output of the second output terminal of the dynamic pulse generating circuit is at an invalid low level.
7. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the rising edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a falling edge pulse generating circuit, a delay circuit, and a controlled current source;
the first input end of the rising edge pulse generating circuit is connected with the input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the falling edge pulse generating circuit is used as the second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the delay circuit;
the output end of the delay circuit is connected with the input end of the controlled current source, and the output end of the controlled current source is connected with the second input end of the rising edge pulse generating circuit;
and the output end of the rising edge pulse generating circuit is used as a first output end of the dynamic pulse generating circuit.
8. The circuit of claim 3, wherein when the dynamic pulse generating circuit is used to control the falling edge pulse width and the rising edge pulse width, the dynamic pulse generating circuit comprises a rising edge pulse generating circuit, a falling edge pulse generating circuit, a first delay circuit, a second delay circuit, a first controlled current source, and a second controlled current source;
the first input end of the rising edge pulse generating circuit is connected with the first input end of the falling edge pulse generating circuit and then serves as the input end of the dynamic pulse generating circuit; the output end of the rising edge pulse generating circuit is used as the first output end of the dynamic pulse generating circuit, and the output end of the rising edge pulse generating circuit is connected with the input end of the first delay circuit; the output end of the falling edge pulse generating circuit is used as a second output end of the dynamic pulse generating circuit, and the output end of the falling edge pulse generating circuit is connected with the input end of the second delay circuit;
the output end of the first delay circuit is connected with the input end of the first controlled current source, and the output end of the first controlled current source is connected with the second input end of the falling edge pulse generating circuit; the output end of the second delay circuit is connected with the input end of the second controlled current source, and the output end of the second controlled current source is connected with the second input end of the rising edge pulse generating circuit.
9. The circuit according to any one of claims 4 to 7,
the rising edge pulse generating circuit comprises a third inverter, a fourth inverter, a fifth inverter, a sixth inverter, a first capacitor and a fifth NOR gate, and when the rising edge pulse generating circuit comprises one input end, the input end of the third inverter is used as the input end of the rising edge pulse generating circuit; when the rising edge pulse generating circuit comprises two input ends, the two input ends of the third inverter are respectively used as a first input end and a second input end of the rising edge pulse generating circuit; the output end of the third inverter is connected with the input end of the fourth inverter and the second input end of the fifth nor gate respectively, the output end of the fourth inverter is connected with the anode of the first capacitor and the input end of the fifth inverter respectively, the cathode of the first capacitor is grounded, the output end of the fifth inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the fifth nor gate, and the output end of the fifth nor gate is used as the output end of the rising edge pulse generating circuit;
when the falling edge pulse generating circuit comprises one input end, the input end of the seventh inverter is used as the input end of the falling edge pulse generating circuit, and the input end of the falling edge pulse generating circuit is connected with the second input end of the sixth NOR gate; when the falling edge pulse generating circuit comprises two input ends, the two input ends of the seventh inverter are respectively used as a first input end and a second input end of the falling edge pulse generating circuit, and the first input end of the falling edge pulse generating circuit is connected with the second input end of the sixth nor gate; an output end of the seventh inverter is connected with an anode of the second capacitor and an input end of the eighth inverter respectively, a cathode of the second capacitor is grounded, an output end of the eighth inverter is connected with an input end of the ninth inverter, an output end of the ninth inverter is connected with a first input end of the sixth nor gate, and an output end of the sixth nor gate is used as an output end of the falling edge pulse generating circuit;
the delay circuit comprises a tenth inverter, an eleventh inverter and a third capacitor, wherein the input end of the tenth inverter is used as the input end of the delay circuit, the output end of the tenth inverter is respectively connected with the anode of the third capacitor and the input end of the eleventh inverter, the cathode of the third capacitor is grounded, and the output end of the eleventh inverter is used as the output end of the delay circuit;
when the dynamic pulse generating circuit further comprises the controlled current source, the controlled current source comprises a current source and a PMOS (P-channel metal oxide semiconductor) tube, the current source is connected between a power supply and a source stage of the PMOS tube, a grid electrode of the PMOS tube is used as an input end of the controlled current source, and a drain electrode of the PMOS tube is used as an output end of the controlled current source.
10. According toA circuit as claimed in any one of claims 4 to 7, characterized in that the delay value of the delay circuit is according to the formula tP+（ΔVS×RL×CDS) (VB-Vth), where VB is the high side power supply and R isLIs a load resistance of the high voltage level shift circuit, CDSIs the drain-source parasitic capacitance of LDMOS, Vth is the threshold value of the common mode filter circuit, and DeltaVSIs the variation of the voltage of the floating ground on the high-voltage side, tPThe delay time of the LDMOS to the high-side output terminal.
CN202111169545.1A 2021-10-08 2021-10-08 High-voltage side gate drive circuit Pending CN114006612A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111169545.1A CN114006612A (en) 2021-10-08 2021-10-08 High-voltage side gate drive circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111169545.1A CN114006612A (en) 2021-10-08 2021-10-08 High-voltage side gate drive circuit

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CN114006612A true CN114006612A (en) 2022-02-01

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