CN106708151B - A kind of low-power consumption low pressure difference linear voltage regulator system - Google Patents
A kind of low-power consumption low pressure difference linear voltage regulator system Download PDFInfo
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- CN106708151B CN106708151B CN201611218141.6A CN201611218141A CN106708151B CN 106708151 B CN106708151 B CN 106708151B CN 201611218141 A CN201611218141 A CN 201611218141A CN 106708151 B CN106708151 B CN 106708151B
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses a kind of low-power consumption low pressure difference linear voltage regulator system, comprising：Low-power consumption reference circuit；Undervoltage lockout circuit, it is connected with described low-power consumption reference circuit；Low differential voltage linear voltage stabilizer circuit, it is connected respectively with described low-power consumption reference circuit and undervoltage lockout circuit；Wherein, described low-power consumption reference circuit is to described undervoltage lockout circuit output reference voltage signal；Described low-power consumption reference circuit is to described low differential voltage linear voltage stabilizer circuit output bias current signal and reference voltage signal；Described undervoltage lockout circuit exports the high enable signal of under-voltage locking and the low enable signal of under-voltage locking to described low differential voltage linear voltage stabilizer circuit.The present invention can significantly improve the transient response performance of LDO circuit.
Description
Technical field
The present invention relates to technical field of power management, and in particular to a kind of low-power consumption low pressure difference linear voltage regulator system, should
For in navigation system, and with band under-voltage protection function.
Background technology
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) is by feat of simple in construction, low-power consumption, low defeated
The advantages that going out noise, chip occupying area few and cheap price, is widely used in portable type electronic product.Phase
Than there is the advantages that low ripple, low output noise in the DC-DC converter of DC-DC, LDO so that at some to output electricity
Precision and stability is pressed to require stricter occasion, LDO has an incomparable advantage, and market development prospect is boundless.
LDO circuit of the prior art as shown in figure 1, its by reference voltage VR, operational amplifier A, MOS driving tubes Q, string
Join divider resistance (R1、R2) form, reference voltage VRWhile input operational amplifier A, by divider resistance R1The signal sampled
Input operational amplifier A, operational amplifier A compare sampled signal and reference voltage V simultaneouslyRMagnitude of voltage size, then will compare
Relatively result is exported to MOS driving tubes Q grid and controlled it, so as to realize the driving adjustment to MOS driving tubes Q.
In order that the voltage that LDO circuit output of the prior art is stable, it usually needs external one big negative in output end
Carry electric capacity CL, utilize this heavy load electric capacity CLA Left half-plane zero point is produced with its equivalent series resistance ESR to carry out system
Compensation, ensure the stability of a system, and this compensation scheme needs to meet certain load current range.
As use of the circuit design to miniaturization and ceramic condenser is more and more extensive, and the ESR of ceramic condenser
(equivalent series resistance) very little, with corresponding electric capacity caused by zero point can be the purpose for not reaching compensation in the place of very high frequency
's.
LDO system power dissipations of the prior art typically also will be more than tens microamperes.In some low-power dissipation systems, also not
Commonly use such framework；The LDO of more research low-power consumption uses the structure without BGR mostly, although its power consumption is relatively low, circuit is tied in itself
Structure is also relatively simple, and the result that it is obtained is that precision is not high.
UVLO circuits of the prior art are as shown in Fig. 2 when reference circuit and under-voltage protection (UVLO) comparator share together
During one power vd D, reference circuit is to need certain supply voltage to establish.If work as VREFMagnitude of voltage be not electricity
When electricity is exactly a stable magnitude of voltage on source VDD mono-, when will have just beginning, detection voltage A points are higher than VREFVoltage,
Which results in false triggering.
The content of the invention
It is an object of the invention to provide a kind of low-power consumption low pressure difference linear voltage regulator system, in low pressure difference linear voltage regulator
It is outer to use ceramic condenser, the spike of output voltage is substantially reduced when overshoot and undershoot occurs in output voltage, is significantly improved
Its transient response performance.
In order to achieve the above object, the present invention is achieved through the following technical solutions：A kind of low-power consumption low pressure difference linearity voltage stabilizing
Device system, is characterized in, comprising：
Low-power consumption reference circuit；
Undervoltage lockout circuit, it is connected with described low-power consumption reference circuit；
Low differential voltage linear voltage stabilizer circuit, it is connected respectively with described low-power consumption reference circuit and undervoltage lockout circuit；Its
In
Described low-power consumption reference circuit is to described undervoltage lockout circuit output reference voltage signal；
Described low-power consumption reference circuit is to described low differential voltage linear voltage stabilizer circuit output bias current signal and base
Quasi- voltage signal；
Described undervoltage lockout circuit exports the high enable signal of under-voltage locking to described low differential voltage linear voltage stabilizer circuit
And the low enable signal of under-voltage locking.
Described undervoltage lockout circuit includes：
Power sense circuit, its input connect a power supply；
Under-voltage protection comparator, its inverting input are connected with the output end of described power sense circuit, homophase input
End is connected with described reference voltage signal output end, and output end is anti-by the first order phase inverter and second level phase inverter of concatenation
It is fed to the feedback input end of power sense circuit；Wherein
The output end of described first order phase inverter exports the high enable signal of under-voltage locking to low pressure difference linear voltage regulator electricity
Road；
The low enable signal of output end output under-voltage locking of described second level phase inverter is electric to low pressure difference linear voltage regulator
Road.
Described power sense circuit, which includes, is sequentially connected in series first resistor, second resistance, 3rd resistor, the described first electricity
One end of one the first transistor, the grid of described the first transistor and described first resistor is set between resistance and second resistance
It is connected with power supply, the other end of described first resistor is connected with the drain electrode of described the first transistor, described first crystal
The source electrode of pipe is connected with one end of described second resistance, and is connected to the inverting input of under-voltage protection comparator, described
The other end of second resistance is connected with described 3rd resistor, the other end ground connection of described 3rd resistor, also comprising one second
Transistor, the source ground of described second transistor, the grid of described second transistor are configured as power sense circuit
Feedback input end, the drain electrode of described second transistor is connected to second resistance and 3rd resistor common port.
Described low differential voltage linear voltage stabilizer circuit include an error amplifier, power adjustment pipe, series connection divider resistance and
Compensating electric capacity, wherein described error amplifier includes several inputs, respectively with described low-power consumption reference circuit and owing
Lock-in circuit connection is pressed, for receiving bias current signal, reference voltage signal and the under-voltage lock of the output of low-power consumption reference circuit
Determine the high enable signal of under-voltage locking, the low enable signal of under-voltage locking of circuit output；The grid of described power adjustment pipe and institute
The output end connection for the error amplifier stated, the source electrode connection power supply of described power adjustment pipe, described power adjustment pipe
Drain electrode is configured as the output end of low differential voltage linear voltage stabilizer circuit, and is grounded by divider resistance of connecting, described supplement
Electric capacity one end is connected with the drain electrode of described power adjustment pipe, and the other end is connected to the input of error amplifier reference voltage signal
End.
Described error amplifier is holohedral symmetry operational transconductance amplifier.
Described low differential voltage linear voltage stabilizer circuit also includes a load capacitance, described load capacitance one end and low voltage difference
The output end connection of linear regulator circuit, other end ground connection；One load resistance, described load resistance one end and low voltage difference line
Property voltage regulator circuit output end connection, the other end ground connection.
Described load capacitance is ceramic condenser.
The capacity of described load capacitance is 1 microfarad.
A kind of low-power consumption low pressure difference linear voltage regulator system of the present invention has advantages below compared with prior art：In low pressure
Ceramic condenser is used outside difference linear constant voltage regulator, the point of output voltage is substantially reduced when overshoot and undershoot occurs in output voltage
Peak, significantly improve its transient response performance；Provided with compensation circuit, in system load minimum, dominant pole is in output end, when negative
It is that dominant pole internally, can reach the stability in whole loading range to carry maximum.
Brief description of the drawings
Fig. 1 is the overall structure diagram of LDO circuit of the prior art；
Fig. 2 is the overall structure diagram of UVLO circuits of the prior art；
Fig. 3 is a kind of overall structure diagram of low-power consumption low pressure difference linear voltage regulator system of the present invention；
Fig. 4 is emulation Bode diagram of the circuit under underloading case of heavy load；
Fig. 5 is LDO small-signal analysis schematic diagram.
Embodiment
Below in conjunction with accompanying drawing, by describing a preferable specific embodiment in detail, the present invention is further elaborated.
A kind of low-power consumption low pressure difference linear voltage regulator system, as shown in figure 3, comprising：Low-power consumption reference circuit 100 (uses
Conventional low-power consumption reference circuit design, quiescent dissipation IQ=2.8uA, is described not as the intermediate portions of this patent)；Under-voltage lock
Determine circuit 200 (UVLO), be connected with described low-power consumption reference circuit 100；Low differential voltage linear voltage stabilizer circuit 300 (LDO), point
It is not connected with described low-power consumption reference circuit 100 and undervoltage lockout circuit 200；Wherein, described low-power consumption reference circuit 100
To the described output reference voltage signal V of undervoltage lockout circuit 200REF；Described low-power consumption reference circuit 100 is to described low
The output bias current signal VBIAS of pressure difference linear regulator circuit 300 and reference voltage signal VREF；Described under-voltage locking electricity
Road 200 exports the high enable signal UVLO_H of under-voltage locking to described low differential voltage linear voltage stabilizer circuit 300 and under-voltage locking is low
Enable signal UVLO_L.
In the present embodiment, as shown in figure 3, described undervoltage lockout circuit 200 includes：Power sense circuit, it is inputted
One power vd D of end connection；Under-voltage protection comparator 201, the output end of its inverting input and described power sense circuit connect
Connect, in-phase input end and described reference voltage signal VREFOutput end connects, the first order phase inverter that output end passes through concatenation
202 and second level phase inverter 203 feed back to the feedback input end of power sense circuit；Wherein, described first order phase inverter 202
Output end export the high enable signal UVLO_H of under-voltage locking to low differential voltage linear voltage stabilizer circuit 300；The described second level is anti-
The output end of phase device 203 exports the low enable signal UVLO_L of under-voltage locking to low differential voltage linear voltage stabilizer circuit 300.
In the present embodiment, as shown in figure 3, described power sense circuit, which includes, is sequentially connected in series first resistor R1, second
Resistance R2,3rd resistor R3, a first transistor MN2 is set between described first resistor R1 and second resistance R2, it is described
The first transistor MN2 grid and described first resistor R1 one end are connected with power supply, and described first resistor R1's is another
End is connected with described the first transistor MN2 drain electrode, described the first transistor MN2 source electrode and described second resistance R2
One end connection, and be connected to the inverting input of under-voltage protection comparator 201, the described second resistance R2 other end and institute
The 3rd resistor R3 connections stated, described 3rd resistor R3 other end ground connection are described also comprising a second transistor MN3
Second transistor MN3 source ground, the feedback that described second transistor MN3 grid is configured as power sense circuit are defeated
Enter end, described second transistor MN3 drain electrode is connected to second resistance R2 and 3rd resistor R3 common ports.
In the present embodiment, such as Fig. 3 and with reference to shown in Fig. 4, according to system scenario requirements, it is less than 1.5V in power vd D, closes
Disconnected LDO；Higher than 1.6V, LDO is opened.The first transistor MN2 (NMOS tube) is used in the present invention, and grid meets power vd D and is placed in
In the resistance chain of power sense circuit, it can be ensured that in VREFBefore not setting up, the first transistor MN2 is closed, and ensures B points
Voltage is always below VREFVoltage, you can ensure that false triggering will not occur for UVLO.When B points voltage is less than VREF, under-voltage protection compares
Device 201 exports high level, and by first order phase inverter 202 and first order phase inverter 203, UVLO_H voltages are low level, UVLO_
L voltages are high level.UVLO_L level feed-backs give second transistor MN3, and now second transistor MN3 is opened, and increase ratio is more electric
Pressure needs higher；Work as VREFWhen voltage is established substantially, the first transistor MN2 is opened, and power sense circuit starts to detect power vd D
Voltage, as B point voltage ratios VREFWhen voltage is high, under-voltage protection comparator 201 exports low level, by the He of first order phase inverter 202
First order phase inverter 203, UVLO_H voltages are high level, and UVLO_L voltages are low level.UVLO_L level feed-backs are brilliant to second
Body pipe MN3, now second transistor MN3 shut-offs, the detection voltage step-down that power vd D declines, realizes lag function.UVLO_H
The control terminal that as output signal to be respectively supplied to LDO to UVLO_L related, ensures after power vd D is higher than 1.6V, LDO can be just
Normally open, after VDD is less than 1.5V, LDO can be turned off, and not provide output voltage.
In the present embodiment, as shown in figure 3, described low differential voltage linear voltage stabilizer circuit 300 include an error amplifier,
Power adjustment pipe Mpower, series connection divider resistance (RF1、RF2) and compensating electric capacity, wherein described error amplifier is comprising some
Individual input, it is connected respectively with described low-power consumption reference circuit 100 and undervoltage lockout circuit 200, for receiving low-power consumption base
The under-voltage locking that bias current signal, reference voltage signal and the undervoltage lockout circuit 200 that quasi- circuit 100 exports export is high enabled
The low enable signal of signal, under-voltage locking；The output of described power adjustment pipe Mpower grid and described error amplifier
End connection, described power adjustment pipe Mpower source electrode connection power vd D, described power adjustment pipe Mpower drain electrode quilt
The output end of low differential voltage linear voltage stabilizer circuit 300 is configured to, and is grounded by divider resistance of connecting, described supplement electric capacity
CcOne end is connected with described power adjustment pipe Mpower drain electrode, and the other end is connected to error amplifier reference voltage signal
Input.
In the present embodiment, as shown in figure 3, in order to ensure the normal work of late-class circuit, described low pressure difference linearity is steady
Transformer circuits 300 also include a load capacitance CL(outside piece), described load capacitance CLOne end and low differential voltage linear voltage stabilizer circuit
300 output end connection, other end ground connection；One load resistance RL, described load resistance RLOne end and low pressure difference linear voltage regulator
The output end connection of circuit 300, other end ground connection；It is preferred that load capacitance CLFor ceramic condenser；Preferably, load capacitance CL's
Capacity is 1 microfarad.
In the present embodiment, the load capacity of low differential voltage linear voltage stabilizer circuit 300 is 10uA~2mA.In order to ensure to be
Unite not less to output capacitance using conventional miller compensation, this scheme in the stability of whole circuit scope, the program
Scheme has obvious effect, when output capacitance is larger, it is impossible to improve LDO stabilization.
In the present embodiment, error amplifier is holohedral symmetry operational transconductance amplifier, and MP2 and MP3 are input to pipe, positive
Termination series connection divider resistance RF1And RF2Common port, anti-phase termination VREF.MP4 and MP5 is current mirror image tube, MN4 and MN5 and MN6
It is current mirror image tube with MN7.The MP5 and MP7 public termination power adjustment pipe Mpower of drain electrode grid.
Compensation way in the present invention：Supplement the common port that electric capacity Cc mono- terminates MP2 and MN5, another termination output
VOUT.Compensation way in the present invention, in system load minimum, dominant pole is in output end, when heavy duty, dominant pole internally,
The stability in whole loading range can be reached.
Compensate stability analysis：LDO small-signal equivalent circuit is as shown in figure 5, wherein Gm1 is error amplifier, mutual conductance
For gm1；Gmp is power-amplifier stage, mutual conductance gmp；GC is feedback stage, mutual conductance gmc, MN5 pipe sampling feedback electric currents, sampling resistor
For 1/gmMN5, the amplification of MN4 pipes, gmc=gmMN4=gmMN5, the output equivalent resistance capacitance at node N1 is respectively ro1And C1, output
Load resistance electric capacity at node is RLAnd CL,
KCL equations are carried out to small-signal figure：
N1:
VOUT:
N2:s*CL*(VOUT-VN2)=VN2*gmMN5；
Transmission function is obtained by above-mentioned equation abbreviation：
Wherein：
A=RL(CL+gmp*ro1*Cc)；
B=RL*CL*ro1*C1；
C=C1*Cc*CL*ro1*RL/gmMN5
According to the change of load current, the specific transmission function under underloading and heavily loaded different situations can be obtained.During underloading,
gmpIt is smaller, CL*RL》gmp*ro1*Cc*RL, then transmission function can using abbreviation as：
In this function, there are a pair of zero pole points to cancel out each other, be left two limits, a dominant pole is in VOUTEnd, and frequency is very
It is low, this limit is only existed in GBW, meets the stability of a system.
When heavy duty, gmpIt can increase with the increase of load current, think when becomeing greater to sufficiently large：gmp*ro1*
Cc*RL》CL*RL.Then transmission function is approximately as described below：
The P in fully loaded transportation conditiond=1/ (gmp*Cc*ro1*RL) become dominant pole, Pnd=gmp*Cc/(C1*CL) it is time limit.
In this case the maximum unit gain bandwidth ω u=g of loopm1/ Cc, ensure the P under fully loaded transportation conditionnd>ωu.Simultaneously in system
Phase degree of desire and stability can be lifted with the increase of load current.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. a kind of low-power consumption low pressure difference linear voltage regulator system, it is characterised in that include：
Low-power consumption reference circuit；
Undervoltage lockout circuit, it is connected with described low-power consumption reference circuit；
Low differential voltage linear voltage stabilizer circuit, it is connected respectively with described low-power consumption reference circuit and undervoltage lockout circuit；Wherein
Described low-power consumption reference circuit is to described undervoltage lockout circuit output reference voltage signal；
Described low-power consumption reference circuit is electric to described low differential voltage linear voltage stabilizer circuit output bias current signal and benchmark
Press signal；
Described undervoltage lockout circuit exports the high enable signal of under-voltage locking to described low differential voltage linear voltage stabilizer circuit and owed
Pressure locks low enable signal；
Described low differential voltage linear voltage stabilizer circuit includes an error amplifier, power adjustment pipe, series connection divider resistance and compensation
Electric capacity, wherein described error amplifier includes several inputs, respectively with described low-power consumption reference circuit and under-voltage lock
Circuit connection is determined, for receiving bias current signal, reference voltage signal and the under-voltage locking electricity of the output of low-power consumption reference circuit
The high enable signal of under-voltage locking, the low enable signal of under-voltage locking of road output；The grid of described power adjustment pipe with it is described
The output end connection of error amplifier, the source electrode connection power supply of described power adjustment pipe, described power adjust the drain electrode of pipe
The output end of low differential voltage linear voltage stabilizer circuit is configured as, and is grounded by divider resistance of connecting, described compensating electric capacity
One end is connected with the drain electrode of described power adjustment pipe, and the other end is connected to the input of error amplifier reference voltage signal.
2. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 1, it is characterised in that described under-voltage locking electricity
Road includes：
Power sense circuit, its input connect a power supply；
Under-voltage protection comparator, its inverting input are connected with the output end of described power sense circuit, in-phase input end with
Described reference voltage signal output end connection, output end are fed back to by the first order phase inverter and second level phase inverter of concatenation
The feedback input end of power sense circuit；Wherein
The output end of described first order phase inverter exports the high enable signal of under-voltage locking to low differential voltage linear voltage stabilizer circuit；
The output end of described second level phase inverter exports the low enable signal of under-voltage locking to low differential voltage linear voltage stabilizer circuit.
3. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 2, it is characterised in that described power detecting electricity
Road is included and is sequentially connected in series first resistor, second resistance, 3rd resistor, and one the is set between described first resistor and second resistance
One end of one transistor, the grid of described the first transistor and described first resistor is connected with power supply, the described first electricity
The other end of resistance is connected with the drain electrode of described the first transistor, the source electrode of described the first transistor and described second resistance
One end connection, and be connected to the inverting input of under-voltage protection comparator, the other end of described second resistance with it is described
3rd resistor connects, the other end of described 3rd resistor ground connection, also comprising a second transistor, described second transistor
Source ground, the grid of described second transistor are configured as the feedback input end of power sense circuit, and described second is brilliant
The drain electrode of body pipe is connected to second resistance and 3rd resistor common port.
4. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 1, it is characterised in that described error amplifier
For holohedral symmetry operational transconductance amplifier.
5. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 1, it is characterised in that described low pressure difference linearity
Voltage regulator circuit also includes the output end company of a load capacitance, described load capacitance one end and low differential voltage linear voltage stabilizer circuit
Connect, other end ground connection；The output end of one load resistance, described load resistance one end and low differential voltage linear voltage stabilizer circuit connects
Connect, other end ground connection.
6. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 5, it is characterised in that described load capacitance is
Ceramic condenser.
7. the low-power consumption low pressure difference linear voltage regulator system as described in claim 5 or 6, it is characterised in that described load electricity
The capacity of appearance is 1 microfarad.
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| CN201611218141.6A CN106708151B (en) | 2016-12-26 | 2016-12-26 | A kind of low-power consumption low pressure difference linear voltage regulator system |
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Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020093268A1 (en) * | 2018-11-07 | 2020-05-14 | 北京比特大陆科技有限公司 | Low-dropout linear voltage-stabilizing circuit and electronic device |
| CN109274362A (en) * | 2018-12-03 | 2019-01-25 | 上海艾为电子技术股份有限公司 | Control circuit |
| CN111669136B (en) * | 2019-03-07 | 2023-04-18 | 雅特力科技(重庆)有限公司 | Multi-stage amplifier with stabilizing circuit |
| CN109947168A (en) * | 2019-03-25 | 2019-06-28 | 厦门科塔电子有限公司 | A kind of low noise low differential voltage linear voltage stabilizer circuit |
| CN115509286A (en) * | 2021-06-07 | 2022-12-23 | 圣邦微电子（北京）股份有限公司 | Undervoltage locking circuit |
| CN116169637B (en) * | 2023-04-06 | 2023-08-01 | 江苏帝奥微电子股份有限公司 | Low-power consumption undervoltage locking protection circuit suitable for high-voltage LDO |
| CN116880633A (en) * | 2023-07-10 | 2023-10-13 | 深圳飞渡微电子有限公司 | Low-dropout linear voltage regulator circuit capable of improving power supply voltage rejection ratio |
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| CN102299501A (en) * | 2010-06-28 | 2011-12-28 | 比亚迪股份有限公司 | Undervoltage protection circuit |
| US20120013317A1 (en) * | 2010-07-13 | 2012-01-19 | Ricoh Company, Ltd. | Constant voltage regulator |
| CN102495656A (en) * | 2011-12-09 | 2012-06-13 | 电子科技大学 | Low dropout linear regulator |
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| CN106708151A (en) | 2017-05-24 |
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