CN106708151A - Low power consumption low differential voltage linear voltage regulator system - Google Patents
Low power consumption low differential voltage linear voltage regulator system Download PDFInfo
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- CN106708151A CN106708151A CN201611218141.6A CN201611218141A CN106708151A CN 106708151 A CN106708151 A CN 106708151A CN 201611218141 A CN201611218141 A CN 201611218141A CN 106708151 A CN106708151 A CN 106708151A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
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Abstract
The invention discloses a low power consumptionlow differential voltage linear voltage regulator system. The system comprises alow power consumption benchmark circuit, an under-voltage locking circuit connected with the low power consumption benchmark circuit, a low differential voltage linear voltage regulator circuit connected with the low power consumption benchmark circuit and the under-voltage locking circuit respectively, wherein the low power consumption benchmark circuit outputs benchmark voltage signals to the under-voltage locking circuit, the low power consumption benchmark circuit outputs bias current signals and benchmark voltage signals to the low differential voltage linear voltage regulator circuit. The low power consumption low differential voltage linear voltage regulator system can substantially enhance the transient response performance of the LDO circuit.
Description
Technical field
The present invention relates to technical field of power management, and in particular to a kind of low-power consumption low pressure difference linear voltage regulator system, should
In for navigation system, and with band under-voltage protection function.
Background technology
Low pressure difference linear voltage regulator (Low Dropout Regulator, LDO) is by feat of simple structure, low-power consumption, low defeated
The advantages of going out noise, chip occupying area few and cheap price, is widely used in portable type electronic product.Phase
Than the advantages of in the DC-DC converter of DC-DC, LDO has low ripple, low output noise so that at some to output electricity
The stricter occasion of pressure precision and stability requirement, LDO has incomparable advantage, and market development prospect is boundless.
LDO circuit of the prior art is as shown in figure 1, it is by reference voltage VR, operational amplifier A, MOS driving tubes Q, string
Connection divider resistance (R1、R2) constitute, reference voltage VRWhile input operational amplifier A, by divider resistance R1The signal for sampling
Input operational amplifier A simultaneously, operational amplifier A compares sampled signal and reference voltage VRMagnitude of voltage size, then will compare
Relatively result is exported to the grid of MOS driving tubes Q and controlled it, so as to realize the driving adjustment to MOS driving tubes Q.
In order that the voltage of LDO circuit output stabilization of the prior art, it usually needs big negative in external one of output end
Carry electric capacity CL, using this heavy load electric capacity CLSystem is carried out with one Left half-plane zero point of its equivalent series resistance ESR generations
Compensate, it is ensured that the stability of a system, and this compensation scheme needs to meet certain load current range.
As circuit design is more and more extensive to the use of miniaturization and ceramic condenser, and ceramic condenser ESR
(equivalent series resistance) very little, the zero point produced with corresponding electric capacity can be the purpose for not reaching compensation in the place of very high frequency
's.
LDO system power dissipations of the prior art typically also will be more than tens microamperes.In some low-power dissipation systems, also not
Commonly use such framework；The LDO of more research low-power consumption uses the structure without BGR mostly, although its power consumption is relatively low, and circuit is tied in itself
Structure is also relatively simple, and the result that it is obtained is precision not high.
UVLO circuits of the prior art are as shown in Fig. 2 when reference circuit and under-voltage protection (UVLO) comparator are shared together
During one power vd D, reference circuit is that the certain supply voltage of needs could be set up.If working as VREFMagnitude of voltage be not electricity
When electricity is exactly the magnitude of voltage of stabilization on source VDD mono-, will exist when just starting, detection voltage A points are higher than VREFVoltage,
Which results in false triggering.
The content of the invention
It is an object of the invention to provide a kind of low-power consumption low pressure difference linear voltage regulator system, in low pressure difference linear voltage regulator
Outer use ceramic condenser, the spike of output voltage is substantially reduced when overshoot and undershoot occurs in output voltage, is significantly improved
Its transient response performance.
In order to achieve the above object, the present invention is achieved through the following technical solutions：A kind of low-power consumption low pressure difference linearity voltage stabilizing
Device system, is characterized in, comprising：
Low-power consumption reference circuit；
Undervoltage lockout circuit, is connected with described low-power consumption reference circuit；
Low differential voltage linear voltage stabilizer circuit, is connected with described low-power consumption reference circuit and undervoltage lockout circuit respectively；Its
In
Described low-power consumption reference circuit is to described undervoltage lockout circuit output reference voltage signal；
Described low-power consumption reference circuit is to described low differential voltage linear voltage stabilizer circuit output bias current signal and base
Quasi- voltage signal；
Described undervoltage lockout circuit exports under-voltage locking enable signal high to described low differential voltage linear voltage stabilizer circuit
And the low enable signal of under-voltage locking.
Described undervoltage lockout circuit is included：
Power sense circuit, its input connects a power supply；
Under-voltage protection comparator, its inverting input is connected with the output end of described power sense circuit, homophase input
End is connected with described reference voltage signal output end, and output end is anti-by the first order phase inverter and second level phase inverter for concatenating
It is fed to the feedback input end of power sense circuit；Wherein
The output end output under-voltage locking of described first order phase inverter is high to enable signal to low pressure difference linear voltage regulator electricity
Road；
The output end output under-voltage locking of described second level phase inverter is low to enable signal to low pressure difference linear voltage regulator electricity
Road.
Described power sense circuit is electric comprising first resistor, second resistance, 3rd resistor, described first is sequentially connected in series
A first transistor is set between resistance and second resistance, the grid of described the first transistor and one end of described first resistor
It is connected with power supply, the other end of described first resistor is connected with the drain electrode of described the first transistor, described first crystal
The source electrode of pipe is connected with one end of described second resistance, and is connected to the inverting input of under-voltage protection comparator, described
The other end of second resistance is connected with described 3rd resistor, and the other end of described 3rd resistor is grounded, also comprising one second
Transistor, the source ground of described transistor seconds, the grid of described transistor seconds is configured as power sense circuit
Feedback input end, the drain electrode of described transistor seconds is connected to second resistance and 3rd resistor common port.
Described low differential voltage linear voltage stabilizer circuit comprising an error amplifier, power adjustment pipe, series connection divider resistance and
Compensating electric capacity, wherein described error amplifier includes several inputs, respectively with described low-power consumption reference circuit and owe
Pressure lock-in circuit connection, bias current signal, reference voltage signal and under-voltage lock for receiving the output of low-power consumption reference circuit
Determine under-voltage locking enable signal high, the low enable signal of under-voltage locking of circuit output；The grid of described power adjustment pipe and institute
The output end connection of the error amplifier stated, the source electrode of described power adjustment pipe connects power supply, and described power adjusts pipe
Drain electrode is configured as the output end of low differential voltage linear voltage stabilizer circuit, and is grounded by divider resistance of connecting, described supplement
Electric capacity one end is connected with the drain electrode of described power adjustment pipe, and the other end is connected to the input of error amplifier reference voltage signal
End.
Described error amplifier is holohedral symmetry operational transconductance amplifier.
Described low differential voltage linear voltage stabilizer circuit also includes a load capacitance, described load capacitance one end and low voltage difference
The output end connection of linear regulator circuit, other end ground connection；One load resistance, described load resistance one end and low voltage difference line
Property voltage regulator circuit output end connection, the other end ground connection.
Described load capacitance is ceramic condenser.
The capacity of described load capacitance is 1 microfarad.
A kind of low-power consumption low pressure difference linear voltage regulator system of the present invention has advantages below compared with prior art：In low pressure
Ceramic condenser is used outside difference linear constant voltage regulator, the point of output voltage is substantially reduced when overshoot and undershoot occurs in output voltage
Peak, significantly improves its transient response performance；Be provided with compensation circuit, when system load is minimum, dominant pole in output end, when negative
It is that dominant pole internally, can reach the stability in whole loading range to carry maximum.
Brief description of the drawings
Fig. 1 is the overall structure diagram of LDO circuit of the prior art；
Fig. 2 is the overall structure diagram of UVLO circuits of the prior art；
Fig. 3 is a kind of overall structure diagram of low-power consumption low pressure difference linear voltage regulator system of the invention；
Fig. 4 is emulation Bode diagram of the circuit under underloading case of heavy load；
Fig. 5 is the small-signal analysis schematic diagram of LDO.
Specific embodiment
Below in conjunction with accompanying drawing, by describing a preferably specific embodiment in detail, the present invention is further elaborated.
A kind of low-power consumption low pressure difference linear voltage regulator system, as shown in figure 3, comprising：Low-power consumption reference circuit 100 (is used
Conventional low-power consumption reference circuit design, quiescent dissipation IQ=2.8uA, not as the intermediate portions description of this patent)；Under-voltage lock
Determine circuit 200 (UVLO), be connected with described low-power consumption reference circuit 100；Low differential voltage linear voltage stabilizer circuit 300 (LDO), point
It is not connected with described low-power consumption reference circuit 100 and undervoltage lockout circuit 200；Wherein, described low-power consumption reference circuit 100
To the described output reference voltage signal V of undervoltage lockout circuit 200REF；Described low-power consumption reference circuit 100 is to described low
The output bias current signal VBIAS of pressure difference linear regulator circuit 300 and reference voltage signal VREF；Described under-voltage locking electricity
Road 200 is low to the described output under-voltage locking enable signal UVLO_H high of low differential voltage linear voltage stabilizer circuit 300 and under-voltage locking
Enable signal UVLO_L.
In the present embodiment, as shown in figure 3, described undervoltage lockout circuit 200 is included：Power sense circuit, its input
One power vd D of end connection；Under-voltage protection comparator 201, its inverting input connects with the output end of described power sense circuit
Connect, in-phase input end and described reference voltage signal VREFOutput end is connected, the first order phase inverter that output end passes through concatenation
202 and second level phase inverter 203 feed back to the feedback input end of power sense circuit；Wherein, described first order phase inverter 202
Output end export under-voltage locking enable signal UVLO_H high to low differential voltage linear voltage stabilizer circuit 300；The described second level is anti-
The output end of phase device 203 exports the low enable signal UVLO_L of under-voltage locking to low differential voltage linear voltage stabilizer circuit 300.
In the present embodiment, as shown in figure 3, described power sense circuit is included is sequentially connected in series first resistor R1, second
Resistance R2,3rd resistor R3, set a first transistor MN2 between described first resistor R1 and second resistance R2, described
One end of the grid of the first transistor MN2 and described first resistor R1 are connected with power supply, and described first resistor R1's is another
End is connected with the drain electrode of described the first transistor MN2, the source electrode and described second resistance R2 of described the first transistor MN2
One end connection, and be connected to the inverting input of under-voltage protection comparator 201, the other end of described second resistance R2 and institute
The 3rd resistor R3 connections stated, the other end ground connection of described 3rd resistor R3 is described also comprising a transistor seconds MN3
The source ground of transistor seconds MN3, the feedback that the grid of described transistor seconds MN3 is configured as power sense circuit is defeated
Enter end, the drain electrode of described transistor seconds MN3 is connected to second resistance R2 and 3rd resistor R3 common ports.
In the present embodiment, such as shown in Fig. 3 and combination Fig. 4, according to system scenario requirements, 1.5V is less than in power vd D, is closed
Disconnected LDO；Higher than 1.6V, LDO is opened.The first transistor MN2 (NMOS tube), grid is used to meet power vd D and be placed in the present invention
In the resistance chain of power sense circuit, it can be ensured that in VREFBefore not setting up, the first transistor MN2 is closed, it is ensured that B points
Voltage is always below VREFVoltage, you can ensure that UVLO will not occur false triggering.When B points voltage is less than VREF, under-voltage protection compares
Device 201 exports high level, and by first order phase inverter 202 and first order phase inverter 203, UVLO_H voltages are low level, UVLO_
L voltages are high level.UVLO_L level feed-backs give transistor seconds MN3, and now transistor seconds MN3 is opened, and increase ratio is more electric
Pressure needs higher；Work as VREFWhen voltage is set up substantially, the first transistor MN2 is opened, and power sense circuit starts detection power vd D
Voltage, as B point voltage ratios VREFWhen voltage is high, the output low level of under-voltage protection comparator 201, by the He of first order phase inverter 202
First order phase inverter 203, UVLO_H voltages are high level, and UVLO_L voltages are low level.UVLO_L level feed-backs are brilliant to second
Body pipe MN3, now transistor seconds MN3 shut-offs, the detection voltage step-down that power vd D declines realizes lag function.UVLO_H
The related control ends of LDO are respectively supplied to as output signal, it is ensured that after power vd D is higher than 1.6V, LDO can be just to UVLO_L
Normally open, less than after 1.5V, LDO can be turned off VDD, not provide output voltage.
In the present embodiment, as shown in figure 3, described low differential voltage linear voltage stabilizer circuit 300 comprising an error amplifier,
Power adjustment pipe Mpower, series connection divider resistance (RF1、RF2) and compensating electric capacity, wherein described error amplifier is comprising some
Individual input, is connected, with described low-power consumption reference circuit 100 and undervoltage lockout circuit 200 for receiving low-power consumption base respectively
The under-voltage locking enable high of the bias current signal, reference voltage signal and the output of undervoltage lockout circuit 200 of the output of quasi- circuit 100
The low enable signal of signal, under-voltage locking；The grid of described power adjustment pipe Mpower and the output of described error amplifier
End connection, the source electrode of described power adjustment pipe Mpower connects power vd D, and described power adjusts the drain electrode quilt of pipe Mpower
The output end of low differential voltage linear voltage stabilizer circuit 300 is configured to, and is grounded by divider resistance of connecting, described supplement electric capacity
CcOne end is connected with the drain electrode of described power adjustment pipe Mpower, and the other end is connected to error amplifier reference voltage signal
Input.
In the present embodiment, as shown in figure 3, normal work in order to ensure late-class circuit, described low pressure difference linearity is steady
Transformer circuits 300 also include a load capacitance CL(outside piece), described load capacitance CLOne end and low differential voltage linear voltage stabilizer circuit
300 output end connection, other end ground connection；One load resistance RL, described load resistance RLOne end and low pressure difference linear voltage regulator
The output end connection of circuit 300, other end ground connection；It is preferred that load capacitance CLIt is ceramic condenser；Preferably, load capacitance CL's
Capacity is 1 microfarad.
In the present embodiment, the load capacity of low differential voltage linear voltage stabilizer circuit 300 is 10uA~2mA.In order to ensure to be
Unite in the stability of whole circuit scope, the program is provided without conventional miller compensation, this scheme is less to output capacitance
Scheme has obvious effect, when output capacitance is larger, it is impossible to improve the stabilization of LDO.
In the present embodiment, error amplifier is holohedral symmetry operational transconductance amplifier, and MP2 and MP3 is input to pipe, positive
Termination series connection divider resistance RF1And RF2Common port, anti-phase termination VREF.MP4 and MP5 is current mirror image tube, MN4 and MN5 and MN6
It is current mirror image tube with MN7.The grid of the public termination power adjustment pipe Mpower of drain electrode of MP5 and MP7.
Compensation way in the present invention：Supplement electric capacity Cc mono- terminates the common port of MP2 and MN5, another termination output
VOUT.Compensation way in the present invention, when system load is minimum, dominant pole in output end, when heavy duty, dominant pole internally,
The stability in whole loading range can be reached.
Compensation stability analysis：The small-signal equivalent circuit of LDO is as shown in figure 5, wherein Gm1 is error amplifier, mutual conductance
It is gm1；Gmp is power-amplifier stage, and mutual conductance is gmp；GC is feedback stage, and mutual conductance is gmc, MN5 pipe sampling feedback electric currents, sampling resistor
It is 1/gmMN5, the amplification of MN4 pipes, gmc=gmMN4=gmMN5, the output equivalent resistance capacitance at node N1 is respectively ro1And C1, output
Load resistance electric capacity at node is RLAnd CL,
KCL equations are carried out to small-signal figure：
N1:
VOUT:
N2:s*CL*(VOUT-VN2)=VN2*gmMN5；
Transmission function is obtained by above-mentioned equation abbreviation：
Wherein：
A=RL(CL+gmp*ro1*Cc)；
B=RL*CL*ro1*C1；
C=C1*Cc*CL*ro1*RL/gmMN5
According to the change of load current, the specific transmission function under underloading and heavily loaded different situations can be obtained.During underloading,
gmpIt is smaller, CL*RL》gmp*ro1*Cc*RL, then transmission function can be with abbreviation：
In this function, there are a pair of zero pole points to cancel out each other, be left two limits, a dominant pole is in VOUTEnd, and frequency is very
It is low, this limit is only existed in GBW, meet the stability of a system.
When heavy duty, gmpCan increase with the increase of load current, think when becomeing greater to sufficiently large：gmp*ro1*
Cc*RL》CL*RL.Then transmission function is approximately as described below：
The P in fully loaded transportation conditiond=1/ (gmp*Cc*ro1*RL) become dominant pole, Pnd=gmp*Cc/(C1*CL) it is time limit.
In this case maximum unit gain bandwidth ω u=g of loopm1/ Cc, it is ensured that the P under fully loaded transportation conditionnd>ωu.Simultaneously in system
Phase degree of desire and stability can be lifted with the increase of load current.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for of the invention
Various modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (8)
1. a kind of low-power consumption low pressure difference linear voltage regulator system, it is characterised in that include：
Low-power consumption reference circuit；
Undervoltage lockout circuit, is connected with described low-power consumption reference circuit；
Low differential voltage linear voltage stabilizer circuit, is connected with described low-power consumption reference circuit and undervoltage lockout circuit respectively；Wherein
Described low-power consumption reference circuit is to described undervoltage lockout circuit output reference voltage signal；
Described low-power consumption reference circuit is to described low differential voltage linear voltage stabilizer circuit output bias current signal and benchmark electricity
Pressure signal；
Described undervoltage lockout circuit exports under-voltage locking enable signal high and owes to described low differential voltage linear voltage stabilizer circuit
The low enable signal of pressure locking.
2. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 1, it is characterised in that described under-voltage locking electricity
Road includes：
Power sense circuit, its input connects a power supply；
Under-voltage protection comparator, its inverting input is connected with the output end of described power sense circuit, in-phase input end with
Described reference voltage signal output end connection, output end is fed back to by the first order phase inverter and second level phase inverter for concatenating
The feedback input end of power sense circuit；Wherein
The output end output under-voltage locking of described first order phase inverter is high to enable signal to low differential voltage linear voltage stabilizer circuit；
The output end output under-voltage locking of described second level phase inverter is low to enable signal to low differential voltage linear voltage stabilizer circuit.
3. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 2, it is characterised in that described power detecting electricity
Road sets one the comprising being sequentially connected in series first resistor, second resistance, 3rd resistor, between described first resistor and second resistance
One transistor, the described grid of the first transistor and one end of described first resistor is connected with power supply, the first described electricity
The other end of resistance is connected with the drain electrode of described the first transistor, the source electrode and described second resistance of described the first transistor
One end connection, and be connected to the inverting input of under-voltage protection comparator, the other end of described second resistance with it is described
3rd resistor is connected, the other end ground connection of described 3rd resistor, also comprising a transistor seconds, described transistor seconds
Source ground, the grid of described transistor seconds is configured as the feedback input end of power sense circuit, and described second is brilliant
The drain electrode of body pipe is connected to second resistance and 3rd resistor common port.
4. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 1, it is characterised in that described low pressure difference linearity
Voltage regulator circuit includes an error amplifier, power adjustment pipe, series connection divider resistance and compensating electric capacity, wherein described error is put
Big device includes several inputs, is connected with described low-power consumption reference circuit and undervoltage lockout circuit respectively, low for receiving
The under-voltage locking enable high of the bias current signal, reference voltage signal and undervoltage lockout circuit output of the output of power consumption reference circuit
The low enable signal of signal, under-voltage locking；The grid of described power adjustment pipe is connected with the output end of described error amplifier,
The source electrode connection power supply of described power adjustment pipe, the drain electrode of described power adjustment pipe is configured as low pressure difference linear voltage regulator
The output end of circuit, and be grounded by divider resistance of connecting, described supplement electric capacity one end and described power adjusts pipe
Drain electrode connection, the other end is connected to the input of error amplifier reference voltage signal.
5. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 4, it is characterised in that described error amplifier
It is holohedral symmetry operational transconductance amplifier.
6. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 4, it is characterised in that described low pressure difference linearity
Voltage regulator circuit also includes a load capacitance, and described load capacitance one end connects with the output end of low differential voltage linear voltage stabilizer circuit
Connect, other end ground connection；One load resistance, described load resistance one end connects with the output end of low differential voltage linear voltage stabilizer circuit
Connect, other end ground connection.
7. low-power consumption low pressure difference linear voltage regulator system as claimed in claim 6, it is characterised in that described load capacitance is
Ceramic condenser.
8. low-power consumption low pressure difference linear voltage regulator system as claimed in claims 6 or 7, it is characterised in that described load electricity
The capacity of appearance is 1 microfarad.
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| CN201611218141.6A CN106708151B (en) | 2016-12-26 | 2016-12-26 | A kind of low-power consumption low pressure difference linear voltage regulator system |
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| CN201611218141.6A CN106708151B (en) | 2016-12-26 | 2016-12-26 | A kind of low-power consumption low pressure difference linear voltage regulator system |
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| CN109274362A (en) * | 2018-12-03 | 2019-01-25 | 上海艾为电子技术股份有限公司 | Control circuit |
| CN109947168A (en) * | 2019-03-25 | 2019-06-28 | 厦门科塔电子有限公司 | A kind of low noise low differential voltage linear voltage stabilizer circuit |
| WO2020093268A1 (en) * | 2018-11-07 | 2020-05-14 | 北京比特大陆科技有限公司 | Low-dropout linear voltage-stabilizing circuit and electronic device |
| CN111669136A (en) * | 2019-03-07 | 2020-09-15 | 雅特力科技(重庆)有限公司 | Multi-stage amplifier with stabilizing circuit |
| CN115509286A (en) * | 2021-06-07 | 2022-12-23 | 圣邦微电子（北京）股份有限公司 | Undervoltage locking circuit |
| CN116169637A (en) * | 2023-04-06 | 2023-05-26 | 江苏帝奥微电子股份有限公司 | Low-power consumption undervoltage locking protection circuit suitable for high-voltage LDO |
| CN116880633A (en) * | 2023-07-10 | 2023-10-13 | 深圳飞渡微电子有限公司 | Low-dropout linear voltage regulator circuit capable of improving power supply voltage rejection ratio |
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| CN106708151B (en) | 2018-02-06 |
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