CN111669136A

CN111669136A - Multi-stage amplifier with stabilizing circuit

Info

Publication number: CN111669136A
Application number: CN201910171032.0A
Authority: CN
Inventors: 王正香; 王海涛; 张文龙
Original assignee: Yateli Technology Chongqing Co ltd
Current assignee: Yateli Technology Chongqing Co ltd
Priority date: 2019-03-07
Filing date: 2019-03-07
Publication date: 2020-09-15
Anticipated expiration: 2039-03-07
Also published as: CN111669136B

Abstract

The invention discloses a multistage amplifier, comprising: the amplifier comprises a first amplification stage, a second amplification stage and a stabilizing circuit. The first amplifier stage has a differential pair for receiving an input signal and generating a first output signal therefrom. The second amplifier stage is coupled to the output terminal of the first amplifier stage, and is configured to receive the first output signal and generate a second output signal accordingly. The stabilizing circuit includes at least one transistor, and the transistors in the stabilizing circuit are respectively coupled to the output terminal of the second amplifier stage and the common terminal of the differential pair, wherein the transistors in the stabilizing circuit have different conduction types from the transistors in the differential pair.

Description

Multi-stage amplifier with stabilizing circuit

Technical Field

The present invention relates to a multi-stage amplifier circuit, and more particularly, to a stabilizing circuit for use in a two-stage or multi-stage amplifier to solve stability problems caused by a light load, and a related multi-stage amplifier.

Background

In analog circuits such as Low dropout regulators (Low drop out regulators) or buffers, a two-stage amplifier circuit architecture is often used. However, in the architecture of the two-stage amplification circuit, there is often a problem of stability. This problem is mainly caused by the light and heavy load variations. In the case of light load, the non-dominant pole (second pole) formed at the output terminal of the second amplification stage in the two-stage amplification circuit is close to the dominant pole (first pole) formed at the output terminal of the first amplification stage, and if the first pole and the second pole are too close to each other or overlap with each other, oscillation of the system may be induced.

One possible solution to this problem is to add a load current or resistance at the output of the second amplifier stage so that the second pole can be moved away from the gain-bandwidth product (GBW) to increase the phase margin (phase margin). However, such an approach is not conducive to low power designs because the load current or resistance typically adds additional power consumption. Therefore, an innovative design is required to solve the stability problem of the two-stage amplifier circuit.

Disclosure of Invention

In order to solve the above problems, the present invention provides a stabilizing circuit for increasing the load of the output terminal of the output two-stage/multi-stage amplifier, thereby increasing the phase margin and solving the instability problem of the two-stage/multi-stage amplifier under the light load condition. Also, the stabilizing circuit of the present invention uses much lower power consumption than that required in the prior art stabilization technique (using load current or resistance). The stabilizing circuit of the invention is biased by the common terminal of the differential pair in the first amplifying stage of the multi-stage amplifier, so that no additional biasing circuit is needed to be arranged, and additional power consumption is caused. Furthermore, the two-stage/multi-stage amplifier of the invention has unity gain feedback (unity gain feedback), so that the stabilizing circuit inherits the driving capability of the differential pair in the first amplifying stage, and a certain phase margin can be improved under lower power consumption.

An embodiment of the present invention provides a multi-stage amplifier. The multistage amplifier includes: the amplifier comprises a first amplification stage, a second amplification stage and a stabilizing circuit. The first amplifier stage has a differential pair for receiving an input signal and generating a first output signal therefrom. The second amplifier stage is coupled to the output terminal of the first amplifier stage, and is configured to receive the first output signal and generate a second output signal accordingly. The stabilizing circuit comprises at least one transistor, and the transistors in the stabilizing circuit are respectively coupled to the output end of the second amplifying stage and the common end of the differential pair, wherein the conduction type of the transistors in the stabilizing circuit is different from that of the transistors in the differential pair.

Drawings

Fig. 1 is a circuit diagram of a first embodiment of the multistage amplifier of the present invention.

Fig. 2 is a circuit diagram of a second embodiment of the multistage amplifier of the present invention.

Fig. 3 is a circuit diagram of a third embodiment of the multistage amplifier of the present invention.

Fig. 4 is a circuit diagram of a fourth embodiment of the multistage amplifier of the present invention.

Wherein the reference numerals are as follows:

100. 300, 400 multistage amplifier

200 load

110. 310 first amplification stage

112 differential pair

120. 320, 420 second amplification stage

130. 330, 430, 115 stabilizing circuit

140. 340, 440 compensation circuit

101. 301, 401 bias current

103. 104, 105, 106, 122, 132, transistors

303、304、322、332、403、404、

405、406、422、432

CC. CL capacitor

RL resistance

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the invention to the reader. However, those skilled in the art will understand how to implement the invention without one or more of the specific details, or with other methods or elements or materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the invention. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics described above may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a circuit diagram of an embodiment of a multi-stage amplifier according to the present invention. As shown, the multi-stage amplifier 100 includes a first amplifier stage 110, a second amplifier stage 120, and a stabilizer circuit 130. It is noted that in other embodiments of the present invention, the multi-stage amplifier may comprise more amplification stages, for example, one or more amplification stages may be provided before the first amplification stage 110. Thus, the two amplifier stages shown in the figures are not the only implementation of the multi-stage amplifier of the present invention.

The first amplifier stage 110 mainly comprises a differential pair of N-

type mosfets

103 and 104. The differential pair 112 of

transistors

103 and 104 is used for receiving the input signal VREF and the second output signal VOUT at the output terminal of the second amplifier stage 120, thereby generating the first output signal VO 1. The non-inverting input terminal (i.e., the gate of the transistor 103) of the first amplification stage 110 is configured to receive the input signal VREF, and the inverting input terminal (i.e., the gate of the transistor 104) of the first amplification stage 110 is coupled to the output terminal of the second amplification stage 120 to receive the second output signal VOUT.

Furthermore, the first amplification stage 110 further includes P-

type mosfets

105 and 106, and a current source 101. The second amplification stage 120 is used for providing current to the load 200, and generates the second output signal VOUT of the multi-stage amplifier 100 based on the first output signal VO1 outputted from the first amplification stage 110. In a preferred embodiment, the second amplification stage 120 is mainly composed of a P-type metal oxide semiconductor field effect transistor 122 as a power element (power element). In addition, in a specific embodiment, the transistor 122 of the second amplification stage 120 is further connected to a compensation circuit 140 for performing miller compensation (millecrompensation), and the compensation circuit 140 includes at least a capacitor CC, thereby improving the stability of the system.

The stabilizing circuit 130 is used to add an extra load to the output of the second amplifier stage 120, so that the second pole in the system can be far from the first pole, and the phase margin can be increased. In a preferred embodiment, the stabilizing circuit 130 is mainly composed of a P-type MOSFET 132. The gate of the transistor 132 is coupled to a common terminal (common terminal)102 of the

differential pair

103 and 104, which may be a common source terminal. And the drain of transistor 132 is coupled to ground. Since the voltage on the common source terminal 102 of the differential pairs 103 and 104 is relatively stable, the P-type mosfet 132 in the stabilizing circuit 130 can be well biased. In addition, the common source terminal 102 of the

differential pair

103 and 104 is used to bias the P-type mosfet 132, so that an additional bias circuit can be omitted, and additional power consumption of the system can be avoided.

Furthermore, since the multi-stage amplifier 100 forms a unit gain feedback (unity gain feedback) configuration, the gate-source voltage VGS of the P-type mosfet 132 is substantially the same as the gate-source voltage VGS of the

transistors

103 and 104 in the differential pair, and in the same process, the P-type mosfet 132 and the N-

type mosfets

103 and 104 can have substantially the same threshold voltage VTH, so that the overdrive voltages (VGS-VTH) of the P-type mosfet 132 and the N-

type mosfets

103 and 104 are substantially the same. Since the second pole is located relative to the transconductance (gm) of the pmos fet 132, the transconductance gm is generally equal to (2 x Io)/((VGS-VTH)) where Io is the current flowing through the transistor 132. Furthermore, the larger the transconductance of the P-type mosfet 132, the farther the second pole may be from the first pole. The driving voltages of the P-type mosfet 132 and the N-

type mosfets

103 and 104 are substantially the same, and therefore, the P-type mosfet has a higher transconductance (the driving voltage of the general input differential pair transistor is designed to be smaller, and therefore, the overdrive voltage (VGS-VTH) is lower, so that the stabilizing circuit 130 only needs lower power consumption to increase a certain phase margin.

It should be noted that although the second amplifier stage 120 and the stabilizing circuit 130 are respectively formed by a single transistor in the above description, in other embodiments of the present invention, the second amplifier stage 120 and the stabilizing circuit 130 may include one or more active and passive components to assist or enhance the performance thereof.

Fig. 2 depicts a circuit diagram of another embodiment of the inventive multi-stage amplifier. The first amplification stage 110 of the embodiment is an Operational Amplifier (Operational Amplifier) and mainly includes a differential pair composed of N-

type mosfets

103 and 104. In this embodiment, the configuration and connection of the stabilizing circuit 130 are the same as those of the embodiment shown in fig. 1, so that the same stabilizing effect can be achieved.

In addition, the present invention can also be implemented using transistors of different conduction types. For example, the

multi-stage amplifiers

300 and 400 of fig. 3 and 4 employ nfets 332 and 432, respectively, as the main components of the

stabilization circuits

330 and 430, and the differential pair of

pfets

303, 304 and 403, 404 in the first amplifier stage. In the connection and configuration, the

multi-stage amplifiers

300 and 400 also have unity gain feedback, so as to improve the transconductance of the

stabilization circuits

330 and 430, and the N-

type mosfets

332 and 432 are also biased by the common source terminal of the differential pair, so as to achieve excellent stabilization effect on the basis of lower energy consumption.

It is worth mentioning that in the prior art, the second pole is usually far away from GBW by increasing the load current or resistance at the output of the second amplifier stage. However, this technical approach has significant drawbacks. Since the transconductance of the load current or resistance is substantially lower than that of the stabilizing

circuit

130, 330, 430 of the present invention, and thus is relatively undesirable in terms of energy utilization, higher power consumption is required to achieve the stabilizing effect consistent with the present invention, and low power consumption design is not facilitated.

To summarize, the stabilizing circuit of the present invention uses the common terminal of the differential pair in the first amplifier stage for biasing, so that no additional biasing circuit is required, thereby avoiding additional power consumption. Furthermore, since the

multi-stage amplifiers

100, 300, 400 have unity gain, the gate-source voltage VGS of the

transistors

132, 332, 432 in the stabilizing

circuits

130, 330, 430 is substantially duplicated to the gate-source voltage VGS of the differential pairs 103 and 104, 303 and 304, 403 and 404, so that the stabilizing circuits themselves are not affected by the load, and have better driving capability, thereby improving a certain phase margin with lower power consumption. Therefore, the two-stage/multi-stage amplifier with high stability and low power consumption can be well realized by the stabilizing circuit provided by the invention.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A multi-stage amplifier, comprising:

a first amplifier stage having a differential pair for receiving an input signal and generating a first output signal therefrom;

a second amplifier stage, coupled to an output of the first amplifier stage, for receiving the first output signal and generating a second output signal accordingly; and

and a stabilizing circuit including at least one transistor, wherein the transistor in the stabilizing circuit is coupled to the output terminal of the second amplifier stage and the common terminal of the differential pair, and the conduction type of the transistor in the stabilizing circuit is different from that of the transistors in the differential pair.

2. The multi-stage amplifier of claim 1, wherein a gate of the transistor in the stabilization circuit is coupled to a common source terminal of the differential pair.

3. The multi-stage amplifier of claim 1, wherein the drain of the transistor in the stabilization circuit is coupled to ground or a power supply terminal.

4. The multi-stage amplifier of claim 1, wherein a source of the transistor in the stabilization circuit is coupled to the output of the second amplification stage.

5. The multi-stage amplifier of claim 1, wherein the transistors in the stabilization circuit are P-type mosfets and the transistors in the differential pair are N-type mosfets.

6. The multi-stage amplifier of claim 1, wherein the transistors in the stabilization circuit are N-type mosfets and the transistors in the differential pair are P-type mosfets.

7. The multi-stage amplifier of claim 1, wherein the second amplifier stage comprises at least one transistor having a conduction type identical to that of the transistor in the stabilization circuit.

8. The multi-stage amplifier of claim 7, further comprising a compensation circuit coupled between the gate and the drain of the transistor of the second amplification stage.

9. The multi-stage amplifier of claim 1, wherein the multi-stage amplifier has unity gain feedback.

10. The multi-stage amplifier of claim 1, wherein an inverting input of the first amplification stage is coupled to the output of the second amplification stage.

11. The multi-stage amplifier of claim 1, wherein the gate-to-source voltages of the transistors in the stabilization circuit are the same as the gate-to-source voltages of the transistors of the differential pair in the first amplification stage.