CN112987841A - Novel linear voltage stabilizer - Google Patents

Novel linear voltage stabilizer Download PDF

Info

Publication number
CN112987841A
CN112987841A CN202110178313.6A CN202110178313A CN112987841A CN 112987841 A CN112987841 A CN 112987841A CN 202110178313 A CN202110178313 A CN 202110178313A CN 112987841 A CN112987841 A CN 112987841A
Authority
CN
China
Prior art keywords
tube
nmos tube
nmos
electrode
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110178313.6A
Other languages
Chinese (zh)
Inventor
蔡胜凯
李响
董渊
庄健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wuxi Indie Microelectronics Technology Co Ltd
Original Assignee
Wuxi Indie Microelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wuxi Indie Microelectronics Technology Co Ltd filed Critical Wuxi Indie Microelectronics Technology Co Ltd
Priority to CN202110178313.6A priority Critical patent/CN112987841A/en
Publication of CN112987841A publication Critical patent/CN112987841A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a novel linear voltage stabilizer, which relates to the technical field of voltage stabilizers, wherein the output end of a first-stage operational amplifier circuit in the novel linear voltage stabilizer is connected with the grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube and used as a main pole point, the drain electrode of the first NMOS tube is connected with a working power supply, the source electrode of the first NMOS tube is grounded sequentially through a first resistor and a second resistor, the source electrode of the first NMOS tube leads out a voltage output end and is used as a secondary pole point to be positively correlated with a load, the voltage output end is connected with an on-chip capacitor and the load, and the common end of the first resistor and the second resistor leads out a; the dynamic zero point generated by the first capacitor, the third resistor and the second NMOS tube can be changed based on the positive correlation between the output current sampled by the dynamic compensation circuit and the load, the dynamic zero point changed along with the load can realize dynamic compensation on the secondary pole point, and the capacitors in the chip are dozens of pf to several nf, so that the wide load has good stability.

Description

Novel linear voltage stabilizer
Technical Field
The invention relates to the technical field of voltage regulators, in particular to a novel linear voltage regulator.
Background
In today's SOC systems, multiple LDOs (linear regulators) are usually required to supply power, and in order to compensate for loop stability and provide better load transient response, a capacitor of about 0.1uf to 10uf is usually suspended at the output of the conventional LDO, which undoubtedly increases the cost and complexity of the system. Therefore, in recent years, LDO without off-chip capacitance has been proposed, but compensation is a difficulty, because SOC system itself also has parasitic capacitance of hundreds pf to tens nf, and it is difficult for conventional compensation to maintain stability in such a wide range.
The circuit structure of the conventional N-type LDO without off-chip capacitor is shown in fig. 1, Cout is an on-chip capacitor (tens to one hundred pf), a main pole P0 is disposed at the output V _ EA of the first stage operational amplifier circuit (dashed box), a secondary pole P1 is at VOUT and increases with the increase of load current, a compensation zero is generated by R0 and C1 as a fixed zero to compensate P1, and P1 increases with the increase of load Iload, so that the zero is difficult to compensate P1 accurately, for example, the zero is disposed at a higher frequency to compensate P1 with a higher frequency when the load is heavy, and when the load is very light, P1 is lowered to a very low frequency, the fixed zero does not play a role of compensation, and the system will be unstable.
Disclosure of Invention
The inventor provides a novel linear voltage regulator aiming at the problems and the technical requirements, and the technical scheme of the invention is as follows:
a novel linear voltage stabilizer is characterized in that the input end of a first-stage operational amplifier circuit is connected with a working power supply, the output end of the first-stage operational amplifier circuit is connected with a grid electrode of a first NMOS (N-channel metal oxide semiconductor) tube, a drain electrode of the first NMOS tube is connected with the working power supply, a source electrode of the first NMOS tube is grounded sequentially through a first resistor and a second resistor, the source electrode of the first NMOS tube is also led out to serve as a voltage output end of the novel linear voltage stabilizer, the voltage output end is connected with an on-chip capacitor and a load, and a feedback voltage end is led out from the common end of the;
the output end of the first-stage operational amplifier circuit is grounded sequentially through a first capacitor and a third resistor, the common end of the first capacitor and the third resistor is connected with the drain electrode of a second NMOS tube, the source electrode of the second NMOS tube is grounded, the dynamic compensation circuit samples the output current of the voltage output end and generates a corresponding compensation signal to be input into the grid electrode of the second NMOS tube, the on-resistance of the second NMOS tube corresponds to the output current of the voltage output end, and the output current of the voltage output end is positively correlated with the load;
the output end of the first-stage operational amplifier circuit generates a dominant pole, the voltage output end generates a secondary pole, and the size of the secondary pole is positively correlated with the load; the second NMOS tube, the first capacitor and the third resistor generate a dynamic zero compensation secondary pole, and the size of the dynamic zero corresponds to the on-resistance of the second NMOS tube and is positively correlated with the load.
The further technical proposal is that the size of the dynamic zero point is
Figure BDA0002941436790000021
Wherein, RdsonN2Is the on-resistance of the second NMOS transistor
Figure BDA0002941436790000022
un is the electron mobility, Cox is the gate oxide capacitance per unit area,
Figure BDA0002941436790000023
is the width-to-length ratio of the second NMOS transistor, VGSN2Is the gate-source voltage, Vth, of the second NMOS transistorN2The threshold voltage of the second NMOS transistor, the gate-source voltage of the second NMOS transistor is related to the compensation signal of the gate and positively related to the load, the on-resistance of the second NMOS transistor is negatively related to the load, R3 is the resistance of the third resistor, C1 is the capacitance of the first capacitor, RdsonN2| | R3 denotes RdsonN2Resistance in parallel with R3.
The dynamic compensation circuit comprises a third NMOS tube, a fourth NMOS tube, a first PMOS tube and a second PMOS tube, wherein the grid electrode of the third NMOS tube is connected with the grid electrode of the first NMOS tube, the source electrode of the third NMOS tube is connected with the voltage output end, the drain electrode of the third NMOS tube is connected with the drain electrode of the first PMOS tube, the grid electrode of the first PMOS tube is connected with the grid electrode of the second PMOS tube and is connected with the drain electrode of the first PMOS tube, the source electrode of the first PMOS tube and the source electrode of the second PMOS tube are both connected with a working power supply, the drain electrode of the second PMOS tube is connected with the drain electrode and the grid electrode of the fourth NMOS tube, the source electrode of the fourth NMOS tube is grounded, and the grid electrode of the fourth NMOS tube is also connected with the.
In the first-stage operational amplifier circuit, a source electrode of a third PMOS tube is connected with a working power supply, a drain electrode of the third PMOS tube is grounded through a reference bias current source, and a grid electrode of the third PMOS tube is connected with the drain electrode and generates bias voltage; the source electrode of the fourth PMOS tube is connected with a working power supply, the drain electrode of the fourth PMOS tube is connected with the drain electrode and the grid electrode of the fifth NMOS tube, the source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is also connected with the grid electrode of the sixth NMOS tube, the source electrode of the sixth NMOS tube is grounded, the drain electrode of the sixth NMOS tube is connected with the drain electrode of the ninth PMOS tube, the source electrode of the ninth PMOS tube is connected with the working power supply, and the drain electrode of the ninth PMOS tube is led out to serve;
the source electrode of the fifth PMOS tube is connected with a working power supply, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is grounded;
the source electrode of the sixth PMOS tube is connected with a working power supply, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the tenth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the source electrode of the eighth NMOS tube is grounded;
the grid electrode of the fourth PMOS tube is connected with the grid electrode and the drain electrode of the seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with a working power supply, the drain electrode of the seventh PMOS tube is connected with the drain electrode of the eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of the eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the working power supply, the drain electrode of the eighth PMOS tube is connected with the drain electrode of the twelfth NMOS tube, and the source electrode of the twelfth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are controlled by bias voltage, the grid electrode of the seventh NMOS tube is connected to the drain electrode of the ninth NMOS tube, and the grid electrode of the eighth NMOS tube is connected to the drain electrode of the tenth NMOS tube; the ninth NMOS tube is connected with the grid electrode of the eleventh NMOS tube and is connected with the feedback voltage end, and the tenth NMOS tube is connected with the grid electrode of the twelfth NMOS tube and is connected with the reference voltage end.
When the load jumps and becomes large, the voltage of the voltage output end drops, the voltage of the feedback voltage end drops, the current of the twelfth NMOS tube is far larger than the current provided by the reference bias current source, and the first-stage operational amplifier circuit outputs and drives the first NMOS tube to enable the voltage of the voltage output end to rise;
when the load jumps and becomes small, the voltage of the voltage output end rises, the voltage of the feedback voltage end rises, the current of the eleventh NMOS tube is far larger than the current provided by the reference bias current source, and the first-stage operational amplifier circuit outputs and drives the first NMOS tube to enable the voltage of the voltage output end to fall.
The further technical scheme is that the first-stage operational amplifier circuit further comprises a tenth PMOS tube and an eleventh PMOS tube, wherein the grid electrode of the seventh NMOS tube is connected with the drain electrode and the grid electrode of the tenth PMOS tube, and the source electrode of the tenth PMOS tube is connected with the drain electrode of the ninth NMOS tube; the grid electrode of the eighth NMOS tube is connected with the drain electrode and the grid electrode of the eleventh PMOS tube, and the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube.
The beneficial technical effects of the invention are as follows:
the application discloses novel linear voltage stabilizer is no off-chip capacitance N type power tube structure, has dynamic zero compensation function, and has fine stability in output capacitance tens pf to several nf, wide load. The output current of the first-stage operational amplifier circuit with the improved design is not limited by the bias current, and the first-stage operational amplifier circuit has a larger output slew rate under the condition of smaller static bias current, so that the response speed of the system is improved. And the first-stage operational amplifier circuit can have a higher input voltage range and an output voltage range.
Drawings
Fig. 1 is a circuit configuration diagram of a conventional linear regulator.
Fig. 2 is a circuit configuration diagram of the novel linear regulator of the present application.
Fig. 3 is another circuit configuration diagram of the novel linear regulator of the present application.
Fig. 4 is another circuit configuration diagram of the novel linear regulator of the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses novel linear voltage regulator please refer to fig. 2, in this novel linear voltage regulator, the input of first order operational amplifier circuit is connected working power supply VDD, output V _ EA is connected the grid of first NMOS pipe N1, the drain electrode of first NMOS pipe N1 is connected working power supply VDD, the source electrode loops through first resistance R1 and second resistance R2 ground connection. The source electrode of the first NMOS tube N1 is also led out to be used as a voltage output end VOUT of the novel linear voltage stabilizer, the voltage output end VOUT is connected with an on-chip capacitor Cout and a load Iload, and the on-chip capacitor Cout is generally dozens to one hundred pf. The common end of the first resistor R1 and the second resistor R2 leads a feedback voltage end VFB to the first-stage operational amplifier circuit.
The output end V _ EA of the first-stage operational amplifier circuit is further grounded through a first capacitor C1 and a third resistor R3 in sequence, the common end of the first capacitor C1 and the third resistor R3 is connected with the drain electrode of the second NMOS transistor N2, and the source electrode of the second NMOS transistor N2 is grounded. The dynamic compensation circuit samples the output current of the voltage output terminal VOUT and generates a corresponding compensation signal to be input to the gate of the second NMOS transistor N2.
On-resistance Rdson of second NMOS transistor N2N2The output current of the voltage output terminal VOUT corresponds to the magnitude of the output current of the voltage output terminal VOUT, and the output current of the voltage output terminal VOUT is positively correlated to the load Iload, so that the on-resistance Rdson of the second NMOS transistor N2N2Corresponding to the load Iload. Specifically, the on-resistance Rdson of the second NMOS transistor N2N2And the gate-source voltage VGS of the second NMOS transistor N2N2Negative correlation, and VGSN2The magnitude of the compensation signal input by the gate of N2 is positively correlated with the magnitude of the output current of the voltage output terminal VOUT, and therefore the on-resistance Rdson of the second NMOS transistor N2N2Negatively correlated with the load Iload. Specifically, the on-resistance of the second NMOS transistor N2
Figure BDA0002941436790000041
un is the electron mobility, Cox is the gate oxide capacitance per unit area,
Figure BDA0002941436790000042
the width-to-length ratio of the second NMOS transistor N2 is adjustable. VGSN2Is the gate-source voltage, Vth, of the second NMOS transistor N2N2Is the threshold voltage of the second NMOS transistor N2, which is generally considered a fixed, known quantity parameter. From this it can be seen that RdsonN2And VGSN2The negative correlation relationship of (c).
In the circuit shown in fig. 2, the output terminal V _ EA of the first stage operational amplifier generates a dominant pole P0, the magnitude of the dominant pole P0, the first capacitance C1 and the output impedance r of the first stage operational amplifierV_EACorrelation, can be expressed as
Figure BDA0002941436790000043
It follows that the dominant pole is a fixed value.
The voltage output end VOUT generates a secondary pole P1, N2, C1 and R3 and the dynamic compensation circuit form a compensation network of the LDO, and the output impedance is very low due to the adoption of an N-type power tube
Figure BDA0002941436790000051
gm is the transconductance of N1, so the secondary pole P1 can be expressed as
Figure BDA0002941436790000052
Cout is the magnitude of the on-chip capacitance, and thus it can be seen that the magnitude of the pole P1 is positively correlated to the load Iload. When the load Iload is lightly loaded, the secondary pole P1 is low and falls within the bandwidth, so that the phase margin is reduced and the system starts to oscillate, and therefore a zero is needed to compensate for the secondary pole P1.
In the present application, the second NMOS transistor N2, the first capacitor C1, and the third resistor R3 generate a dynamic zero compensation secondary pole P1, and the magnitude zero of the dynamic zero corresponds to the on-resistance of the second NMOS transistor N2, specifically, is inversely related to the on-resistance of N2. In particular, as can be seen from the structure of fig. 2, the magnitude zero of the dynamic zero point is
Figure BDA0002941436790000053
RdsonN2| | R3 denotes the on-resistance Rdson of N2N2Parallel resistance to the resistance R3 of the third resistor, from which the on-resistance Rdson of zero and N2 can be seenN2Is negative in betweenAnd (4) correlation relation.
Since the on-resistance of N2 is negatively correlated with load Iload, the magnitude zero of the dynamic zero is positively correlated with load Iload. Therefore, when the load Iload becomes smaller, the positive correlation between the secondary pole P1 and the load Iload becomes smaller, and the positive correlation between zero and the load Iload also becomes smaller to compensate the pole P1. When the load Iload becomes larger, the positive correlation between the secondary point P1 and the load Iload becomes larger, and the positive correlation between the zero and the load Iload becomes larger at this time to compensate the secondary point P1. Therefore, dynamic zero compensation is realized, and verified that the transient response speed and stability are good in a wide load when the on-chip capacitor Cout is dozens of pf to several nf.
The structure of the dynamic compensation circuit in this application is shown in fig. 2, and includes a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P1 and a second PMOS transistor P2, a gate of the third NMOS transistor N3 is connected to a gate of the first NMOS transistor N1, a source is connected to the voltage output terminal VOUT, and a drain is connected to a drain of the first PMOS transistor P1, a gate of the first PMOS transistor P1 is connected to a gate of the second PMOS transistor P2 and to a drain of the first PMOS transistor P1, a source of the first PMOS transistor P1 and a source of the second PMOS transistor P2 are both connected to the working power VDD, a drain of the second PMOS transistor P2 is connected to a drain and a gate of the fourth NMOS transistor N4, a source of the fourth NMOS transistor N4 is grounded, and a gate of the fourth NMOS transistor N4 is further connected to a gate of the second NMOS transistor N2. Then P2 may sample the output current at the voltage output VOUT and the sampled output current flows into N4 to generate the corresponding gate-source voltage input N2 for control.
Referring to fig. 3, in the first stage operational amplifier circuit of the present application, a rail-to-rail output amplifier structure is adopted, in the first stage operational amplifier circuit, a source of a third PMOS transistor P3 is connected to a working power VDD, a drain of the third PMOS transistor P3 is grounded through a reference bias current source IB, and a gate of the third PMOS transistor P3 is connected to the drain of the third PMOS transistor P3578 and generates a bias voltage VBP, which is generated after the reference bias current source IB flows through the third PMOS transistor P3. The source electrode of the fourth PMOS transistor P4 is connected to the operating power VDD, the drain electrode is connected to the drain electrode and the gate electrode of the fifth NMOS transistor N5, the source electrode of the fifth NMOS transistor N5 is grounded, and the gate electrode is further connected to the gate electrode of the sixth NMOS transistor N6. The source of the sixth NMOS transistor N6 is grounded, and the drain is connected to the drain of the ninth PMOS transistor P9. The source electrode of the ninth PMOS tube P9 is connected with the working power supply VDD, and the drain electrode of the ninth PMOS tube P9 is led out to be used as the output end V _ EA of the first-stage operational amplifier circuit.
The source electrode of the fifth PMOS tube P5 is connected with a working power supply VDD, the drain electrode is connected with the drain electrode of the ninth NMOS tube N9, the source electrode of the ninth NMOS tube N9 is connected with the drain electrode of the seventh NMOS tube N7, and the source electrode of the seventh NMOS tube N7 is grounded.
The source electrode of the sixth PMOS tube P6 is connected with the working power supply VDD, the drain electrode is connected with the drain electrode of the tenth NMOS tube N10, the source electrode of the tenth NMOS tube N10 is connected with the drain electrode of the eighth NMOS tube N8, and the source electrode of the eighth NMOS tube N8 is grounded.
The grid electrode of the fourth PMOS tube P4 is connected with the grid electrode and the drain electrode of the seventh PMOS tube P7, the source electrode of the seventh PMOS tube P7 is connected with the working power supply VDD, and the drain electrode of the seventh PMOS tube P7 is connected with the drain electrode of the eleventh NMOS tube N11. The source of the eleventh NMOS transistor N11 is connected to the drain of the eighth NMOS transistor N8.
The gate of the ninth PMOS transistor P9 is connected to the gate and the drain of the eighth PMOS transistor P8, and the source of the eighth PMOS transistor P8 is connected to the operating power supply VDD. The drain of the eighth PMOS transistor P8 is connected to the drain of the twelfth NMOS transistor N12, and the source of the twelfth NMOS transistor N12 is connected to the drain of the seventh NMOS transistor N7.
The fifth PMOS transistor P5 and the sixth PMOS transistor P6 are controlled by bias voltage, the gate of the seventh NMOS transistor N7 is connected to the drain of the ninth NMOS transistor N9, and the gate of the eighth NMOS transistor N8 is connected to the drain of the tenth NMOS transistor N10. The ninth NMOS transistor N9 is connected to the gate of the eleventh NMOS transistor N11 and to the feedback voltage terminal VFB, i.e., the common terminal of the connections R1 and R2. The tenth NMOS transistor N10 is connected to the gate of the twelfth NMOS transistor N12 and connected to the reference voltage terminal VREF, so that the voltage of the final voltage output terminal VOUT can be expressed as
Figure BDA0002941436790000061
However, the output current of the first-stage operational amplifier in the prior art shown in fig. 1 is limited by the bias current IBIAS of MN3, which results in limited output slew rate and slow transient response speed, and if the transient response is to be improved, only the bias current can be increased, which undoubtedly increases the static power consumption of the system. The output current of the first-stage operational amplifier circuit based on the structure provided by the application is not limited by the reference bias current source IB, and the first-stage operational amplifier circuit has a larger output slew rate under the condition of smaller static bias current, so that the response speed of the system is improved, and the specific introduction is as follows:
(1) when the load Iload jumps and becomes larger, the voltage of the voltage output terminal VOUT decreases, the voltage of the feedback voltage terminal VFB decreases, the current of the twelfth NMOS transistor N12 is much larger than the current provided by the reference bias current source IB, and the output of the first stage operational amplifier circuit drives the first NMOS transistor N1 to increase the voltage of the voltage output terminal VOUT.
Specifically, when the load Iload jumps from a light load to a heavy load, the voltage drop at the voltage output terminal VOUT causes the feedback voltage terminal VFB to drop by Δ V, and since the current of N9 is fixed and supplied by P5, the source of N9 also drops by Δ V. The reference voltage terminal VREF is fixed and is biased by N10, so the source terminal of N10 is kept constant. This results in the gate-source voltages of N11 and N12 being respectively decreased by Δ V and increased by Δ V, so that the current of N12 can be independent of and much larger than the reference bias current source IB, the currents of N11 and N12 are mirrored through the current mirror and finally drive the gate of N1, so that the voltage of the voltage output terminal VOUT rises and finally stabilizes, and the slew rate of the gate of N1 is greatly increased in such a way that the output current is not limited by the reference bias current source IB, thereby increasing the transient response speed of the entire LDO.
(2) When the load Iload jumps and becomes small, the voltage of the voltage output terminal VOUT rises, the voltage of the feedback voltage terminal VFB rises, the current of the eleventh NMOS transistor N11 is much larger than the current provided by the reference bias current source IB, and the first stage operational amplifier outputs the driving first NMOS transistor N1 so that the voltage of the voltage output terminal VOUT decreases.
Similar to the above case, when the load Iload jumps from a heavy load to a light load, the voltage overshoot of the voltage output terminal VOUT causes the feedback voltage terminal VFB to increase by Δ V, causing the gate-source voltages of N11 and N12 to increase by Δ V and decrease by Δ V, respectively, so that the current of N11 can be unrestricted by and much larger than the reference bias current source IB, and the currents of N11 and N12 are mirrored through the current mirror and finally drive the gate of N1, so that the voltage of the voltage output terminal VOUT decreases and finally stabilizes. Also has a higher transient response speed.
In addition, the first-stage operational amplifier circuit with the structure has a higher output voltage range of VdsatN6～(VDD-VdsatP9)，VdsatN6And VdsatP9Overdrive voltages of N6 and N9, respectively. In the configuration shown in fig. 3, VGS needs to be satisfied for the input range to operate N9 in the saturation regionN7>VFB-VthN9For N7 to work in saturation region, VFB-VGS needs to be satisfiedN9>VGSN7-VthN7From the above two equations, it can be seen that in the circuit structure shown in FIG. 3, the input range of the input operational amplifier is VGSN 7-VthN7+VGSN9＜VFB＜VGSN7+VthN9。
Further based on the circuit structure of fig. 3, referring to fig. 4, the first-stage operational amplifier circuit of the present application further includes a tenth PMOS transistor P10 and an eleventh PMOS transistor P11, so that N7 is not directly connected to the drain of N9, N8 is not directly connected to the drain of N10, but: the grid electrode of the seventh NMOS transistor N7 is connected with the drain electrode and the grid electrode of the tenth PMOS transistor P10, and the source electrode of the tenth PMOS transistor P10 is connected with the drain electrode of the ninth NMOS transistor N9; the gate of the eighth NMOS transistor N8 is connected to the drain and gate of the eleventh PMOS transistor P11, and the source of the eleventh PMOS transistor P11 is connected to the drain of the tenth NMOS transistor N10.
The addition of P10 and P11 in fig. 4 expands the input voltage range relative to fig. 3, where VGS is required to be satisfied in fig. 4 to operate N9 in the saturation regionN7+VGSP10>VFB-VthN9For N7 to work in saturation region, VFB-VGS needs to be satisfiedN9>VGSN7-VthN7From the above two equations, it can be found that in the circuit structure shown in fig. 4, the input range of the input operational amplifier is VGSN7-VthN7+VGSN9<VFB<VGSN7+VGSP10+VthN9The upper range of VFB is VGS larger than the input range of FIG. 3P10. Wherein, VGSN7Is the gate-source voltage, Vth, of N7N7Is the threshold voltage of N7, VGSN9Is the gate-source voltage, Vth, of N9N9Is the threshold voltage of N9, VGSP10Is the gate-source voltage of P10.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.

Claims (6)

1. A novel linear voltage stabilizer is characterized in that in the novel linear voltage stabilizer, the input end of a first-stage operational amplifier circuit is connected with a working power supply, the output end of the first-stage operational amplifier circuit is connected with a grid electrode of a first NMOS tube, a drain electrode of the first NMOS tube is connected with the working power supply, a source electrode of the first NMOS tube is grounded sequentially through a first resistor and a second resistor, the source electrode of the first NMOS tube is also led out to serve as a voltage output end of the novel linear voltage stabilizer, an on-chip capacitor and a load are connected at the voltage output end, and a feedback voltage end is led out from the common end of the first resistor and the second resistor to the first-stage;
the output end of the first-stage operational amplifier circuit is grounded sequentially through a first capacitor and a third resistor, the common end of the first capacitor and the third resistor is connected with the drain electrode of a second NMOS tube, the source electrode of the second NMOS tube is grounded, a dynamic compensation circuit samples the output current of the voltage output end and generates a corresponding compensation signal to be input into the grid electrode of the second NMOS tube, the on-resistance of the second NMOS tube corresponds to the output current of the voltage output end, and the output current of the voltage output end is positively correlated with the load;
the output end of the first-stage operational amplifier circuit generates a main pole, the voltage output end generates a secondary pole, and the size of the secondary pole is positively correlated with the load; the second NMOS tube, the first capacitor and the third resistor generate dynamic zero compensation for the secondary pole, and the size of the dynamic zero corresponds to the on-resistance of the second NMOS tube and is positively correlated with the load.
2. The novel linear regulator according to claim 1,
the size of the dynamic zero point is
Figure FDA0002941436780000011
Wherein, RdsonN2Is the on-resistance of the second NMOS transistor
Figure FDA0002941436780000012
un is the electron mobility, Cox is the gate oxide capacitance per unit area,
Figure FDA0002941436780000013
is the width-to-length ratio of the second NMOS transistor, VGSN2Is the gate-source voltage, Vth, of the second NMOS transistorN2The threshold voltage of the second NMOS transistor, the gate-source voltage of the second NMOS transistor is related to the compensation signal of the gate and positively related to the load, the on-resistance of the second NMOS transistor is negatively related to the load, R3 is the resistance of the third resistor, C1 is the capacitance of the first capacitor, RdsonN2| | R3 denotes RdsonN2Resistance in parallel with R3.
3. The novel linear voltage regulator according to claim 1, wherein the dynamic compensation circuit includes a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor and a second PMOS transistor, a gate of the third NMOS transistor is connected to a gate of the first NMOS transistor, a source of the third NMOS transistor is connected to the voltage output terminal, and a drain of the third PMOS transistor is connected to a drain of the first PMOS transistor, a gate of the first PMOS transistor is connected to a gate of the second PMOS transistor and to a drain of the first PMOS transistor, a source of the first PMOS transistor and a source of the second PMOS transistor are both connected to the operating power supply, a drain of the second PMOS transistor is connected to a drain and a gate of the fourth NMOS transistor, a source of the fourth NMOS transistor is grounded, and a gate of the fourth NMOS transistor is further connected to a gate of the second NMOS transistor.
4. The novel linear voltage regulator according to any one of claims 1 to 3, wherein in the first-stage operational amplifier circuit, a source electrode of a third PMOS tube is connected with the working power supply, a drain electrode of the third PMOS tube is grounded through a reference bias current source, and a gate electrode of the third PMOS tube is connected with the drain electrode and generates a bias voltage; a source electrode of the fourth PMOS tube is connected with the working power supply, a drain electrode of the fourth PMOS tube is connected with a drain electrode and a grid electrode of the fifth NMOS tube, a source electrode of the fifth NMOS tube is grounded, the grid electrode of the fifth NMOS tube is also connected with a grid electrode of the sixth NMOS tube, a source electrode of the sixth NMOS tube is grounded, a drain electrode of the sixth NMOS tube is connected with a drain electrode of the ninth PMOS tube, a source electrode of the ninth PMOS tube is connected with the working power supply, and a drain electrode of the ninth PMOS tube is led out to be used as an output end of the;
the source electrode of the fifth PMOS tube is connected with the working power supply, the drain electrode of the fifth PMOS tube is connected with the drain electrode of the ninth NMOS tube, the source electrode of the ninth NMOS tube is connected with the drain electrode of the seventh NMOS tube, and the source electrode of the seventh NMOS tube is grounded;
the source electrode of the sixth PMOS tube is connected with the working power supply, the drain electrode of the sixth PMOS tube is connected with the drain electrode of the tenth NMOS tube, the source electrode of the tenth NMOS tube is connected with the drain electrode of the eighth NMOS tube, and the source electrode of the eighth NMOS tube is grounded;
the grid electrode of the fourth PMOS tube is connected with the grid electrode and the drain electrode of a seventh PMOS tube, the source electrode of the seventh PMOS tube is connected with the working power supply, the drain electrode of the seventh PMOS tube is connected with the drain electrode of an eleventh NMOS tube, and the source electrode of the eleventh NMOS tube is connected with the drain electrode of the eighth NMOS tube;
the grid electrode of the ninth PMOS tube is connected with the grid electrode and the drain electrode of an eighth PMOS tube, the source electrode of the eighth PMOS tube is connected with the working power supply, the drain electrode of the eighth PMOS tube is connected with the drain electrode of a twelfth NMOS tube, and the source electrode of the twelfth NMOS tube is connected with the drain electrode of the seventh NMOS tube;
the grid electrodes of the fifth PMOS tube and the sixth PMOS tube are controlled by bias voltage, the grid electrode of the seventh NMOS tube is connected to the drain electrode of the ninth NMOS tube, and the grid electrode of the eighth NMOS tube is connected to the drain electrode of the tenth NMOS tube; the ninth NMOS tube is connected with the grid electrode of the eleventh NMOS tube and connected with the feedback voltage end, and the tenth NMOS tube is connected with the grid electrode of the twelfth NMOS tube and connected with the reference voltage end.
5. The novel linear regulator according to claim 4,
when the load jumps and becomes large, the voltage of the voltage output end drops, the voltage of the feedback voltage end drops, the current of the twelfth NMOS tube is far larger than the current provided by the reference bias current source, and the first-stage operational amplifier circuit outputs and drives the first NMOS tube to enable the voltage of the voltage output end to rise;
when the load jumps and becomes small, the voltage of the voltage output end rises, the voltage of the feedback voltage end rises, the current of the eleventh NMOS tube is far larger than the current provided by the reference bias current source, and the first-stage operational amplifier circuit outputs and drives the first NMOS tube to enable the voltage of the voltage output end to fall.
6. The novel linear voltage regulator according to claim 4, wherein the first-stage operational amplifier circuit further comprises a tenth PMOS transistor and an eleventh PMOS transistor, a gate of the seventh NMOS transistor is connected to a drain and a gate of the tenth PMOS transistor, and a source of the tenth PMOS transistor is connected to a drain of the ninth NMOS transistor; the grid electrode of the eighth NMOS tube is connected with the drain electrode and the grid electrode of the eleventh PMOS tube, and the source electrode of the eleventh PMOS tube is connected with the drain electrode of the tenth NMOS tube.
CN202110178313.6A 2021-02-09 2021-02-09 Novel linear voltage stabilizer Pending CN112987841A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110178313.6A CN112987841A (en) 2021-02-09 2021-02-09 Novel linear voltage stabilizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110178313.6A CN112987841A (en) 2021-02-09 2021-02-09 Novel linear voltage stabilizer

Publications (1)

Publication Number Publication Date
CN112987841A true CN112987841A (en) 2021-06-18

Family

ID=76393847

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110178313.6A Pending CN112987841A (en) 2021-02-09 2021-02-09 Novel linear voltage stabilizer

Country Status (1)

Country Link
CN (1) CN112987841A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113760029A (en) * 2021-08-31 2021-12-07 西安电子科技大学 Novel low dropout linear regulator based on full MOS reference source
CN113970949A (en) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 High-speed linear voltage stabilizer with quick response
CN115494909A (en) * 2022-09-27 2022-12-20 青岛信芯微电子科技股份有限公司 Zero compensation circuit, chip and display device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101847028A (en) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 Dynamic compensation circuit with ultra-low power consumption and linear regulator with the same
CN201616035U (en) * 2009-04-28 2010-10-27 Bcd半导体制造有限公司 Enhanced miller compensation low dropout linear regulator
US8169203B1 (en) * 2010-11-19 2012-05-01 Nxp B.V. Low dropout regulator
CN103105883A (en) * 2011-11-11 2013-05-15 中国科学院微电子研究所 Linear voltage regulator with load detection circuit and dynamic zero compensation circuit
CN104460802A (en) * 2014-11-27 2015-03-25 电子科技大学 Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same
CN106774614A (en) * 2016-12-05 2017-05-31 电子科技大学 A kind of low pressure difference linear voltage regulator with super transconductance structure
CN107797599A (en) * 2017-10-31 2018-03-13 中国电子科技集团公司第五十八研究所 LDO circuit with dynamic compensation and fast transient response
CN109116906A (en) * 2018-10-31 2019-01-01 上海海栎创微电子有限公司 A kind of low pressure difference linear voltage regulator based on adaptive antenna zero compensation

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN201616035U (en) * 2009-04-28 2010-10-27 Bcd半导体制造有限公司 Enhanced miller compensation low dropout linear regulator
CN101847028A (en) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 Dynamic compensation circuit with ultra-low power consumption and linear regulator with the same
US8169203B1 (en) * 2010-11-19 2012-05-01 Nxp B.V. Low dropout regulator
CN103105883A (en) * 2011-11-11 2013-05-15 中国科学院微电子研究所 Linear voltage regulator with load detection circuit and dynamic zero compensation circuit
CN104460802A (en) * 2014-11-27 2015-03-25 电子科技大学 Self-adapting current multiplication circuit and low-dropout-voltage linear voltage regulator integrating same
CN106774614A (en) * 2016-12-05 2017-05-31 电子科技大学 A kind of low pressure difference linear voltage regulator with super transconductance structure
CN107797599A (en) * 2017-10-31 2018-03-13 中国电子科技集团公司第五十八研究所 LDO circuit with dynamic compensation and fast transient response
CN109116906A (en) * 2018-10-31 2019-01-01 上海海栎创微电子有限公司 A kind of low pressure difference linear voltage regulator based on adaptive antenna zero compensation

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113760029A (en) * 2021-08-31 2021-12-07 西安电子科技大学 Novel low dropout linear regulator based on full MOS reference source
CN113760029B (en) * 2021-08-31 2022-06-17 西安电子科技大学 Novel low dropout linear regulator based on full MOS reference source
CN113970949A (en) * 2021-12-27 2022-01-25 江苏长晶科技股份有限公司 High-speed linear voltage stabilizer with quick response
CN115494909A (en) * 2022-09-27 2022-12-20 青岛信芯微电子科技股份有限公司 Zero compensation circuit, chip and display device
CN115494909B (en) * 2022-09-27 2024-03-08 青岛信芯微电子科技股份有限公司 Zero compensation circuit, chip and display device

Similar Documents

Publication Publication Date Title
CN108803761B (en) LDO circuit that contains high-order temperature compensation
CN108235744B (en) Low dropout linear voltage stabilizing circuit
CN106558987B (en) Low quiescent current linear regulator circuit
US10541677B2 (en) Low output impedance, high speed and high voltage generator for use in driving a capacitive load
CN112987841A (en) Novel linear voltage stabilizer
US7656224B2 (en) Power efficient dynamically biased buffer for low drop out regulators
KR20140089814A (en) Low drop out regulator
CN110096086B (en) Voltage regulator device
JP6545692B2 (en) Buffer circuit and method
KR101238173B1 (en) A Low Dropout Regulator with High Slew Rate Current and High Unity-Gain Bandwidth
US20130307502A1 (en) Reducing power consumption in a voltage regulator
CN111176358B (en) Low-power-consumption low-dropout linear voltage regulator
US10175707B1 (en) Voltage regulator having feedback path
CN111290460B (en) Low dropout regulator with high power supply rejection ratio and rapid transient response
CN115016594B (en) Low-dropout linear voltage regulator
CN113467559B (en) Adaptive dynamic zero compensation circuit applied to LDO (low dropout regulator)
CN113721688B (en) high-PSRR high-transient-response low-dropout linear voltage regulator capable of being quickly and stably connected
CN113448372A (en) Compensation of low dropout voltage regulator
CN207731181U (en) The LDO linear voltage regulators of New-type CMOS structure
CN108052153A (en) The LDO linear voltage regulators of New-type CMOS structure
CN215376184U (en) Quick response low dropout regulator circuit
CN115390606B (en) Voltage regulator
CN116027838A (en) Low dropout linear voltage regulator, voltage stabilizing system and dynamic compensation method of pole of voltage stabilizing system
TWI548964B (en) Flipped voltage zero compensation circuit
CN114253340A (en) Frequency compensation linear voltage stabilizing circuit with zero point dynamic adjustment

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210618

RJ01 Rejection of invention patent application after publication