CN111162743B - Error amplifier and switching power supply - Google Patents

Error amplifier and switching power supply Download PDF

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Publication number
CN111162743B
CN111162743B CN201911382855.4A CN201911382855A CN111162743B CN 111162743 B CN111162743 B CN 111162743B CN 201911382855 A CN201911382855 A CN 201911382855A CN 111162743 B CN111162743 B CN 111162743B
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China
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tube
pmos
pmos tube
nmos
electrode
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CN111162743A (en
Inventor
冯杰
徐平
胡琅
胡强
侯立涛
郭远军
李晓峰
黄丽玲
黄星星
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
    • H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32—Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45—Differential amplifiers
    • H03F3/45071—Differential amplifiers with semiconductor devices only
    • H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

The application provides an error amplifier and switching power supply, the error amplifier includes: a bias circuit; the first-stage amplifying circuit is connected with the bias circuit to acquire a first bias current, two input ends of the first-stage amplifying circuit are input with differential signals, and an output end of the first-stage amplifying circuit outputs error voltage signals; the second-stage amplifying circuit comprises a fourth PMOS tube, a seventh PMOS tube, a first capacitor and a seventh NMOS tube, wherein the grid electrode of the seventh PMOS tube is connected with the biasing circuit to acquire a preset bias voltage so that the seventh PMOS tube is in a linear region, the source electrode of the seventh PMOS tube is connected with the output end of the first-stage amplifying circuit to acquire the error voltage signal, the drain electrode of the seventh PMOS tube is connected with one end of the first capacitor, and the other end of the first capacitor is connected with the drain electrode of the seventh NMOS tube and the drain electrode of the fourth MOS tube, and the drain electrode of the seventh PMOS tube is connected with a first common node and takes the first common node as the output end of the second-stage amplifying circuit; system stability is ensured and power consumption is reduced.

Description

Error amplifier and switching power supply
Technical Field
The application relates to the technical field of switching circuits, in particular to an error amplifier and a switching power supply.
Background
With the progress of science and the development of electronic commerce, the requirements of power management chips for consumer and portable applications are also increasing. Because of the development of microelectronic technology, switching power supplies have entered into a highly integrated era, and portable electronic products play a vital role in daily life, no matter flat-panel, mobile phones, palm computers or other portable electronic products powered by batteries, miniaturization, low power consumption and stability are increasingly pursued. The error amplifier is used in switching power supply to compare and amplify the sampled voltage at output end with reference voltage, and the error amplified signal is input into comparator to generate pulse signal for controlling power switch tube. The larger the gain of the error amplifier is, the smaller the ripple wave of the output voltage is, and the better the load adjustment rate of the whole system is; the phase margin of the error amplifier is 45 degrees to 60 degrees, the system is stable, and the dynamic response is good; the smaller the quiescent current of the error amplifier, the lower the overall power consumption. The larger the gain variation, the larger the output voltage ripple of the switching power supply if the error amplifier is within a wide supply voltage range. Solving this problem requires an error amplifier with small gain variation with supply voltage, simple circuitry, and small quiescent current.
The traditional error amplifier has simple circuit, smaller gain and larger change along with the power supply voltage, and the RC compensation adopted for improving the phase margin brings additional power consumption.
Accordingly, the prior art has drawbacks and improvements are urgently needed.
Disclosure of Invention
An object of the embodiments of the present application is to provide an error amplifier and a switching power supply, which are used for ensuring system stability and reducing power consumption.
In a first aspect, embodiments of the present application provide an error amplifier, applying a switching power supply, the error amplifier including:
a bias circuit for generating a first bias current, a second bias current and a predetermined bias voltage;
the first-stage amplifying circuit is connected with the bias circuit to acquire a first bias current, two input ends of the first-stage amplifying circuit are input with differential signals, and an output end of the first-stage amplifying circuit outputs error voltage signals;
the second-stage amplifying circuit comprises a fourth PMOS tube, a seventh PMOS tube, a first capacitor and a seventh NMOS tube, wherein the grid electrode of the seventh PMOS tube is connected with the biasing circuit to obtain a preset bias voltage so that the seventh PMOS tube is in a linear region, the source electrode of the seventh PMOS tube is connected with the output end of the first-stage amplifying circuit to obtain the error voltage signal, the drain electrode of the seventh PMOS tube is connected with one end of the first capacitor, the other end of the first capacitor is connected with the drain electrode of the seventh NMOS tube and the drain electrode of the fourth MOS tube, the drain electrode of the seventh NMOS tube is connected with a first common node and is used as the output end of the second-stage amplifying circuit, the source electrode of the seventh NMOS tube is grounded, and the source electrode of the fourth PMOS tube is connected with the biasing circuit to obtain a second preset bias current.
Optionally, in the error amplifier described in the embodiments of the present application, the first stage amplifying circuit is a differential amplifying circuit.
Optionally, in the error amplifier described in the embodiment of the present application, the first stage amplifying circuit includes a third PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
the source electrode of the third PMOS tube is connected with a preset power supply voltage, the grid electrode of the third PMOS tube is connected with the bias circuit to obtain a first bias current, the drain electrode of the third PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected, the drain electrode of the fifth PMOS tube, the grid electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube are connected, the source electrode of the fifth NMOS tube is grounded, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube and the drain electrode of the sixth PMOS tube are connected to serve as an error voltage output end of the first-stage amplifying circuit; and the grid electrode of the sixth PMOS tube and the grid electrode of the fifth PMOS tube are connected with differential voltage signals.
Optionally, in the error amplifier described in the embodiment of the present application, the bias circuit includes a first PMOS transistor and a second PMOS transistor;
the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a preset power supply voltage;
the grid electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the second PMOS tube in a second common node, and the second common node is respectively connected with the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube so as to respectively provide bias current for the grid electrode of the third PMOS tube and the fourth PMOS tube.
Optionally, in the error amplifier described in the embodiment of the present application, the bias circuit further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the first PMOS tube are connected to a third common node, and the third common node is connected with the seventh PMOS tube;
the source electrode of the first NMOS tube, the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected, the source electrode of the third NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is connected with the ground.
Optionally, in the error amplifier according to the embodiment of the present application, the bias circuit further includes a resistor, and the source of the fourth NMOS transistor is grounded through the resistor.
Optionally, in the error amplifier according to the embodiment of the present application, the gain of the first stage amplifying circuit is adjusted by adjusting the width-to-length ratio of the sixth PMOS transistor, the width-to-length ratio of the sixth NMOS transistor, and the drain current of the third PMOS transistor.
Optionally, in the error amplifier according to the embodiment of the present application, the gain of the second stage amplifying circuit is adjusted by adjusting the width-to-length ratio of the seventh NMOS transistor, the width-to-length ratio of the fourth PMOS transistor, and the drain current of the fourth PMOS transistor.
Optionally, in the error amplifier according to the embodiment of the present application, the phase margin of the second stage amplifying circuit is adjusted by adjusting the width-to-length ratio of the seventh PMOS transistor P7 and the capacitance value of the first capacitor.
In a second aspect, embodiments of the present application provide a switching power supply including an error amplifier as described in any one of the above.
From the above, the error amplifier and the switching power supply provided in the embodiments of the present application operate in the linear region by controlling the seventh PMOS transistor, so that the seventh PMOS transistor is equivalent to a resistor, and forms RC miller compensation with the first capacitor, thereby ensuring system stability and reducing power consumption.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic block diagram of an error amplifier provided in an embodiment of the present application.
Fig. 2 is a circuit configuration diagram of an error amplifier according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
In the description of the present application, it should be noted that, the azimuth or positional relationship indicated by the terms "inner", "outer", etc. are based on the azimuth or positional relationship shown in the drawings, or the azimuth or positional relationship that is commonly put when the product of the application is used, are merely for convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and therefore should not be construed as limiting the present application. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.
It should also be noted that the terms "disposed," "coupled," and "connected" are to be construed broadly, and may be, for example, fixedly coupled, detachably coupled, or integrally coupled, unless otherwise specifically defined and limited; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Referring to fig. 1 and fig. 2, fig. 1 is a schematic circuit diagram of an error amplifier according to an embodiment of the present application. The error amplifier employs a switching power supply, the error amplifier comprising: a bias circuit 30, a first stage amplification circuit 10 and a second stage amplification circuit 20.
The bias circuit 30 is configured to generate a first bias current, a second bias current, and a predetermined bias voltage. A first stage amplifying circuit 10 connected to the bias circuit 30 to obtain a first bias current, wherein two input terminals thereof input differential signals, and an output terminal thereof outputs an error voltage signal;
the second stage amplifying circuit 20 includes a fourth PMOS transistor, a seventh PMOS transistor, a first capacitor, and a seventh NMOS transistor, where a gate of the seventh PMOS transistor is connected to the bias circuit 30 to obtain a preset bias voltage so that the seventh PMOS transistor is in a linear region, a source of the seventh PMOS transistor is connected to an output of the first stage amplifying circuit 10 to obtain the error voltage signal, a drain of the seventh PMOS transistor is connected to one end of the first capacitor, another end of the first capacitor is connected to a drain of the seventh NMOS transistor and a drain of the fourth NMOS transistor are connected to a first common node and use the first common node as an output of the second stage amplifying circuit 20, a source of the seventh NMOS transistor is grounded, and a source of the fourth PMOS transistor is connected to the bias circuit 30 to obtain a second preset bias current. The gain of the second-stage amplifying circuit 20 can be adjusted by adjusting the width-to-length ratio of the seventh NMOS transistor, the width-to-length ratio of the fourth PMOS transistor and the drain current of the fourth PMOS transistor; the phase margin of the second stage amplifying circuit 20 is adjusted by adjusting the width-to-length ratio of the seventh PMOS P7 and the capacitance value of the first capacitor.
According to the error amplifier provided by the embodiment of the application, the seventh PMOS tube P7 is controlled to work in the linear region, so that the seventh PMOS tube P7 is equivalent to a resistor, RC miller compensation is formed by the resistor and the first capacitor C, system stability is guaranteed, and power consumption is reduced.
Specifically, the first-stage amplification circuit 10 is a differential amplification circuit. The first stage amplifying circuit 10 includes a third PMOS transistor P3, a fifth PMOS transistor P5, a sixth PMOS transistor P6, a fifth NMOS transistor N5, and a sixth NMOS transistor N6.
The source electrode of the third PMOS transistor P3 is connected to a preset supply voltage Vin, the gate electrode of the third PMOS transistor P3 is connected to the bias circuit 30 to obtain a first bias current, the drain electrode of the third PMOS transistor P3, the source electrode of the fifth PMOS transistor P5 and the source electrode of the sixth PMOS transistor P6 are connected, the drain electrode of the fifth PMOS transistor P5, the gate electrode and the drain electrode of the fifth NMOS transistor N5 and the gate electrode of the sixth NMOS transistor N6 are connected, the source electrode of the fifth NMOS transistor N5 is grounded, the source electrode of the sixth NMOS transistor N6 is grounded, and the drain electrode of the sixth NMOS transistor N6 and the drain electrode of the sixth PMOS transistor P6 are connected as an error voltage output end of the first stage amplifying circuit 10; and the grid electrode of the sixth PMOS tube P6 and the grid electrode of the fifth PMOS tube P5 are connected with differential voltage signals. The gain of the first-stage amplifying circuit 10 is adjusted by adjusting the width-to-length ratio of the sixth PMOS transistor P6, the width-to-length ratio of the sixth NMOS transistor N6, and the drain current of the third PMOS transistor P3.
Specifically, the bias circuit 30 includes a first PMOS transistor P1, a second PMOS transistor P2, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, and a fourth NMOS transistor N4.
The source electrode of the first PMOS tube P1 and the source electrode of the second PMOS tube P2 are connected and connected with a preset power supply voltage; the grid electrode of the first PMOS tube P1, the grid electrode of the second PMOS tube P2 and the drain electrode are connected to a second common node, and the second common node is respectively connected with the grid electrode of the third PMOS tube P3 and the grid electrode of the fourth PMOS tube so as to respectively provide bias current for the grid electrode of the third PMOS tube P3 and the fourth PMOS tube. The grid electrode and the drain electrode of the first NMOS tube N1, the grid electrode of the second NMOS tube N2 and the drain electrode of the first PMOS tube P1 are connected to a third common node, and the third common node is connected with the seventh PMOS tube; the source electrode of the first NMOS tube N1, the grid electrode and the drain electrode of the third NMOS tube N3 and the grid electrode of the fourth NMOS tube N4 are connected, the source electrode of the third NMOS tube N3 is grounded, the drain electrode of the fourth NMOS tube N4 is connected with the source electrode of the second NMOS tube N2, and the source electrode of the fourth NMOS tube N4 is connected with the ground.
Optionally, in the error amplifier according to the embodiment of the present application, the bias circuit 30 further includes a resistor R, and the source of the fourth NMOS transistor N4 is grounded through the resistor R.
The bias current provided by the bias circuit is only related to the resistor R, the third NMOS tube N3 and the fourth NMOS tube N4, and is not influenced by the power supply voltage, so that the gain is less changed by the power supply voltage, and the stability can be improved.
The embodiment of the application also provides a switching power supply, which comprises the error amplifier in any embodiment.
The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. An error amplifier employing a switching power supply, the error amplifier comprising:
a bias circuit for generating a first bias current, a second bias current and a predetermined bias voltage;
the first-stage amplifying circuit is connected with the bias circuit to acquire a first bias current, two input ends of the first-stage amplifying circuit are input with differential signals, and an output end of the first-stage amplifying circuit outputs error voltage signals;
the second-stage amplifying circuit comprises a fourth PMOS tube, a seventh PMOS tube, a first capacitor and a seventh NMOS tube, wherein the grid electrode of the seventh PMOS tube is connected with the biasing circuit to obtain a preset bias voltage so that the seventh PMOS tube is in a linear region, the source electrode of the seventh PMOS tube is connected with the output end of the first-stage amplifying circuit to obtain the error voltage signal, the drain electrode of the seventh PMOS tube is connected with one end of the first capacitor, the other end of the first capacitor is connected with the drain electrode of the seventh NMOS tube and the drain electrode of the fourth PMOS tube, the first common node is used as the output end of the second-stage amplifying circuit, the source electrode of the seventh NMOS tube is grounded, and the source electrode of the fourth PMOS tube is connected with the biasing circuit to obtain a second preset bias current.
2. The error amplifier of claim 1, wherein the first stage amplification circuit is a differential amplification circuit.
3. The error amplifier of claim 2, wherein the first stage amplification circuit comprises a third PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a fifth NMOS transistor, and a sixth NMOS transistor;
the source electrode of the third PMOS tube is connected with a preset power supply voltage, the grid electrode of the third PMOS tube is connected with the bias circuit to obtain a first bias current, the drain electrode of the third PMOS tube, the source electrode of the fifth PMOS tube and the source electrode of the sixth PMOS tube are connected, the drain electrode of the fifth PMOS tube, the grid electrode of the fifth NMOS tube and the drain electrode of the sixth NMOS tube are connected, the source electrode of the fifth NMOS tube is grounded, the source electrode of the sixth NMOS tube is grounded, and the drain electrode of the sixth NMOS tube and the drain electrode of the sixth PMOS tube are connected to serve as an error voltage output end of the first-stage amplifying circuit; and the grid electrode of the sixth PMOS tube and the grid electrode of the fifth PMOS tube are connected with differential voltage signals.
4. The error amplifier of claim 3, wherein the bias circuit comprises a first PMOS transistor and a second PMOS transistor;
the source electrode of the first PMOS tube is connected with the source electrode of the second PMOS tube and is connected with a preset power supply voltage;
the grid electrode of the first PMOS tube is connected with the grid electrode and the drain electrode of the second PMOS tube in a second common node, and the second common node is respectively connected with the grid electrode of the third PMOS tube and the grid electrode of the fourth PMOS tube so as to respectively provide bias current for the grid electrode of the third PMOS tube and the fourth PMOS tube.
5. The error amplifier of claim 4, wherein the bias circuit further comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor;
the grid electrode and the drain electrode of the first NMOS tube, the grid electrode of the second NMOS tube and the drain electrode of the first PMOS tube are connected to a third common node, and the third common node is connected with the seventh PMOS tube;
the source electrode of the first NMOS tube, the grid electrode of the third NMOS tube, the drain electrode of the third NMOS tube and the grid electrode of the fourth NMOS tube are connected, the source electrode of the third NMOS tube is grounded, the drain electrode of the fourth NMOS tube is connected with the source electrode of the second NMOS tube, and the source electrode of the fourth NMOS tube is connected with the ground.
6. The error amplifier of claim 5 wherein the bias circuit further comprises a resistor through which the source of the fourth NMOS transistor is grounded.
7. The error amplifier of claim 6, wherein the gain of the first stage amplifying circuit is adjusted by adjusting the aspect ratio of the sixth PMOS transistor, the aspect ratio of the sixth NMOS transistor, and the drain current of the third PMOS transistor.
8. The error amplifier of claim 3 wherein the gain of the second stage amplifying circuit is adjusted by adjusting the aspect ratio of the seventh NMOS transistor, the aspect ratio of the fourth PMOS transistor, and the drain current of the fourth PMOS transistor.
9. The error amplifier of claim 3 wherein the phase margin of the second stage amplifying circuit is adjusted by adjusting the aspect ratio of the seventh PMOS transistor and the capacitance value of the first capacitor.
10. A switching power supply comprising an error amplifier as claimed in any one of claims 1 to 9.
CN201911382855.4A 2019-12-27 2019-12-27 Error amplifier and switching power supply Active CN111162743B (en)

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Application Number Priority Date Filing Date Title
CN201911382855.4A CN111162743B (en) 2019-12-27 2019-12-27 Error amplifier and switching power supply

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Application Number Priority Date Filing Date Title
CN201911382855.4A CN111162743B (en) 2019-12-27 2019-12-27 Error amplifier and switching power supply

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CN111162743B true CN111162743B (en) 2024-01-16

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0606094A2 (en) * 1993-01-08 1994-07-13 Sony Corporation Monolithic microwave integrated circuit
CN107040224A (en) * 2017-05-04 2017-08-11 广州慧智微电子有限公司 One kind control circuit and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0606094A2 (en) * 1993-01-08 1994-07-13 Sony Corporation Monolithic microwave integrated circuit
CN107040224A (en) * 2017-05-04 2017-08-11 广州慧智微电子有限公司 One kind control circuit and method

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