CN103455076A - High power supply rejection LDO voltage stabilizer based on native NMOS transistor - Google Patents

Abstract

A high power supply rejection LDO voltage stabilizer based on a native NMOS transistor belongs to the field of integrated circuits, and aims to solve the contradiction among the drop-away voltage and efficiency of the LDO voltage stabilizer and the high-frequency power supply rejection. The voltage stabilizer comprises an error amplifier A1, a resistor R1, a resistor R2, a filtering resistor RF, a filtering capacitor CF, a first native NMOS transistor MNA1 and a second native NMOS transistor MNA 2, wherein the non-inverting input end of the error amplifier A1 is connected with the output end of the reference voltage; the opposite phase input end of the error amplifier A1 is connected to a feedback node; the common node of the resistor R1 and the resistor R2 serves as a feedback node VF1; the output end of the error amplifier is connected with a grid electrode of the first native NMOS transistor MNA1; the drain electrode of the first native NMOS transistor MNA1 is connected with a power supply VDD, and the source electrode of the first native NMOS transistor MNA1 is connected with one end of the resistor R2; the other end of the resistor R1 is connected with one end of the resistor R2; the source electrode of the second native NMOS transistor MNA 2 is the output end VOUT of the LDO voltage stabilizer.

Description

A kind of high power supply based on the native nmos pass transistor suppresses the LDO voltage stabilizer

Technical field

The present invention relates to a kind of high power supply based on the native nmos pass transistor and suppress the LDO voltage stabilizer, belong to integrated circuit fields.

Background technology

Growing along with semiconductor processing technology, scale and the integrated level of integrated circuit improve constantly, the SOC (system on a chip) (SOC) that comprises a plurality of circuit modules such as simulation, numeral and radio frequency is widely used, and towards the future development of low cost, high integration, miniaturization and hand-held day by day.But the performance of these SOC also easily is subject to the interference of the noises such as high-frequency digital switch, radio-frequency module, has reduced the signal to noise ratio (S/N ratio) of circuit and affected the performance of system.In order to reduce the impact of environment high-frequency noises on the SOC performance, in system, application LDO voltage stabilizer has become a kind of main flow trend.

As shown in Figure 1, its on-chip circuit structure is by error amplifier A for tradition LDO stabilizator structure ₁, PMOS transistor M _p, building-out capacitor C ₁with feedback resistance R ₁, R ₂form the outer electric capacity C of sheet ₂with pull-up resistor R _lbe respectively equivalent load capacitance and the equivalent load resistance of this LDO voltage stabilizer application circuit.Error amplifier A wherein ₁with reference to voltage V _rEFwith feedback node V _fvoltage difference amplified, error amplifier A ₁output V _{o_A1}be used for driving PMOS transistor M _pgrid.The output voltage V of this LDO voltage stabilizer _oUTcan be expressed as

$V_{\mathrm{OUT}}=V_{\mathrm{DD}}-V_{\mathrm{DROP}}=V_{\mathrm{DD}}-V_{\mathrm{OV}\_M_P}---\left(1\right)$

V wherein _dROPthe drop-away voltage of LDO voltage stabilizer, V _dDsupply voltage,

transistor M _poverdrive voltage.LDO voltage stabilizer drop-away voltage is the important indicator of estimating LDO voltage stabilizer performance, and drop-away voltage is less, and the output efficiency of LDO voltage stabilizer is just higher.Due to PMOS transistor M _pwith error amplifier A ₁acting in conjunction, the output voltage of LDO voltage stabilizer will significantly be improved by the impact of interference noise on power supply.Wherein the LDO voltage stabilizer generally means with power supply inhibition (PSR) for the inhibition degree of noise on power supply.Theoretical study results shows, the power supply of traditional LDO voltage stabilizer suppresses can be expressed as with frequency change

$\mathrm{PSR}\left(s\right)=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{DD}}}\left(s\right)=\frac{1+g_{m\_P}{r}_{\mathrm{ds}\_P}}{1+\frac{r_{\mathrm{ds}\_P}}{Z_L\left(s\right)}+\frac{r_{\mathrm{ds}\_P}}{R_1+R_2}+\frac{g_{m\_P}{r}_{\mathrm{ds}\_P}{A}_{\mathrm{eo}}{R}_2}{(R_1+R_2)(1+\frac{s}{w_e})}}---\left(2\right)$

G wherein _{m_P}and r _{ds_P}respectively PMOS transistor M in Fig. 1 _pmutual conductance and drain-source resistance, Z _l(s) be that the equiva lent impedance of LDO output end of voltage stabilizer off chip resistor and electric capacity (does not comprise R ₁and R ₂), A _eoand w _erespectively error amplifier A ₁low-frequency gain and dominant pole.Under low frequency, its power supply suppresses can be approximated to be

$\mathrm{PSR}=(s=0)\≈\frac{1}{A_{\mathrm{eo}}\frac{R_2}{R_1+R_2}\·g_{m\_P}{r}_{\mathrm{ds}\_P}}---\left(3\right)$

For to equivalent load resistance R _lprovide enough large electric current, M _pbreadth length ratio all can be very large, and provide less drop-away voltage.Due to PMOS transistor M _psize larger, error amplifier A ₁output voltage V _{o_A1}the equivalent gate capacitance driven will be very large, adds PMOS transistor M _pgate leakage capacitance and building-out capacitor C ₁miller effect, the bandwidth of whole feedback control loop can be very low, so the PSR of LDO voltage stabilizer can significantly worsen along with the rising of frequency, its high frequency electric source suppresses can be approximated to be

$\mathrm{PSR}=(s=\∞)\≈g_{m\_P}\frac{R_L\·r_{\mathrm{ds}\_P}}{R_L+r_{\mathrm{ds}\_P}}---\left(4\right)$

Pull-up resistor R due to the LDO voltage stabilizer _lall smaller, therefore most LDO voltage stabilizer frequencies are all very low to the inhibition ability of power supply high frequency noise.In order to overcome output power transistors M _pthe impact on loop bandwidth and high frequency electric source inhibition of gate leakage capacitance and building-out capacitor Miller effect, in certain applications, the researcher has proposed the scheme as output power transistors with a nmos pass transistor, as shown in Figure 2, this LDO stabilizer output voltage can be expressed as

$V_{\mathrm{OUT}}=V_{\mathrm{DD}}-V_{\mathrm{DROP}}=V_{\mathrm{DD}}-V_{\mathrm{GS}\_M_N}=V_{\mathrm{DD}}-V_{\mathrm{TH}\_M_N}-V_{\mathrm{OV}\_M_N}---\left(5\right)$

Wherein:

transistor M _noverdrive voltage,

for the threshold voltage of nmos pass transistor in Fig. 2, and

wherein: V _{tH_N}threshold voltage during for substrate and source shorted, η is the body bias effect coefficient, V _bSfor the voltage between transistorized lining and source electrode.Considered transistor M after body bias effect _nthreshold voltage, its value is generally overdrive voltage

several times.Therefore this can increase the drop-away voltage of voltage stabilizer, reduces the power efficiency of LDO voltage stabilizer, by sacrificing drop-away voltage and efficiency, exchanges the improvement that high frequency electric source suppresses for.

Summary of the invention

The present invention seeks to, in order to solve the contradiction between LDO voltage stabilizer drop-away voltage and efficiency and high frequency electric source inhibition, provides a kind of high power supply based on the native nmos pass transistor to suppress the LDO voltage stabilizer.

A kind of high power supply based on the native nmos pass transistor of the present invention suppresses the LDO voltage stabilizer, and it comprises error amplifier A ₁, resistance R ₁, resistance R ₂, filter resistance R _f, filter capacitor C _f, a native nmos pass transistor M _nA1with the 2nd native nmos pass transistor M _nA2;

Error amplifier A ₁in-phase input end connect reference voltage V _rEFoutput terminal, error amplifier A ₁inverting input connect feedback node V _f1, resistance R ₁and resistance R ₂common node as feedback node V _f1;

Error amplifier A ₁output terminal V _{o_A1}the grid that connects a native nmos pass transistor MNA1; The one native nmos pass transistor M _nA1drain electrode connect power supply V _dD, a native nmos pass transistor M _nA1source electrode contact resistance R ₁an end; Resistance R ₁other end contact resistance R ₂an end, resistance R ₂the other end connect GND;

Error amplifier A ₁output terminal V _{o_A1}also connect filter resistance R _fan end, filter resistance R _fthe other end connect filter capacitor C _fan end, filter capacitor C _fthe other end connect GND; Filter resistance R _fwith filter capacitor C _fcommon port V _fconnect the 2nd native nmos pass transistor M _nA2grid, the 2nd native nmos pass transistor M _nA2drain electrode connect power supply V _dD; The 2nd native nmos pass transistor M _nA2source electrode be LDO output end of voltage stabilizer V _oUT.

Advantage of the present invention: actual flow built-in testing result verification has been passed through in the improvement that high frequency electric source is suppressed based on native nmos pass transistor LDO voltage stabilizer that the present invention proposes, LDO voltage stabilizer and traditional LDO voltage stabilizer power supply that Fig. 4 has provided the present invention's proposition suppress (PSR) test result relatively, wherein curve 1 is that traditional LDO voltage stabilizer power supply suppresses test result, curve 2 is that the power supply of the LDO voltage stabilizer based on the native nmos pass transistor that proposes in the present invention suppresses in Fig. 4, the given traditional LDO voltage stabilizer power supply under low frequency of curve 1 suppresses, after frequency surpasses 5KHz, power supply suppresses to start to descend, frequency surpasses 100KHz, power supply suppresses to drop to be less than-20dB, after frequency surpasses 1MHz, power supply suppresses reached+3dB, can't the high frequency interference on power supply be suppressed.Curve 2 is that the LDO voltage stabilizer power supply based on native NMOS crystal proposed in the present invention suppresses, and it is suitable with the inhibition of traditional LDO stabilized voltage supply when low frequency.After frequency surpasses 10KHz, the LDO voltage stabilizer power supply proposed in the present invention suppresses with frequency change significantly better than traditional LDO voltage stabilizer, at 200K, in the 100MHz frequency band, its power supply suppresses for-22dB left and right, and power supply noise is only less than 1/10 output terminal that can be transferred to the LDO voltage stabilizer.

The accompanying drawing explanation

Fig. 1 is traditional LDO voltage regulator circuit figure;

Fig. 2 is that traditional high power supply suppresses LDO voltage regulator circuit figure;

Fig. 3 is a kind of circuit diagram that suppresses the LDO voltage stabilizer based on the high power supply of native nmos pass transistor of the present invention;

Fig. 4 be the present invention propose based on native nmos pass transistor voltage stabilizer and traditional voltage stabilizer Power Supply Rejection Ratio than result schematic diagram; Curve 1 in figure means that traditional LDO voltage stabilizer power supply suppresses curve, and curve 2 means that LDO voltage stabilizer power supply of the present invention suppresses curve;

Fig. 5 is the symbol of traditional nmos pass transistor;

Fig. 6 is the sectional view of traditional nmos pass transistor;

Fig. 7 is the I-V performance diagram of traditional nmos pass transistor;

Fig. 8 is native nmos pass transistor symbol;

Fig. 9 is the sectional view of native nmos pass transistor;

Figure 10 is the I-V performance diagram of native nmos pass transistor.

Embodiment

Embodiment one: below in conjunction with Fig. 1 to Figure 10, present embodiment is described, the described a kind of high power supply based on the native nmos pass transistor of present embodiment suppresses the LDO voltage stabilizer, and it comprises error amplifier A ₁, resistance R ₁, resistance R ₂, filter resistance R _f, filter capacitor C _f, a native nmos pass transistor M _nA1with the 2nd native nmos pass transistor M _nA2;

Error amplifier A ₁in-phase input end connect reference voltage V _rEFoutput terminal, error amplifier A ₁inverting input connect feedback node V _f1, resistance R ₁and resistance R ₂common node as feedback node V _f1;

Error amplifier A ₁output terminal V _{o_A1}connect a native nmos pass transistor M _nA1grid; The one native nmos pass transistor M _nA1drain electrode connect power supply V _dD, a native nmos pass transistor M _nA1source electrode contact resistance R ₁an end; Resistance R ₁other end contact resistance R ₂an end, resistance R ₂the other end connect GND;

Error amplifier A ₁output terminal V _{o_A1}also connect filter resistance R _fan end, filter resistance R _fthe other end connect filter capacitor C _fan end, filter capacitor C _fthe other end connect GND; Filter resistance R _fwith filter capacitor C _fcommon port V _fconnect the 2nd native nmos pass transistor M _nA2grid, the 2nd native nmos pass transistor M _nA2drain electrode connect power supply V _dD; The 2nd native nmos pass transistor M _nA2source electrode be LDO output end of voltage stabilizer V _oUT.

Native MOS is actual is exactly the pipe that threshold voltage is close to zero.

Propose high power supply inhibition LDO voltage stabilizer in present embodiment and be based on native nmos pass transistor design realization, so the native nmos pass transistor is the key of this invention implementation.Fig. 5 to Fig. 7 has provided circuit symbol, device architecture sectional view and the I-V family curve of traditional nmos pass transistor.Fig. 8 to Figure 10 has provided circuit symbol, device architecture sectional view and the I-V family curve of the native nmos pass transistor that the present invention uses.From the traditional nmos pass transistor sectional view shown in Fig. 6, can find out, this transistor fabrication is being mixed with on the substrate of p type impurity, injects heavily doped N-type impurity and has formed transistorized source, drain region (N+), utilizes polysilicon to form grid.The tradition nmos pass transistor, in process, is understood the lower p type impurity of N+ zone implantation concentration between source electrode and drain electrode, and this can absorb the negative charge in this zone.Therefore traditional NMOS crystal is at gate source voltage V _gS, between its source electrode and drain electrode, can't form conducting channel at=0 o'clock.When transistorized grid adds positive voltage, negative charge can be assembled between transistorized source electrode and drain electrode, until gate source voltage, over after certain threshold voltage, can form conducting channel between source electrode and drain electrode, has electric current in transistor and flows through.This transistor channel forms needed threshold voltage and just is called the threshold voltage that transistor is opened, and its value is generally hundreds of millivolt (occurrence changes according to technique is different).And the native nmos pass transistor shown in Fig. 9 is in process, can not inject the doped with P type impurity of adjusting threshold voltage between its source electrode and drain electrode, therefore for the native nmos pass transistor, when gate source voltage is 0, there is conducting channel between its source electrode and drain electrode, now, as long as there are voltage difference in source electrode and drain electrode, just have electric current and flow through this transistor.From Fig. 7 and Figure 10, can find out, the I-V characteristic curve shape of tradition nmos pass transistor and native nmos pass transistor is similar, difference mainly is that the threshold voltage of traditional nmos pass transistor is the hundreds of millivolt, and the threshold voltage of native nmos pass transistor is approximately 0.Therefore, after introducing the native nmos pass transistor, in Fig. 3, the output voltage of LDO voltage stabilizer still utilizes formula (5) to calculate, but because the threshold voltage of native nmos pass transistor is approximately 0, therefore, after quoting the native nmos pass transistor, in Fig. 3, the output voltage of LDO voltage stabilizer can be expressed as

$V_{\mathrm{OUT}}=V_{\mathrm{DD}}-V_{\mathrm{DROP}}=V_{\mathrm{DD}}-V_{\mathrm{GS}\_M_{\mathrm{NA}2}}\≈V_{\mathrm{DD}}-V_{\mathrm{OV}\_M_{\mathrm{NA}2}}---\left(6\right)$

Wherein

the 2nd native nmos pass transistor M in Fig. 3 _nA2overdrive voltage.Formula (6) and (1) can be found out, the drop-away voltage of the LDO voltage stabilizer based on the native nmos pass transistor proposed in the present invention is similar as the structure of power transistor with tradition application PMOS transistor, can overcome traditional nmos pass transistor restriction to drop-away voltage and power efficiency to the LDO voltage stabilizer in Fig. 2.

The inhibition ability to power supply noise based on native nmos pass transistor LDO voltage stabilizer that present embodiment proposes can obtain according to small-signal analysis.At first, analytical error amplifier A ₁, a native nmos pass transistor M _nA1, resistance R ₁and resistance R ₂the backfeed loop formed, and with power supply V _dDas the input end that disturbs AC signal, so a native nmos pass transistor M _nA1grid and source electrode position to the gain of power supply interference noise, can be expressed as respectively

$V_{O\_A1}=\frac{-V_S\·R_2}{R_1+R_2}\·\frac{A_{\mathrm{eo}}}{1+\frac{s}{w_e}}---\left(7\right)$

$[g_{m\_\mathrm{NA}1}(V_{O\_A1}-V_S)+\frac{V_{\mathrm{DD}}-V_S}{r_{\mathrm{ds}\_\mathrm{NA}1}}](R_1+R_2)=V_S---\left(8\right)$

A wherein _eoand w _ebe respectively low-frequency gain and the dominant pole bandwidth of error amplifier, s=jw is complex frequency, and w is circular frequency, g _{m_NA1}and r _{ds_NA1}be respectively a native nmos pass transistor M _nA1mutual conductance and equivalent resistance.V _sa native nmos pass transistor M _nA1the amplitude that the source electrode power supply disturbs.

Formula (7) and (8) are arranged, can be calculated a native nmos pass transistor M _nA1the gain of source to the power supply interference noise, this gain can be expressed as

$\frac{V_S}{V_{\mathrm{DD}}}=\frac{1}{\frac{r_{\mathrm{ds}\_\mathrm{NA}1}}{R_1+R_2}+\frac{g_{m\_\mathrm{NA}1\·R_2\·r_{\mathrm{ds}\_\mathrm{NA}1}}}{R_1+R_2}\·\frac{A_{\mathrm{eo}}}{1+\frac{s}{w_e}}+\frac{g_{m\_\mathrm{NA}1}}{r_{\mathrm{ds}\_\mathrm{NA}1}+1}}---\left(9\right)$

Formula (9) is analyzed and simplified, and under low frequency, its ability of inhibition to power supply noise can approximate representation be

$\frac{V_S}{V_{\mathrm{DD}}}{|}_{s\→0\≈}\frac{R_1+R_2}{g_{m\_\mathrm{NA}1}{r}_{\mathrm{ds}\_\mathrm{NA}1}{R}_2{A}_{\mathrm{eo}}}=\frac{1}{A_{\mathrm{eo}}\mathrm{\β}{g}_{m\_\mathrm{NA}1}{r}_{\mathrm{ds}\_\mathrm{NA}1}}---\left(10\right)$

Wherein this amplifier feedback factor, a native nmos pass transistor M now _nA1source node suppresses quite inhibition and the transistorized LDO voltage stabilizer of formula (3) the middle application PMOS power supply of power supply interference noise.To in formula (10) substitution formula (7), can obtain error amplifier A ₁the power supply of output terminal under low frequency suppress:

$V_{O\_A1}{|}_{s\→0}=\frac{1}{g_{m\_\mathrm{NA}1}\·r_{\mathrm{ds}\_\mathrm{NA}1}}---\left(11\right)$

Error amplifier A ₁output voltage V _{o_A1}process is by filter resistance R _fwith filter capacitor C _fafter the low-pass filter formed, drive the 2nd native nmos pass transistor M _nA2grid, i.e. the 2nd native nmos pass transistor M _nA2grid suppresses to be expressed as to the power supply of power supply interference noise

$V_{G\_\mathrm{NA}2}=V_{O\_A1}{|}_{s\→A1}\·\frac{1}{1+\frac{s}{w_{\mathrm{RC}}}}---\left(12\right)$

Wherein, w _rCthe pole frequency of filter resistance and filter capacitor, for the 2nd native nmos pass transistor M _nA2carrying out small-signal analysis can obtain

$g_{m\_\mathrm{NA}2}(V_{G\_\mathrm{NA}2}-V_{\mathrm{OUT}})+\frac{V_{\mathrm{DD}}-V_{\mathrm{OUT}}}{r_{\mathrm{ds}\_\mathrm{NA}2}}\·R_L=V_{\mathrm{OUT}}---\left(13\right)$

G in formula (13) _{m_NA2}and r _{ds_NA2}be respectively the 2nd native nmos pass transistor M _nA2mutual conductance and equivalent resistance, R _lfor equivalent load resistance.

Formula (13) is arranged and obtains

$\frac{V_{\mathrm{OUT}}}{V_{\mathrm{DD}}}=\frac{1}{\frac{R_L}{r_{\mathrm{ds}\_\mathrm{NA}2}}+1+g_{m\_\mathrm{NA}2}\·r_{\mathrm{ds}\_\mathrm{NA}2}+g_{m2\_\mathrm{NA}2}\·r_{\mathrm{ds}\_\mathrm{NA}2}\·\frac{A_{\mathrm{eo}}{R}_2}{(R_1+R_2)(1+\frac{s}{w_e})(1+\frac{s}{w_{\mathrm{RC}}})}}---\left(14\right)$

When low frequency, this LDO voltage stabilizer output node power supply suppresses to be expressed as

$\frac{V_{\mathrm{OUT}}}{V_{\mathrm{DD}}}{|}_{s\→0}\≈\frac{R_1+R_2}{g_{m\_\mathrm{NA}2}{r}_{\mathrm{ds}\_\mathrm{NA}2}{R}_2{A}_{\mathrm{eo}}}=\frac{1}{A_{\mathrm{eo}}\mathrm{\β}{g}_{m\_\mathrm{NA}2}{r}_{\mathrm{ds}\_\mathrm{NA}2}}---\left(15\right)$

Its size suppresses quite with the transistorized LDO voltage stabilizer of formula (3) middle application PMOS power supply.When high frequency, the power supply of this LDO voltage stabilizer suppresses can be approximated to be

$\frac{V_{\mathrm{OUT}}}{V_{\mathrm{DD}}}{|}_{s\→\∞}=\frac{1}{g_{m\_\mathrm{NA}2}\·r_{\mathrm{ds}\_\mathrm{NA}2}}---\left(16\right)$

In the present embodiment, be about-22dB left and right, this LDO voltage stabilizer based on the native nmos pass transistor is under high frequency, the poorest power supply suppresses also have-22dB, in this and Fig. 4, curve 2 has provided that the present invention proposes suppresses the test result high band based on native nmos pass transistor LDO voltage stabilizer power supply and fits like a glove, and has proved the improvement that this circuit suppresses LDO voltage stabilizer high frequency electric source.

Fig. 5 to Fig. 7 has provided circuit symbol, device architecture sectional view and the I-V family curve of traditional nmos pass transistor.

Fig. 8 to Figure 10 has provided circuit symbol, device architecture sectional view and the I-V family curve of the native nmos pass transistor that the present invention uses.

From Fig. 5 to Figure 10, can find out, add man-hour at common nmos pass transistor, meeting injection one deck below its grid is adjusted the impurity of threshold voltage, therefore its transistorized threshold voltage generally can reach hundreds of mV, and the native nmos pass transistor of using in the present invention is in the process of making, need to be below grid injection adjust the impurity of threshold voltage, so this transistor process do not need to increase new level, can not increase the plate-making cost of process.Because the grid of native nmos pass transistor does not have implanted dopant, so its threshold voltage is very low, is generally in the 0V left and right, can realize the nature conducting.

Claims (1)

1. the high power supply based on the native nmos pass transistor suppresses the LDO voltage stabilizer, it is characterized in that, it comprises error amplifier A ₁, resistance R ₁, resistance R ₂, filter resistance R _f, filter capacitor C _f, a native nmos pass transistor M _nA1with the 2nd native nmos pass transistor M _nA2;

Error amplifier A ₁in-phase input end connect reference voltage V _rEFoutput terminal, error amplifier A ₁inverting input connect feedback node V _f1, resistance R ₁and resistance R ₂common node as feedback node V _f1;

Error amplifier A ₁output terminal V _{o_A1}connect a native nmos pass transistor M _nA1grid; The one native nmos pass transistor M _nA1drain electrode connect power supply V _dD, a native nmos pass transistor M _nA1source electrode contact resistance R ₁an end; Resistance R ₁other end contact resistance R ₂an end, resistance R ₂the other end connect GND;

Error amplifier A ₁output terminal V _{o_A1}also connect filter resistance R _fan end, filter resistance R _fthe other end connect filter capacitor C _fan end, filter capacitor C _fthe other end connect GND; Filter resistance R _fwith filter capacitor C _fcommon port V _fconnect the 2nd native nmos pass transistor M _nA2grid, the 2nd native nmos pass transistor M _nA2drain electrode connect power supply V _dD; The 2nd native nmos pass transistor M _nA2source electrode be LDO output end of voltage stabilizer V _oUT.

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