CN116774767A - Low-noise high-power supply rejection ratio stabilized voltage power supply and electronic equipment - Google Patents

Low-noise high-power supply rejection ratio stabilized voltage power supply and electronic equipment Download PDF

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CN116774767A
CN116774767A CN202310178431.6A CN202310178431A CN116774767A CN 116774767 A CN116774767 A CN 116774767A CN 202310178431 A CN202310178431 A CN 202310178431A CN 116774767 A CN116774767 A CN 116774767A
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power supply
unit
tube
output
voltage stabilizing
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CN116774767B (en
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王韩
李立
杨磊
王东旺
马洪祥
吕晓鹏
胡锦瑞
方舒悦
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Zhaoxun Hengda Technology Co ltd
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Zhaoxun Hengda Technology Co ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Amplifiers (AREA)

Abstract

The invention discloses a low-noise high-power supply rejection ratio stabilized voltage power supply and electronic equipment. The power supply voltage end is connected with the power supply end of the first-stage voltage stabilizing circuit, the output end of the first-stage voltage stabilizing circuit is connected with the power supply end of the second-stage voltage stabilizing circuit, and the output end of the second-stage voltage stabilizing circuit is connected with the output end of the voltage stabilizing power supply. The first-stage voltage stabilizing circuit adopts a structure that a feedback network and an output unit are arranged separately and a power tube is an NMOS tube, and generates and outputs intermediate voltage; the second-stage voltage stabilizing circuit adopts a single-tube amplifier structure to generate and output a power supply voltage; through cascade connection of the first-stage voltage stabilizing circuit and the second-stage voltage stabilizing circuit, low-noise high-power supply rejection ratio voltage output is realized at the output end of the voltage stabilizing power supply.

Description

Low-noise high-power supply rejection ratio stabilized voltage power supply and electronic equipment
Technical Field
The invention relates to a low-noise high-power supply rejection ratio stabilized voltage power supply, and also relates to electronic equipment comprising the stabilized voltage power supply, belonging to the technical field of integrated circuits.
Background
As is well known, a low dropout linear regulator (LDO) is widely used as a power management module for various integrated circuits and electronic devices, and has low cost, low power consumption, and other excellent performances. For example, an LDO that supplies power to an MCU chip requires a large output drive current; LDOs for supplying power to wireless transceiver chips, LDOs with low noise are needed; LDOs that power analog circuits in SOC chips require LDOs with high power supply rejection ratios (PSRs). In many analog circuits and radio frequency circuits, a power supply of a Voltage Controlled Oscillator (VCO) has a high requirement on performance indexes of the LDO, which requires a high power supply rejection ratio and a high rejection ratio, and also requires that the influence of power supply noise on the VCO is well suppressed, and meanwhile, the noise generated by the LDO itself is required to be small, so as to improve the phase noise of the VCO.
In the prior art, a typical LDO circuit is shown in fig. 1, which includes a current source I0, an operational amplifier OP, an output driving tube PM2, a resistor R0, and a capacitor C0; the operational amplifier OP is composed of five tubes. In order to obtain better noise performance, a larger current I1 needs to flow through the operational amplifier OP to reduce the noise of the LDO, but the suppression capability of the structure to the power supply is quite general. In addition, since the output driving tube PM2 is a PMOS tube, when performing frequency compensation, the output terminal Vout is pushed to the far end to be the secondary pole, and the drain terminal of the output node PM0 of the operational amplifier is the dominant pole, the output terminal Vout of the LDO cannot be configured with a large capacitor C0 (usually 50pF or less) to filter noise generated by the power supply and the operational amplifier itself. Therefore, how to overcome the above problems, it is a technical research topic of the art to provide a regulated power supply with low noise and high power supply rejection ratio to meet the power supply requirements of VCO and various application IC chips.
In the chinese patent No. ZL 201911257150.X, a two-stage low dropout linear regulator with low noise and high power supply rejection ratio is disclosed. The two-stage low-dropout linear voltage regulator is formed by cascading a low-dropout linear voltage regulator with a high power supply rejection ratio and a low-noise low-dropout linear voltage regulator; the former comprises a high power supply rejection ratio band gap reference voltage source and a high power supply rejection ratio low dropout regulator main body circuit; the latter includes a low noise bandgap reference voltage source and a low noise low dropout linear regulator main body circuit. At a power supply voltage VDD of 1.8V, the low dropout linear regulator with high power supply rejection ratio provides a zero temperature coefficient power supply voltage VDD1 of 1.4V for the low dropout linear regulator with low noise; the two stages of low-voltage difference linear voltage stabilizer with low noise and high power supply rejection ratio are realized through cascade connection, and a zero temperature coefficient voltage Vout of 600mV is output.
Disclosure of Invention
The primary technical problem to be solved by the invention is to provide a low-noise high-power supply rejection ratio stabilized voltage power supply.
Another technical problem to be solved by the present invention is to provide an electronic device including the regulated power supply.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
according to a first aspect of an embodiment of the present invention, a low-noise high-power supply rejection ratio regulated power supply is provided, including a first stage voltage stabilizing circuit and a second stage voltage stabilizing circuit; wherein,,
the power supply voltage Vdd terminal is connected with the power supply terminal of the first stage voltage stabilizing circuit, the output terminal of the first stage voltage stabilizing circuit is connected with the power supply terminal of the second stage voltage stabilizing circuit, and the output terminal of the second stage voltage stabilizing circuit is connected with the output terminal of the voltage stabilizing power supply;
the first-stage voltage stabilizing circuit is an LDO circuit, is arranged separately from the output unit by adopting a feedback network, and is of an NMOS tube structure, and generates and outputs an intermediate voltage Vdd1; the second-stage voltage stabilizing circuit comprises at least one LDO circuit, and each LDO circuit adopts a structure of a single-tube amplifier to generate and output a power supply voltage Vout; through cascade connection of the first-stage voltage stabilizing circuit and the second-stage voltage stabilizing circuit, low-noise high-power supply rejection ratio voltage output is realized at the output end of the voltage stabilizing power supply.
Preferably, the first-stage voltage stabilizing circuit comprises an operational amplifying unit, a feedback unit and an output unit; wherein,,
the power end of the operational amplification unit is connected with a power voltage Vdd end, the non-inverting input end of the operational amplification unit is connected with a first reference voltage end, and the output end of the operational amplification unit is respectively connected with the input ends of the feedback unit and the output unit; the output end of the feedback unit is connected with the inverting input end of the operational amplification unit; and the output end of the output unit is connected with the second-stage voltage stabilizing circuit.
Preferably, the operational amplifier unit adopts a folding operational amplifier structure.
Preferably, the feedback unit is composed of an eighth NMOS tube NM7 and a first feedback resistor R0; wherein,,
the drain electrode of the eighth NMOS tube NM7 is connected with a power supply voltage Vdd end, the grid electrode of the eighth NMOS tube NM7 is connected with the output end of the operational amplification unit and the input end of the output unit, and the source electrode of the eighth NMOS tube NM7 is connected with a first feedback resistor R0 and the inverting input end of the operational amplification unit; the other end of the first feedback resistor R0 is connected with a ground potential end.
Preferably, the output unit is composed of a ninth NMOS tube NM8 and a first filter capacitor C0; wherein,,
the drain electrode of the ninth NMOS tube NM8 is connected with a power supply voltage Vdd end, the grid electrode of the ninth NMOS tube NM8 is connected with the output end of the operational amplification unit and the input end of the feedback unit, the source electrode of the ninth NMOS tube NM8 is connected with a first filter capacitor C0 and the output end of the first stage voltage stabilizing circuit, and the other end of the first filter capacitor C0 is connected with a ground potential end.
Preferably, the capacitance value of the first filter capacitor C0 is not smaller than 100pF.
Preferably, each LDO circuit in the second-stage voltage stabilizing circuit has the same structure, and comprises a current source unit, a bias voltage unit and an amplifying output unit; wherein,,
the output end of the current source unit is connected with the input end of the bias voltage unit and the first input end of the amplifying output unit; the output end of the bias voltage unit is connected with the third input end of the amplifying output unit; and the second input end of the amplifying output unit is connected with a second reference voltage end, and the output end of the amplifying output unit is connected with the output end of the LDO circuit.
Preferably, the bias voltage unit is composed of a twelfth PMOS tube PM12, a twelfth NMOS tube NM12 and a thirteenth NMOS tube NM 13; wherein,,
the grid electrode of the twelfth PMOS tube PM12 is connected with the output end of the current source unit and the first input end of the amplifying output unit, the source electrode of the twelfth PMOS tube PM12 is connected with the output end of the first-stage voltage stabilizing circuit, the drain electrode of the twelfth PMOS tube PM12 is connected with the drain electrode of the twelfth NMOS tube NM12 and the third input end of the amplifying output unit, the drain electrode of the twelfth NMOS tube NM12 is connected with the grid electrode in a short circuit mode, the source electrode of the twelfth NMOS tube NM12 is connected with the drain electrode of the thirteenth NMOS tube NM13 in a short circuit mode, the drain electrode of the thirteenth NMOS tube NM13 is connected with the grid electrode in a short circuit mode, and the source electrode of the thirteenth NMOS tube NM13 is connected with the ground potential end.
The amplifying output unit is preferably composed of a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, a fifteenth PMOS tube PM15, a fourteenth NMOS tube NM14, an eleventh resistor R11 and a second filter capacitor C10; wherein,,
the thirteenth PMOS tube PM13, the fourteenth PMOS tube PM14 and the fifteenth PMOS tube PM15 form a single-tube amplifier, wherein the fifteenth PMOS tube PM15 is an input tube, the fourteenth PMOS tube PM14 is a cascade tube, and the thirteenth PMOS tube PM13 is a load tube.
Preferably, in the amplifying output unit, a gate of a thirteenth PMOS tube PM13 is connected to the output end of the current source unit and the input end of the bias voltage unit, a source of the thirteenth PMOS tube PM13 is connected to the output end of the first stage voltage stabilizing circuit, a drain of the thirteenth PMOS tube PM13 is connected to a gate of a fourteenth PMOS tube PM14 and a drain of a fourteenth NMOS tube NM14, a gate of the fourteenth NMOS tube NM14 is connected to the second reference voltage end, a source of the fourteenth NMOS tube NM14 is connected to an eleventh resistor R11 and a drain of the fifteenth PMOS tube PM15, and the other end of the eleventh resistor R11 is connected to a ground potential end; the grid electrode of the fifteenth PMOS tube PM15 is connected with the output end of the bias voltage unit, and the source electrode of the fifteenth PMOS tube PM15 is connected with the second filter capacitor C10, the drain electrode of the fourteenth PMOS tube PM14 and the output end of the amplifying output unit; the other end of the second filter capacitor C10 is connected with a ground potential end; the source electrode of the fourteenth PMOS tube PM14 is connected with the output end of the first-stage voltage stabilizing circuit.
Preferably, the second-stage voltage stabilizing circuit adopts two or more LDOs with the same structure and is used for providing two or more power supplies for the application circuit; the power end of each LDO is connected with the output end of the first-stage voltage stabilizing circuit.
According to a second aspect of an embodiment of the present invention, there is provided an electronic device including the above-described low-noise high-power supply rejection ratio regulated power supply.
Compared with the prior art, the low-noise high-power supply rejection ratio voltage-stabilized power supply provided by the invention adopts a two-stage LDO stacking structure, namely the cascade connection of the first-stage voltage-stabilized circuit and the second-stage voltage-stabilized circuit, and finally the low-noise high-power supply rejection ratio voltage output is realized at the output end of the voltage-stabilized power supply. The first-stage voltage stabilizing circuit adopts the technical scheme that the output unit and the feedback unit are arranged separately, so that the output end can be provided with a larger filter capacitor, and noise generated by a power supply and the LDO is reduced. Meanwhile, by adopting the technical scheme that the folding operational amplifier structure and the power tube in the output unit adopts the NMOS tube, the power supply rejection ratio and the noise performance of the first-stage voltage stabilizing circuit are improved. The second-stage voltage stabilizing circuit further effectively reduces noise generated by the LDO by adopting the technical scheme of a single-tube amplifier. Therefore, the low-noise high-power supply rejection ratio stabilized power supply has the beneficial effects of excellent power supply performance and the like, and can provide a power supply with excellent performance for VCO and various application IC chips.
Drawings
FIG. 1 is a schematic diagram of a typical LDO circuit of the prior art;
FIG. 2 is a block diagram of a low noise high power supply rejection ratio regulated power supply according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a first stage voltage regulator circuit according to an embodiment of the present invention;
FIG. 4 is a schematic circuit diagram of a second stage voltage regulator circuit according to an embodiment of the present invention;
FIG. 5 is a simulation test chart of the power supply rejection ratio of the regulated power supply according to the embodiment of the invention;
FIG. 6 is a simulation test chart of the noise of the regulated power supply according to the embodiment of the invention;
FIG. 7 is a schematic diagram of a voltage-stabilized power supply with multiple output terminals according to an embodiment of the present invention;
fig. 8 is a schematic diagram of an electronic device using a low-noise high-power supply rejection ratio regulated power supply according to an embodiment of the present invention.
Detailed Description
The technical contents of the present invention will be described in detail with reference to the accompanying drawings and specific examples.
As shown in FIG. 2, the low-noise high-power supply rejection ratio stabilized power supply provided by the embodiment of the invention comprises a first-stage stabilized voltage circuit and a second-stage stabilized voltage circuit. The power supply voltage Vdd terminal is connected to the power supply terminal of the first stage voltage stabilizing circuit, the output terminal of the first stage voltage stabilizing circuit is connected to the power supply terminal of the second stage voltage stabilizing circuit, and the output terminal of the second stage voltage stabilizing circuit is connected to the output terminal of the voltage stabilizing power supply.
The first stage voltage stabilizing circuit is an LDO circuit, a feedback network and an output unit are arranged separately, and a power tube is of an NMOS tube structure and generates and outputs an intermediate voltage Vdd1.
The second-stage voltage stabilizing circuit comprises at least one LDO circuit, and each LDO circuit adopts a single-tube amplifier structure and generates and outputs a power supply voltage Vout.
Through the cascade connection mode of the first-stage voltage stabilizing circuit and the second-stage voltage stabilizing circuit, low-noise high-power supply rejection ratio voltage output is finally realized at the output end of the voltage stabilizing power supply. Typically, the intermediate voltage Vdd1 is less than the supply voltage Vdd, and the supply voltage Vout is less than the intermediate voltage Vdd1. For example, the power supply voltage vdd=3.3v, the intermediate voltage vds1=1.8v, and the power supply voltage vout=1.1V.
As shown in fig. 3, in one embodiment of the present invention, the first stage voltage stabilizing circuit includes an operational amplifying unit, a feedback unit, and an output unit. The operational amplifier unit is a folding operational amplifier OP1, a power supply end of the operational amplifier is connected with a power supply voltage Vdd end, a non-inverting input end of the operational amplifier unit is connected with a first reference voltage Vin end, and output ends of the operational amplifier unit are respectively connected with input ends of the feedback unit and the output unit; the output end of the feedback unit is connected with the inverting input end of the operational amplifier OP1 (namely the operational amplifying unit); the output end of the output unit is used as the output end of the first-stage voltage stabilizing circuit and is connected with the second-stage voltage stabilizing circuit.
In one embodiment of the present invention, the operational amplifying unit is composed of a first PMOS tube PM0, a second PMOS tube PM1, a third PMOS tube PM2, and a fourth PMOS tube PM3, and a first NMOS tube NM0, a second NMOS tube NM1, a third NMOS tube NM2, a fourth NMOS tube NM3, a fifth NMOS tube NM4, a sixth NMOS tube NM5, and a seventh NMOS tube NM6, which together form a folded operational amplifier structure (OP 1). The sources of the first PMOS tube PM0 and the second PMOS tube PM1 are both connected to the power supply voltage Vdd, the gate of the seventh NMOS tube NM6 is connected to the first reference voltage Vin as the non-inverting input terminal of the operational amplifier OP1, the gate of the sixth NMOS tube NM5 is connected to the output terminal of the feedback unit as the inverting input terminal of the operational amplifier OP1, and the connection point of the drain of the fourth PMOS tube PM3 and the drain of the fourth NMOS tube NM3 is connected to the input terminals of the feedback unit and the output unit as the output terminal of the operational amplifier OP1, respectively.
In one embodiment of the present invention, the feedback unit is composed of an eighth NMOS transistor NM7 and a first feedback resistor R0. The drain electrode of the eighth NMOS transistor NM7 is connected to the power supply voltage Vdd, the gate electrode of the eighth NMOS transistor NM7 (i.e., the input end of the feedback unit) is connected to the output end of the operational amplifier OP1 and the input end of the output unit, and the source electrode of the eighth NMOS transistor NM7 (i.e., the output end of the feedback unit) is connected to the first feedback resistor R0 on one hand and the inverting input end of the operational amplifier OP1 on the other hand; the other end of the first feedback resistor R0 is connected with a ground potential end.
In one embodiment of the present invention, the output unit is composed of a ninth NMOS transistor NM8 and a first filter capacitor C0. The drain electrode of the ninth NMOS tube NM8 is connected to the power supply voltage Vdd, the gate electrode of the ninth NMOS tube NM8 (i.e., the input end of the output unit) is connected to the output end of the operational amplifier OP1 and the input end of the feedback unit, and the source electrode of the ninth NMOS tube NM8 is connected to the first filter capacitor C0 on one hand and the output end of the first stage voltage stabilizing circuit on the other hand; the other end of the first filter capacitor C0 is connected with the ground potential end.
In the first-stage voltage stabilizing circuit, the operational amplification unit and the feedback unit form a feedback structure, so that the source voltage of the eighth NMOS tube NM7 in the feedback unit is equal to the first reference voltage Vin input by the grid electrode of the seventh NMOS tube NM6 in the operational amplification unit, and the first reference voltage Vin does not change along with the change of the power supply voltage Vdd. In addition, since the operational amplification unit circuit and the feedback unit form a stable feedback path, the voltages of the nodes in the feedback path are stable, and therefore, the output voltage Va of the operational amplification unit, that is, the gate voltage of the eighth NMOS transistor NM7 in the feedback unit and the gate voltage of the ninth NMOS transistor NM8 in the output unit are also stable and do not change with the change of the power supply voltage Vdd.
At the output end of the first stage voltage stabilizing circuit, the intermediate voltage Vdd1 satisfies the following formula:
Vdd1＝Va－Vgs_nm8 (1)
where Va is the output voltage of the operational amplifier OP1, vgs_nr8 is the gate-source voltage value of the ninth NMOS transistor NM 8. The magnitude of the voltage vgs_nr8 is related to the magnitude of the output current of the ninth NMOS transistor NM8, so the magnitude of the intermediate voltage Vdd1 also varies with the magnitude of the output current. Since the output terminal of the first stage voltage stabilizing circuit only provides an intermediate voltage, the influence of certain fluctuation of the intermediate voltage Vdd1 is not great.
In the embodiment of the present invention, on the one hand, since the feedback network of the first-stage voltage stabilizing circuit only exists between the operational amplifying unit and the feedback unit, a corresponding frequency compensation network (not shown in fig. 3) is set to also exist between the operational amplifying unit and the feedback unit, so that the first-stage voltage stabilizing circuit obtains better stability even if the frequency compensation network adopts miller compensation, and the output unit is not affected. Further, since the frequency compensation network is only between the operational amplification unit and the feedback unit and is separated from the output unit circuit, the first filter capacitor C0 connected to the output end of the output unit can select a larger filter capacitor, and effectively filter the power supply Vdd and noise generated by the operational amplification unit and the feedback unit. The capacitance value of the first filter capacitor C0 may be designed to be greater than 100pF, and may be designed to be increased to 500pF or greater than 500pF according to the chip area.
On the other hand, since the power tube in the output unit of the first stage voltage stabilizing circuit adopts the ninth NMOS tube NM8, when the source end (i.e., the output end Vdd 1) is seen from the drain end (i.e., the power supply Vdd end) of the NMOS tube according to the characteristics of the NMOS tube, a large resistance state is presented, and compared with the state that the power tube adopts the PMOS tube in the prior art, the power supply rejection ratio performance can be effectively improved.
Meanwhile, as the operational amplifier unit of the first-stage voltage stabilizing circuit adopts the folding operational amplifier OP1, the folding operational amplifier can generate larger gain and improve the power supply rejection ratio performance at the low frequency of the LDO. The influence of the gain of the operational amplifier on the power supply rejection ratio performance at the low frequency of the LDO in the prior art is further improved.
As shown in fig. 4, in one embodiment of the present invention, the second stage voltage stabilizing circuit is an LDO circuit, which includes a current source unit, a bias voltage unit, and an amplifying output unit. The output end of the current source unit is connected with the input end of the bias voltage unit on one hand and the first input end of the amplifying output unit on the other hand; the output end of the bias voltage unit is connected with the third input end of the amplifying output unit, the second input end of the amplifying output unit is connected with the second reference voltage Vin1 end, and the output end of the amplifying output unit is connected with the output end of the LDO circuit.
In one embodiment of the present invention, the current source unit is composed of tenth PMOS transistor PM10 and eleventh PMOS transistor PM11, and tenth NMOS transistor NM10, eleventh NMOS transistor NM11, and tenth resistor R10. The source of the tenth PMOS tube PM10 and the source of the eleventh PMOS tube PM11 are both connected to the intermediate voltage Vdd1 end (i.e., the output end of the first stage voltage stabilizing circuit); the connection point of the drain of the eleventh PMOS tube PM11 and the drain of the eleventh NMOS tube NM11 is used as an output end of the current source unit, and is connected to the input end of the bias voltage unit and the first input end of the amplifying output unit, respectively.
In one embodiment of the present invention, the bias voltage unit is composed of a twelfth PMOS transistor PM12, a twelfth NMOS transistor NM12, and a thirteenth NMOS transistor NM 13. The gate of the twelfth PMOS tube PM12 (i.e., the input end of the bias voltage unit) is connected to the output end of the current source unit on the one hand, and is connected to the first input end of the amplifying output unit on the other hand, the source of the twelfth PMOS tube PM12 is connected to the middle voltage Vdd1 end (i.e., the output end of the first stage voltage stabilizing circuit), the drain of the twelfth PMOS tube PM12 (i.e., the output end of the bias voltage unit) is connected to the drain of the twelfth NMOS tube NM12 and the third input end of the amplifying output unit, the drain of the twelfth NMOS tube NM12 is connected to the gate in short circuit, the source of the twelfth NMOS tube NM12 is connected to the drain of the thirteenth NMOS tube NM13, the drain of the thirteenth NMOS tube NM13 is connected to the gate in short circuit, and the source of the thirteenth NMOS tube NM13 is connected to the ground potential end.
In one embodiment of the present invention, the amplifying output unit is composed of a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14, a fifteenth PMOS tube PM15, a fourteenth NMOS tube NM14, an eleventh resistor R11, and a second filter capacitor C10. The gate of the thirteenth PMOS tube PM13 (i.e., the first input end of the amplifying output unit) is connected to the output end of the current source unit and the input end of the bias voltage unit, the source of the thirteenth PMOS tube PM13 is connected to the middle voltage Vdd1 end (i.e., the output end of the first stage voltage stabilizing circuit), the drain of the thirteenth PMOS tube PM13 is connected to the gate of the fourteenth PMOS tube PM14 and the drain of the fourteenth NMOS tube NM14, the gate of the fourteenth NMOS tube NM14 (i.e., the second input end of the amplifying output unit) is connected to the second reference voltage Vin1 end, the source of the fourteenth NMOS tube NM14 is connected to the drain of the eleventh resistor R11 and the fifteenth PMOS tube PM15, and the other end of the eleventh resistor R11 is connected to the ground potential end; the grid electrode of the fifteenth PMOS tube PM15 (namely the third input end of the amplifying output unit) is connected with the output end of the bias voltage unit, and the source electrode of the fifteenth PMOS tube PM15 is connected with the drain electrodes of the second filter capacitor C10 and the fourteenth PMOS tube PM14 on one hand and the output end of the LDO circuit on the other hand; the other end of the second filter capacitor C10 is connected with a ground potential end; the source of the fourteenth PMOS PM14 is connected to the intermediate voltage Vdd1 terminal (i.e., the output terminal of the first stage voltage stabilizing circuit).
In the second-stage voltage stabilizing circuit, the current source unit is a typical current source circuit structure, and the gate voltages of the tenth NMOS transistor NM10 and the eleventh NMOS transistor NM11 are equal to each other, which is obtained by:
Vgs_nm11＝Vgs_nm10+Vr10 (2)
where vgs_nr11 is the gate-source voltage of the eleventh NMOS transistor NM11, vgs_nr10 is the gate-source voltage of the tenth NMOS transistor NM10, and Vr10 is the voltage across the tenth resistor R10.
As can be deduced from equation 2, the bias current I1 (i.e., the current flowing through the tenth resistor R10) output by the current source satisfies the following equation:
I1＝ (Vgs_nm11－Vgs_nm10)/ R10 (3)
wherein, R10 is the resistance value of tenth resistor R10. Since (vgs_nm 11-vgs_nr10) is the voltage difference Δvgs of the positive temperature coefficient, the bias current I1 is a current of the positive temperature coefficient. The bias current is copied by the twelfth PMOS tube PM12 of the bias unit, is injected into branches of the twelfth NMOS tube NM12 and the thirteenth NMOS tube NM13, generates bias voltage V1 at the drain electrode of the twelfth PMOS tube PM12, and the gate-source voltage Vgs of the twelfth NMOS tube NM12 and the thirteenth NMOS tube NM13 is the voltage with the negative temperature coefficient, so the bias voltage V1 is the bias voltage generated by overlapping the current with the positive temperature coefficient and the voltage with the negative temperature coefficient, the temperature coefficient is approximately zero, and the better temperature coefficient is realized.
In the amplifying output unit of the second-stage voltage stabilizing circuit, a thirteenth PMOS tube PM13, a fourteenth PMOS tube PM14 and a fifteenth PMOS tube PM15 form a single-tube amplifier, wherein the fifteenth PMOS tube PM15 is an input tube, the fourteenth PMOS tube PM14 is a cascade (cascade) tube for improving the gain of single-tube input, and the thirteenth PMOS tube PM13 is a load tube. The output end of the single-tube amplifier is connected to the grid electrode of the fourteenth NMOS tube NM14 (namely, the power tube), and an LDO structure is formed. The output end Vout of the LDO is connected with the source electrode of the fifteenth PMOS tube PM15, a closed-loop negative feedback structure is formed, and the stability of output voltage is ensured. Compared with an LDO circuit adopting a double-tube structure amplifier in the prior art, the second-stage voltage stabilizing circuit in the embodiment of the invention adopts a single-tube amplifier structure, the number of transistors in the circuit is reduced by half, and flicker noise and thermal noise generated by the device can be effectively reduced.
According to the analysis of the working principle, the voltage-stabilized power supply provided by the embodiment of the invention realizes voltage output with low noise and high power supply rejection ratio at the output end of the voltage-stabilized power supply through the cascade connection mode of stacking the first-stage voltage-stabilized circuit and the second-stage voltage-stabilized circuit.
In order to verify the excellent performance of the regulated power supply provided by the embodiment of the invention, the inventor respectively performs simulation tests of the power supply rejection ratio and noise on the regulated power supply and the prior art scheme, and the test results are as follows.
The simulation test result of the power supply rejection ratio is shown in fig. 5, wherein the abscissa indicates the working frequency and the ordinate indicates the power supply rejection ratio. As can be seen from the figure, by adopting the technical scheme provided by the embodiment of the invention, the power supply rejection ratio performance of the stabilized power supply is better than that of the prior art, and particularly, the power supply rejection ratio performance of the technical scheme provided by the embodiment of the invention is more remarkable in improving effect in the range of 1 MHz-100 MHz.
The simulation test result of the noise is shown in fig. 6, wherein the abscissa of the figure is the working frequency, and the ordinate is the noise. As can be seen from the figure, by adopting the technical scheme provided by the embodiment of the invention, the noise performance of the regulated power supply is superior to that of the prior art, and particularly, the frequency is within the range of below 10 KHz.
In addition, according to specific requirements of the IC chips of various application types on the number of power supplies, the second stage voltage stabilizing circuit in the voltage stabilizing power supply provided by the embodiment of the invention may further include a mode of parallel connection of two or more identical LDOs, so as to provide a plurality of power supplies for the application circuit. As shown in FIG. 7, the second stage voltage stabilizing circuit comprises LDO21 and LDO22 … … LDO2n, wherein the circuit structures of LDO21 and LDO22 … … LDO2n are the same (as shown in FIG. 4), and the power supply ends of the second stage voltage stabilizing circuit are connected with the output end of the first stage voltage stabilizing circuit.
The embodiment of the invention also provides electronic equipment, which comprises the low-noise high-power supply rejection ratio stabilized power supply, wherein the stabilized power supply is used as a power supply component for providing power supply for an application integrated circuit in the electronic equipment. As shown in fig. 8, the electronic device at least includes a processor, a memory, a power supply assembly, and further includes a communication assembly, a sensor assembly, a multimedia assembly, an input/output interface, etc. according to actual needs. The memory, the communication component, the sensor component, the power component, the multimedia component and the input/output interface are all connected with the processor. The memory may be a Static Random Access Memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc., and the processor may be a Central Processing Unit (CPU), a Graphics Processor (GPU), a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Digital Signal Processing (DSP) chip, etc. Other communication components, sensor components, multimedia components, etc. may be implemented using common components and are not specifically described herein.
In summary, compared with the prior art, the low-noise high-power supply rejection ratio voltage-stabilized power supply provided by the invention adopts a two-stage LDO stacking structure, namely, the cascade connection of the first-stage voltage-stabilizing circuit and the second-stage voltage-stabilizing circuit, and finally, the low-noise high-power supply rejection ratio voltage output is realized at the output end of the voltage-stabilized power supply. The first-stage voltage stabilizing circuit adopts the technical scheme that the output unit and the feedback unit are arranged separately, so that the output end can be provided with a larger filter capacitor, and noise generated by a power supply and the LDO is reduced. Meanwhile, by adopting the technical scheme that the folding operational amplifier structure and the power tube in the output unit adopts the NMOS tube, the power supply rejection ratio and the noise performance of the first-stage voltage stabilizing circuit are improved. The second-stage voltage stabilizing circuit further effectively reduces noise generated by the LDO by adopting the technical scheme of a single-tube amplifier. Therefore, the low-noise high-power supply rejection ratio stabilized power supply has the beneficial effects of excellent power supply performance and the like, and can provide a power supply with excellent performance for VCO and various application IC chips.
It should be noted that the above embodiments are only examples, and the technical solutions of the embodiments may be combined, which are all within the protection scope of the present invention.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
The low-noise high-power supply rejection ratio regulated power supply and the electronic device provided by the invention are described in detail above. Any obvious modifications to the present invention, without departing from the spirit thereof, would constitute an infringement of the patent rights of the invention and would take on corresponding legal liabilities.

Claims (12)

1. The low-noise high-power supply rejection ratio stabilized voltage power supply is characterized by comprising a first-stage stabilized voltage circuit and a second-stage stabilized voltage circuit; wherein,,
the power supply voltage (Vdd) terminal is connected to the power supply terminal of the first stage voltage stabilizing circuit, the output terminal of the first stage voltage stabilizing circuit is connected to the power supply terminal of the second stage voltage stabilizing circuit, and the output terminal of the second stage voltage stabilizing circuit is connected to the output terminal of the voltage stabilizing power supply;
the first-stage voltage stabilizing circuit is an LDO circuit, is arranged separately from the output unit by adopting a feedback network, and is of an NMOS tube structure, and generates and outputs an intermediate voltage (Vdd 1); the second-stage voltage stabilizing circuit comprises at least one LDO circuit, each LDO circuit adopts a structure of a single-tube amplifier and generates and outputs a power supply voltage (Vout); through cascade connection of the first-stage voltage stabilizing circuit and the second-stage voltage stabilizing circuit, low-noise high-power supply rejection ratio voltage output is realized at the output end of the voltage stabilizing power supply.
2. The regulated power supply of claim 1, wherein:
the first-stage voltage stabilizing circuit comprises an operational amplification unit, a feedback unit and an output unit; wherein,,
the power end of the operational amplification unit is connected with a power voltage (Vdd) end, the non-inverting input end of the operational amplification unit is connected with a first reference voltage end, and the output end of the operational amplification unit is respectively connected with the input ends of the feedback unit and the output unit; the output end of the feedback unit is connected with the inverting input end of the operational amplification unit; and the output end of the output unit is connected with the second-stage voltage stabilizing circuit.
3. The regulated power supply of claim 2, wherein:
the operational amplifier unit adopts a folding operational amplifier structure.
4. The regulated power supply of claim 2, wherein:
the feedback unit consists of an eighth NMOS tube (NM 7) and a first feedback resistor (R0); wherein,,
the drain electrode of the eighth NMOS tube (NM 7) is connected with a power supply voltage (Vdd) end, the grid electrode of the eighth NMOS tube (NM 7) is connected with the output end of the operational amplifying unit and the input end of the output unit, and the source electrode of the eighth NMOS tube (NM 7) is connected with a first feedback resistor (R0) and the inverting input end of the operational amplifying unit; the other end of the first feedback resistor (R0) is connected with a ground potential end.
5. The regulated power supply of claim 2, wherein:
the output unit consists of a ninth NMOS tube (NM 8) and a first filter capacitor (C0); wherein,,
the drain electrode of the ninth NMOS tube (NM 8) is connected with a power supply voltage (Vdd) end, the grid electrode of the ninth NMOS tube (NM 8) is connected with the output end of the operational amplifying unit and the input end of the feedback unit, the source electrode of the ninth NMOS tube (NM 8) is connected with a first filter capacitor (C0) and the output end of the first stage voltage stabilizing circuit, and the other end of the first filter capacitor (C0) is connected with a ground potential end.
6. The regulated power supply of claim 5, wherein:
the capacitance value of the first filter capacitor C0 is not less than 100pF.
7. The regulated power supply of claim 1, wherein:
each LDO circuit in the second-stage voltage stabilizing circuit has the same structure and comprises a current source unit, a bias voltage unit and an amplifying output unit; wherein,,
the output end of the current source unit is connected with the input end of the bias voltage unit and the first input end of the amplifying output unit; the output end of the bias voltage unit is connected with the third input end of the amplifying output unit; and the second input end of the amplifying output unit is connected with a second reference voltage end, and the output end of the amplifying output unit is connected with the output end of the LDO circuit.
8. The regulated power supply of claim 7, wherein:
the bias voltage unit consists of a twelfth PMOS tube (PM 12), a twelfth NMOS tube (NM 12) and a thirteenth NMOS tube (NM 13); wherein,,
the grid of a twelfth PMOS tube (PM 12) is connected with the output end of the current source unit and the first input end of the amplifying output unit, the source electrode of the twelfth PMOS tube (PM 12) is connected with the output end of the first-stage voltage stabilizing circuit, the drain electrode of the twelfth PMOS tube (PM 12) is connected with the drain electrode of the twelfth NMOS tube (NM 12) and the third input end of the amplifying output unit, the drain electrode of the twelfth NMOS tube (NM 12) is connected with the grid in a short circuit mode, the source electrode of the twelfth NMOS tube (NM 12) is connected with the drain electrode of the thirteenth NMOS tube (NM 13) in a short circuit mode, the drain electrode of the thirteenth NMOS tube (NM 13) is connected with the grid in a short circuit mode, and the source electrode of the thirteenth NMOS tube (NM 13) is connected with the ground potential end.
9. The regulated power supply of claim 7, wherein:
the amplifying output unit consists of a thirteenth PMOS tube (PM 13), a fourteenth PMOS tube (PM 14) and a fifteenth PMOS tube (PM 15), and a fourteenth NMOS tube (NM 14), an eleventh resistor (R11) and a second filter capacitor (C10); wherein,,
the thirteenth PMOS tube (PM 13), the fourteenth PMOS tube (PM 14) and the fifteenth PMOS tube (PM 15) form a single-tube amplifier, wherein the fifteenth PMOS tube (PM 15) is an input tube, the fourteenth PMOS tube (PM 14) is a cascade tube, and the thirteenth PMOS tube (PM 13) is a load tube.
10. The regulated power supply of claim 9, wherein:
in the amplifying output unit, a grid electrode of a thirteenth PMOS tube (PM 13) is connected with an output end of the current source unit and an input end of the bias voltage unit, a source electrode of the thirteenth PMOS tube (PM 13) is connected with an output end of the first-stage voltage stabilizing circuit, a drain electrode of the thirteenth PMOS tube (PM 13) is connected with a grid electrode of a fourteenth PMOS tube (PM 14) and a drain electrode of a fourteenth NMOS tube (NM 14), a grid electrode of the fourteenth NMOS tube (NM 14) is connected with the second reference voltage end, a source electrode of the fourteenth NMOS tube (NM 14) is connected with an eleventh resistor (R11) and a drain electrode of the fifteenth PMOS tube (PM 15), and the other end of the eleventh resistor (R11) is connected with a ground potential end; the grid electrode of the fifteenth PMOS tube (PM 15) is connected with the output end of the bias voltage unit, and the source electrode of the fifteenth PMOS tube (PM 15) is connected with the drain electrode of the second filter capacitor (C10) and the fourteenth PMOS tube (PM 14) and the output end of the amplifying output unit; the other end of the second filter capacitor (C10) is connected with a ground potential end; the source electrode of the fourteenth PMOS tube (PM 14) is connected with the output end of the first-stage voltage stabilizing circuit.
11. The regulated power supply of claim 1, wherein:
the second-stage voltage stabilizing circuit adopts two or more LDOs with the same structure and is used for providing two or more power supplies for the application circuit; the power end of each LDO is connected with the output end of the first-stage voltage stabilizing circuit.
12. An electronic device comprising the regulated power supply of any one of claims 1 to 11.
CN202310178431.6A 2023-02-28 Low-noise high-power supply rejection ratio stabilized voltage power supply and electronic equipment Active CN116774767B (en)

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CN103455076A (en) * 2013-09-12 2013-12-18 福建一丁芯光通信科技有限公司 High power supply rejection LDO voltage stabilizer based on native NMOS transistor
CN106155157A (en) * 2015-05-15 2016-11-23 亚德诺半导体集团 Comprise circuit and the technology of cascade LDO regulation and control
CN110837268A (en) * 2019-12-10 2020-02-25 复旦大学 Two-stage low dropout linear regulator with low noise and high power supply rejection ratio

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100109435A1 (en) * 2008-09-26 2010-05-06 Uti Limited Partnership Linear Voltage Regulator with Multiple Outputs
CN102239457A (en) * 2008-12-09 2011-11-09 高通股份有限公司 Low drop-out voltage regulator with wide bandwidth power supply rejection ratio
CN103455076A (en) * 2013-09-12 2013-12-18 福建一丁芯光通信科技有限公司 High power supply rejection LDO voltage stabilizer based on native NMOS transistor
CN106155157A (en) * 2015-05-15 2016-11-23 亚德诺半导体集团 Comprise circuit and the technology of cascade LDO regulation and control
CN110837268A (en) * 2019-12-10 2020-02-25 复旦大学 Two-stage low dropout linear regulator with low noise and high power supply rejection ratio

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