KR102138770B1 - Buffer circuit, amplifier and regulator with high stability and fast response - Google Patents

Abstract

This embodiment relates to a buffer circuit, an amplifier and a regulator. An aspect of the present embodiment, the first input signal and the second input signal, a gain stage for generating a first output signal by amplifying the difference between the first input signal and the second input signal; And an output stage that receives and amplifies the first output signal to generate a second output signal and outputs it through an output terminal, wherein the output stage comprises: a bias generator that generates a first bias voltage; A bias adjusting unit receiving the first bias voltage and generating and outputting a second bias voltage; And an output unit receiving the second bias voltage and generating the second output signal using a bias current corresponding to the second bias voltage.

Description

Buffer circuit, amplifier and regulator with high stability and fast response characteristics{BUFFER CIRCUIT, AMPLIFIER AND REGULATOR WITH HIGH STABILITY AND FAST RESPONSE}

The present invention relates to buffer circuits, amplifiers and regulators. More particularly, it relates to a buffer circuit, an amplifier and a regulator having high stability and fast response characteristics.

A regulator is a device used to provide a stable output voltage in various electronic devices. In particular, the Low Drop Out Regulator (hereinafter referred to as LDO) is a portable, battery-operated battery such as a cell phone, a wireless phone, a pager, a personal digital assistants (PDA), a portable personal computer, a camcorder, and a digital camera. It has been widely used to generate stable voltage with high efficiency in a device.

The LDO regulator features a low drop out voltage. That is, when the LDO regulator receives an unregulated input voltage received from a power source such as a battery and provides a regulated output voltage, the difference between the input voltage and the output voltage can be minimized. Minimizing the dropout voltage means increasing power efficiency and reducing energy consumption. Therefore, LDO' regulator is widely used in applications requiring low power. In particular, it can be said that the usefulness is greater in applications that require long-term operation from batteries, such as portable devices. For this reason, an increase in demand for portable devices directly leads to an increase in demand for LDO regulators.

A large-capacity pass transistor can be used to improve the driving capability of the regulator. A large-capacity pass transistor includes a large parasitic capacitance, and a circuit having a low output impedance, so-called Super Source Follow (SSF) can be used inside the amplifier to properly drive the large-capacity pass transistor. Low output impedance can be achieved by the negative feedback loop, and the additional effect of the negative feedback loop can improve the sink or sourcing capability of the output stage depending on the circuit configuration. However, the phase margin may be reduced by the feedback loop, which may cause a problem that stability is deteriorated. In addition, a circuit such as SSF has excellent current sinking ability from the output terminal, but the ability to supply current to the output terminal is relatively insufficient, thereby increasing the buffer circuit output voltage (i.e., amplifier output voltage). There is a problem that it is slow. In addition, if the amplifier is not properly designed, there is a problem that power supply noise affects the regulator output through the pass transistor.

The present invention can provide a buffer circuit, an amplifier and a regulator having high stability, fast response characteristics, and/or excellent power supply noise canceling performance.

One aspect of the present invention for achieving the above object, a reference voltage generation circuit for generating and outputting a reference voltage; An amplifier for receiving a first input signal corresponding to an output voltage and a second input signal corresponding to the reference voltage, and outputting an output signal amplifying the difference between the first input signal and the second input signal; And a pass transistor for adjusting the output voltage in response to the output signal of the amplifier, wherein the amplifier includes an output stage for generating the output signal, and the output stage is for generating a bias for generating a first bias voltage. part; A bias adjusting unit receiving the first bias voltage and generating and outputting a second bias voltage; And an output unit receiving the second bias voltage and generating the output signal using a bias current corresponding to the second bias voltage. The second bias voltage in the rising section of the amplifier output signal includes the It is a regulator characterized by being lower than the first bias voltage.

delete

delete

In the regulator, the second bias voltage may reduce the high frequency component of power supply noise compared to the first bias voltage so that the high frequency component of the power supply noise is increased in the amplifier output signal.

In the regulator, the bias adjusting unit may lower a peak at a unit gain frequency (UGF) of an output signal transfer function for an input signal of the output stage.

In the regulator, the bias adjustment unit, a resistor connected between the first bias voltage and the second bias voltage; And a capacitor connected between the feedback signal provided from the output unit and the second bias voltage.

In the regulator, the amplifier further includes a gain stage that amplifies the difference between the first input signal and the second input signal and provides it to the output stage, and the feedback signal increases in the output signal of the gain stage. When you can descend.

In the regulator, the resistor may be implemented as a transistor.

In the regulator, the output stage may further include a power supply noise feedforward unit that transmits a low frequency component of power supply noise to the output terminal.

In the regulator, the output unit may include a transconductance boost stage that reduces the output impedance.

Another aspect of the present invention, a gain stage for receiving a first input signal and a second input signal, amplifying the difference between the first input signal and the second input signal to generate a first output signal; And an output stage that receives and amplifies the first output signal to generate a second output signal and outputs it through an output terminal, wherein the output stage comprises: a bias generator that generates a first bias voltage; A bias adjusting unit receiving the first bias voltage and generating and outputting a second bias voltage; And an output unit receiving the second bias voltage and generating the second output signal using a bias current corresponding to the second bias voltage. The bias generator comprises a first connected in series between power and ground. 1 transistor and a current source, and the output unit includes a second transistor, a third transistor, and a fourth transistor connected in series between the power supply and the ground, and the bias adjusting unit includes a gate of the first transistor and the first An amplifier comprising a resistor connected between the gates of the two transistors and a capacitor connected between the gate of the second transistor and the drain of the third transistor.

delete

In the amplifier, the resistor may be implemented as a transistor.

In the amplifier, the output unit may further include a fifth transistor connected between the output terminal and the ground.

In the amplifier, the output stage may further include a power supply noise feedforward unit that transmits a low frequency component of power supply noise to the output unit.

Another aspect of the present invention, a buffer circuit for generating an output signal amplifying an input signal and outputting it through an output node, comprising: a first transistor having a source connected to a power source and a gate and a drain connected to each other; A current source connected between the drain and ground of the first transistor; A second transistor having a source connected to the power supply and a drain connected to the output node; A third transistor having a source connected to the output node, a drain connected to a first node, and receiving the input signal through a gate; A fourth transistor having a drain connected to the first node and a source connected to the ground; A fifth transistor having a gate connected to the first node, a drain connected to the output node, and a source connected to the ground; A resistor connected between the gate of the first transistor and the gate of the second transistor; And a capacitor connected between the gate of the second transistor and the first node.

In the buffer circuit, the resistor may be a sixth transistor having a source connected to a gate of the first transistor and a gate and a drain connected to the gate of the second transistor.

The buffer circuit according to the present embodiment may improve stability, transient response characteristics, and/or power supply noise removal performance. The regulator according to this embodiment can improve stability, transient response characteristics, and/or power supply noise rejection performance by using an amplifier including such a buffer circuit.

1 is a view schematically illustrating a regulator according to an embodiment of the present invention.
2 is a block diagram schematically illustrating an amplifier according to an embodiment.
3 is a block diagram schematically illustrating the output stage of an amplifier according to an embodiment.
4 is a diagram illustrating an output stage circuit of an amplifier according to an embodiment.
5 is a diagram illustrating an operation waveform of the output stage circuit according to the embodiment of FIG. 4.
Fig. 6 is a diagram illustrating the output stage circuit of the amplifier as a comparative example compared to the embodiment of the present invention.
7 is a diagram illustrating an operation waveform of the output stage circuit according to the comparative example of FIG. 6.
8 is a view for explaining power supply noise removal characteristics of the output stage circuit according to the embodiment of FIG. 4.
9 is a view for explaining power supply noise removal characteristics of the output stage circuit according to the comparative example of FIG. 6.
10 is a diagram illustrating an equivalent circuit for analyzing the stability of the output stage circuit according to the comparative example of FIG. 6.
FIG. 11 is a diagram illustrating a loop gain and an input-output transfer function of the output stage circuit according to the comparative example of FIG. 6.
12 is a diagram illustrating an equivalent circuit for analyzing the stability of the output stage circuit according to the embodiment of FIG. 4.
13 is a diagram illustrating a loop gain and an input-output transfer function of the output stage circuit according to the embodiment of FIG. 4 in comparison with a comparative example.
14 is a diagram illustrating an output stage circuit of an amplifier according to an embodiment of the present invention.
15 is a block diagram schematically illustrating the output stage of an amplifier according to an embodiment of the present invention.
16 is a diagram illustrating an output stage circuit of an amplifier according to an embodiment of the present invention.
17 is a diagram illustrating a buffer circuit according to an embodiment.

Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. It should be noted that in adding reference numerals to the components of each drawing, the same components have the same reference numerals as possible, even if they are displayed on different drawings. In addition, in describing the present invention, when it is determined that detailed descriptions of related well-known structures or functions may obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), and (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, or order of the component is not limited by the term. When a component is described as being "connected", "coupled" or "connected" to another component, that component may be directly connected to or connected to the other component, but another component between each component It should be understood that elements may be "connected", "coupled" or "connected".

1 is a view schematically illustrating a regulator according to an embodiment of the present invention.

Referring to FIG. 1, the regulator 10 may include an amplifier 100, a reference voltage generation circuit 200, a pass transistor 300, and an output voltage detector 400.

The regulator 10 may provide a power supply voltage Vdd through the input terminal A and an output voltage Vout to the load through the output terminal B.

The reference voltage generation circuit 200 may generate and output a reference voltage Vref. For example, the reference voltage generation circuit 200 may operate using the power source voltage Vdd as a power source or may receive both the power source voltage Vdd and the output voltage Vout and selectively use the power source. As the reference voltage generation circuit 200, a circuit commonly referred to as a band gap reference (BGR) may be used.

The amplifier 100 receives the first input signal Vin1 corresponding to the output voltage Vout and the second input signal Vin2 corresponding to the reference voltage Vref, and the first input signal Vin1 and the second The output signal Vao amplifying the difference between the input signals Vin2 may be output. For example, the first input signal Vin1 of the amplifier 100 may be a voltage at which the output voltage Vout is divided by the output voltage detector 400. For example, the second input signal Vin2 of the amplifier 100 may be a voltage corresponding to the reference voltage Vref generated by the reference voltage generation circuit 200. The reference voltage Vref output from the reference voltage generation circuit 200 may be directly used as the second input signal Vin2 of the amplifier 100 without additional processing, but may be removed from the amplifier 100 after a predetermined process. It can also be used as an input signal (Vin2). The amplifier 100 may operate using a power supply voltage Vdd as a power supply.

The pass transistor 300 may adjust the output voltage Vout in response to the amplifier output signal Vao. Adjustment of the output voltage (Vout) by the pass transistor 300, adjustment of the current flowing from the input terminal (A) to the output terminal (B) or the voltage drop between the power supply voltage (Vdd) and the output voltage (Vout) Alternatively, it may be understood that it is performed by adjusting the impedance inside the pass transistor 300. In the pass transistor 300, a first terminal (eg, source) is connected to a power supply voltage (Vdd), a second terminal (eg, drain) is connected to an output voltage (Vout), and a third terminal (eg, a gate). Can be connected to the amplifier output signal (Vao). 1, the pass transistor MP is illustrated as a P-type FET, but the present embodiment is not limited thereto.

The output voltage detector 400 may generate a voltage corresponding to the output voltage Vout and feed it back to the amplifier 100. For example, the output voltage detector 400 may provide a voltage obtained by dividing the output voltage Vout as the first input signal Vin1 of the amplifier. In FIG. 1, the output voltage detector 400 is illustrated as a resistance voltage divider including two resistors R1 and R2, but the present invention is not limited thereto, and other types of voltage divider circuits or detection circuits may be used.

In the configuration as shown in FIG. 1, when the gain of the amplifier 100 is large, the two input signals Vin1 and Vin2 of the amplifier 100 may have substantially the same magnitude. For example, the amplifier 100 drives the pass transistor 300 such that the voltage Vin1 divided by the output voltage Vout and the reference voltage Vref have the same size, and thus the output voltage Vout is It may be adjusted to a size corresponding to the reference voltage Vref.

2 is a block diagram schematically illustrating an amplifier according to an embodiment.

Referring to FIG. 2, the amplifier 100 may include a gain stage 110 and an output stage 120.

The gain stage 110 receives the first input signal Vin1 and the second input signal Vin2, amplifies the difference between the first input signal Vin1 and the second input signal Vin2, and amplifies the first output signal ( Vgso).

The output stage 120 may receive the first output signal Vgso from the gain stage 110 and generate the second output signal Vao and output it through the output terminal. The second output signal Vao may be a signal that amplifies or buffers the first output signal Vgso. The second output signal Vao output by the output stage 120 may be an output signal of the amplifier 100.

For example, the gain gain of the gain stage 110 may have a larger value than the gain gain of the output stage 120. For example, the output impedance of the output stage 120 may have a smaller value than the output impedance of the gain stage 110. In this case, the gain stage 110 is mainly responsible for the gain amplification function of the amplifier 100, and the output stage 120 can be mainly responsible for the function of lowering the output impedance of the amplifier 100. For example, the output stage 120 lowers the output impedance but the voltage amplification factor is set similar to 1 to operate as a buffer. In this case, the output stage 120 may include a buffer circuit.

3 is a block diagram schematically illustrating an output stage inside an amplifier according to an embodiment.

Referring to FIG. 3, the output stage 120 may include a bias generation unit 121, a bias adjustment unit 122, and an output unit 123.

The bias generator 121 may generate a first bias voltage Vb1.

The bias adjusting unit 122 may receive the first bias voltage Vb1 from the bias generator 121 and generate and output the second bias voltage Vb2. The bias adjusting unit 122 may receive the feedback signal Vn1 from the output unit 123 and adjust the second bias voltage Vb2 using the feedback signal Vn1. In this embodiment, the bias adjusting unit 122 adjusts the second bias voltage Vb2 by using the feedback signal Vn1, so that the transient response, stability, and/or power supply rejection (PSR) performance of the amplifier is achieved. Can improve. This will be described in detail below.

The output unit 123 receives an input signal Vgso from an external (eg, gain stage), receives a second bias voltage Vb2 from the bias adjustment unit 122, and corresponds to the second bias voltage Vb2. The output signal Vao may be generated using the bias current.

4 is a diagram illustrating an output stage circuit of an amplifier according to an embodiment. In addition to the output stage 120 of the amplifier, a reference voltage generation circuit 200, an amplifier gain stage 110, a pass transistor 300, and an output voltage detector 400 are also shown. Other configurations than stage 120 are shown briefly.

The output stage 120 may include a bias generation unit 121, a bias adjustment unit 122, and an output unit 123. As described above, the output stage 120 can operate as a buffer.

The bias generator 121 may generate a first bias voltage Vb1. To this end, the bias generator 121 may include a first transistor M1 and a current source Ibias connected in series between the power supply Vdd and the ground GND. The source of the first transistor M1 is connected to the power supply Vdd, and the gate and drain are interconnected to be connected to the current source Ibias. The current source Ibias may be connected between the drain of the first transistor M1 and the ground GND. The current source causes the bias current Ibias to flow through the first transistor M1, so that a first bias voltage Vb1 corresponding to the bias current Ibias may be generated at the gate of the first transistor M1. have. The first bias voltage Vb1 may be provided to the bias adjusting unit 122.

The output unit 123 may include a second transistor M2 to a fifth transistor M5.

The source of the second transistor M2 is connected to the power supply Vdd, the drain of the second transistor M2 is connected to the output node n0, and the gate of the second transistor M2 is the bias adjusting unit 122 It may be connected to the second bias voltage (Vb2) output. The second transistor M2 may supply a bias current I1 corresponding to the second bias voltage Vb2 to the output node n0.

The source of the third transistor M3 is connected to the output node n0, the drain of the third transistor M3 is connected to the first node n1, and the gate of the third transistor M3 is the output stage 120 ). For example, the input signal connected to the gate of the third transistor M3 may be the output signal Vgso of the gain stage 110. The third transistor M3 may allow the current I21 to flow from the output node n0 to ground GND. The current I21 flowing through the third transistor M3 may be changed in response to the output signal Vgso of the gain stage 110.

The drain of the fourth transistor M4 is connected to the first node n1, the source of the fourth transistor M4 is connected to the ground GND, and the gate of the fourth transistor M4 is the bias signal Vbn. Can be connected to. The drain of the fifth transistor M5 is connected to the drain of the second transistor M2 (that is, the output node n0), the source of the fifth transistor M5 is connected to the ground GND, and the fifth transistor The gate of M5 may be connected to the first node n1. The fifth transistor M5 allows the current I22 to flow from the output node n0 to the ground GND in response to the first node voltage Vn1, thereby increasing transconductance and lowering the output impedance. . For this reason, the fourth transistor M4 and the fifth transistor M5 are also referred to as a transconductance boost stage.

The voltage Vn1 of the first node n1, in which the drain of the third transistor M3 and the drain of the fourth transistor M4 are interconnected, is moved in the opposite direction to the output signal Vgso of the gain stage Vgso. Can. For example, the voltage Vn1 of the first node n1 may have a form in which the output signal Vgso of the gain stage Vgso is inverted. The voltage Vn1 of the first node n1 may be fed back to the bias adjusting unit 122.

The output unit 123 configured as described above may be referred to as an SSF (Super Source Follower) due to its large driving capability and low output impedance.

The bias adjusting unit 122 is provided with a first bias voltage Vb1 from the bias generating unit 121, a feedback signal is provided from the output unit 123, and a second bias voltage is supplied to the output unit 123. (Vb2). The feedback signal may be a signal that moves against the change of the input signal Vgso. For example, the feedback signal may be the first node voltage Vn1.

The bias adjusting unit 122 may include a resistor Rs connected between the first bias voltage Vb1 and the second bias voltage Vb2 and a capacitor Cs connected between the second bias voltage Vb2 and the feedback signal. Can. For example, the resistor Rs is connected between the gate of the first transistor M1 and the gate of the second transistor M2, and the capacitor Cs is the gate of the second transistor M2 and the first node n1 ). Here, the resistor Rs may be implemented as an actual resistor or may be implemented to operate like a resistor using another device. For example, when a resistor Rs is implemented using a semiconductor transistor, there is an advantage in that the size is reduced and manufacturing is easy.

The bias adjusting unit 122 arranges a resistor Rs between the first bias voltage Vb1 and the second bias voltage Vb2, so that the second bias voltage Vb2 to be used by the output unit 123 is a bias generator The first bias voltage Vb1 generated by 121 may be influenced, but the two bias voltages Vb1 and Vb2 may be temporarily changed. In addition, the bias adjusting unit 122 includes a capacitor Cs coupling the first node voltage Vn1 and the second bias voltage Vb2, so that the bias adjustment unit 122 is dependent on the first node voltage Vn1 of the output unit 123. The second bias voltage Vb2 may be affected. Due to these characteristics of the bias adjustment unit 122, the transient characteristics, stability and/or PSR characteristics of the amplifier 100 may be improved. This part will be described in detail below.

4 illustrates the case where the circuit according to the present embodiment is used as the output stage 120 of the amplifier, the circuit according to the present embodiment can be used for other applications as a buffer circuit.

FIG. 5 is a diagram illustrating an operation waveform of the output stage 120 of FIG. 4. 5 shows the output signal of the gain stage 110 (Vgso, that is, the input signal of the output stage), the first node voltage Vn1, the second bias voltage Vb2, and the output signal of the output stage Vao in order. It is done. Hereinafter, the operation of the output stage circuit will be described with reference to FIGS. 4 and 5.

It is assumed that the output signal Vgso of the gain stage 110 switches between a low state and a high state at times t1, t2, t3, and t4. Here, the low state and the high state can be understood as two states for examining response characteristics in the transient state.

When the output signal Vgso of the gain stage 110 is inverted from the low state to the high state at the time t1, the first node voltage Vn1 is output by the third transistor M3 by the third transistor M3. ) May be inverted from a high state to a low state in an inverted form. The first node voltage Vn1 is connected to the second bias voltage Vb2 through the capacitor Cs, and since the capacitor Cs voltage cannot change instantaneously (that is, it cannot be discontinuous), the second bias The voltage Vb2 reflects the sudden change of the first node voltage Vn1, and the second bias voltage Vb2 also drops sharply at t1 and gradually increases. Since the first bias voltage Vb1 is constant (a constant current flows in the current source Ibias, the first bias voltage Vb1 is also kept constant), the second bias voltage Vb2 gradually decreases as time elapses from t1. It rises to approach 1 bias voltage Vb1.

The output signal Vao of the output stage 120 starts rising at t1 corresponding to the output signal Vgso of the gain stage 110. The rise of the output signal Vao of the output stage 120 depends on the current I1 supplied from the second transistor M2. That is, the greater the current I1 supplied from the second transistor M2, the faster the output signal Vao of the output stage 120 can rise. According to the present exemplary embodiment, the current supplied to the output node n0 through the second transistor M2 at t1 is the second bias voltage Vb2 at the time t1 because the second bias voltage Vb2 is sharply lower than the first bias voltage Vb1. I1) may be increased (compared to the case where the first bias voltage Vb1 is applied to the second transistor M2 as it is). That is, while the second bias voltage Vb2 maintains a lower value than the first bias voltage Vb1, the current I1 supplied to the output node n0 through the second transistor M2 may increase, Due to this, the rising speed of the output signal Vao may increase.

When the output signal Vgso of the gain stage 110 is inverted from a high state to a low state at a time t2, the first node voltage Vn1 is output from the gain stage 110 by the third transistor M3. ) Is inverted to be inverted from low to high. The sudden rise of the first node voltage Vn1 is reflected in the second bias voltage Vb2 through the capacitor Cs, and the second bias voltage Vb2 also rises rapidly at t2 and then gradually decreases and decreases the first bias voltage ( Vb1).

The output signal Vao of the output stage 120 starts to fall at t2 corresponding to the output signal Vgso of the gain stage 110. The output signal Vao of the output stage 120 rapidly decreases as the current I21 flowing through the third transistor M2 and the current I22 flowing through the fifth transistor M5 increase, and the second transistor ( The larger the current I1 supplied to the output node n0 through M2), the slower the fall. According to the present embodiment, since the second bias voltage Vb2 is higher than the first bias voltage Vb1 at time t2, the current I1 supplied to the output node n0 through the second transistor M2 is As it becomes smaller, the output signal Vao may fall faster. That is, while the second bias voltage Vb2 maintains a higher value than the first bias voltage Vb1, the current I1 supplied to the output node n0 through the second transistor M2 may be small. , Due to this, the descending speed of the output signal Vao may increase.

As described above, in the present embodiment, the transient characteristic of the output signal Vao can be improved by making the second bias voltage Vb2 different from the first bias voltage Vb1 in the change section of the output signal Vao. . To this end, illustratively, the bias adjusting unit 122 uses a feedback signal (eg, a first node voltage) moving opposite to the input signal Vgso, to increase the second bias voltage in the rising section of the output signal Vao ( Vb2) increases the current (I1) supplied to the output node (n0) by having a lower value than the first bias voltage (Vb1), and the second bias voltage (Vb2) in the falling section of the output signal (Vao) By having a value higher than that of the first bias voltage Vb1, the current I1 supplied to the output node n0 can be reduced. Since the current supply capability of the second transistor M2 is relatively weak compared to the current sink capability of the third to fifth transistors M3 to M5, the effect of improving the transient characteristics according to this embodiment is output. In the rising section of the signal Vao, a greater effect can be exhibited.

FIG. 6 is a diagram illustrating an output stage circuit of an amplifier as a comparative example compared to an embodiment of the present invention, and FIG. 7 is a diagram illustrating an operation waveform of an output stage circuit according to the comparative example of FIG. 6.

Referring to FIGS. 6 and 7, the output stage 20 of the comparative example is different in that it does not include a bias adjusting unit compared to the embodiment of FIG. 4. That is, in the output stage 20 of the comparative example, the gate of the first transistor M1 is directly connected to the gate of the second transistor M2, such that the second bias voltage Vb2 is the same as the first bias voltage Vb1. It differs from the embodiment of FIG. 4 in that it maintains.

In this case, since the second bias voltage Vb2 maintains a substantially constant value regardless of the rise or fall of the output signal Vao, like the first bias voltage Vb1, the output node (through the second transistor M2) The current I3 supplied to n0) is also kept constant. Therefore, there is no effect of increasing the rising and falling speed of the output signal Vao. In the output stage 20 of the comparative example, since the current supply capability through the second transistor M2 is relatively insufficient compared to the current sink capability by the third to fifth transistors M3 to M5, the output signal Vao The disadvantage that the rate of ascension is slow may be highlighted.

8 is a view for explaining power supply noise removal characteristics of the output stage circuit according to the embodiment of FIG. 4.

The power supply Vdd may include noise of various frequency components. It is preferable that the noise component of the power supply Vdd does not appear in the output voltage Vout of the regulator. The power noise rejection characteristic is also referred to as a power supply rejection (PSR) characteristic.

In order to prevent power supply noise from appearing at the output voltage Vout of the regulator, it is preferable to include power supply noise in the amplifier output signal Vao. The source of the pass transistor 300 is connected to the power supply (Vdd), so when the gate of the pass transistor 300 does not include power supply noise, the power supply (Vdd) noise is transmitted from the source of the pass transistor 300 through the drain. It can affect the output voltage (Vout). That is, when power noise is commonly applied to the source and the gate of the pass transistor 300, power noise may not appear in the final output voltage Vout due to mutual cancellation of the gate and the source of the pass transistor 300. .

First, the transmission of low-frequency components of power supply noise through the third transistor M3 will be described. The gain stage 110 may operate using a power supply Vdd. The gain stage 110 generally includes internal resistance and parasitic capacitance, so that the high frequency component of the power supply Vdd noise is removed and the low frequency component can be transmitted to the output stage 120 through the output signal Vgso. have. In this case, the low frequency component of the power supply Vdd noise may be included in the amplifier output signal Vao through the third transistor M3.

Next, the transmission of the high frequency component of the power supply noise through the second transistor M2 will be described. Both the high frequency component and the low frequency component of the power supply noise may affect the first bias voltage Vb1 through the first transistor M1. However, since the resistor Rs and the capacitor Cs of the bias adjusting unit 122 function as a low-pass filter, the high frequency component of the power supply noise is reduced and the power supply noise low frequency component is mainly left in the second bias voltage Vb2. Since the gate of the second transistor M2 has a power supply noise low frequency component, and the source of the second transistor M2 includes both the high frequency component and the low frequency component of the power supply noise, the power supply noise low frequency component is the second transistor M2. The same is included in the gate and the source of each other to cancel each other, and only the high-frequency power supply noise component may be transmitted to the output signal Vao through the second transistor M2.

Accordingly, the amplifier output signal Vao includes both the high-frequency power supply noise component transmitted through the second transistor M2 and the low-frequency power supply component noise transmitted through the third transistor M3, and thus the final output voltage Vout of the regulator. The power supply noise component may be reduced.

As described above, according to the present embodiment, the high frequency component of the power supply noise may be reduced in the second bias voltage Vb2 by the bias adjusting unit 122 compared to the first bias voltage Vb1. In this case, the high frequency component of the power supply noise is increased in the amplifier output signal Vao, and the power supply noise component may be reduced in the regulator output voltage Vout. In order to effectively reduce the power supply noise component of the regulator output voltage Vout, the frequency range of the power supply noise high frequency component transmitted through the second transistor M2 is the frequency range of the power supply noise low frequency component transmitted through the third transistor M3. It would be desirable to design such that power supply noises in the entire frequency range may appear in the output signal Vao without complementing each other.

9 is a view for explaining power supply noise removal characteristics of the output stage circuit according to the comparative example of FIG. 6.

Referring to FIG. 9, in the case of the comparative example, since there is no bias adjusting unit, both the high frequency component and the low frequency component of the power supply noise generated in the first bias voltage Vb1 are transferred to the second bias voltage Vb2. In this case, since both the gate and the source of the second transistor M2 include a high frequency component and a low frequency component of power supply noise, the power supply noises cancel each other and are not transmitted to the output signal Vao through the second transistor M2. . Therefore, since the high frequency component of the power supply noise is not included in the output signal Vao, the high frequency component of the power supply noise applied to the source of the pass transistor 300 may appear at the output voltage Vout through the pass transistor 300.

As described above with reference to FIGS. 8 and 9, the regulator including the output stage 120 according to the present embodiment may improve power noise removal performance.

Next, referring to FIGS. 10 to 13, it will be described that the amplifier and the regulator according to the present embodiment have excellent stability characteristics.

First, the stability characteristics of the comparative example of FIG. 6 will be described with reference to FIGS. 10 and 11. 10 is a diagram illustrating an equivalent circuit for analyzing the stability of the output stage according to the comparative example of FIG. 6, and FIG. 11 is a diagram illustrating a loop gain and an input-output transfer function of the output stage according to the comparative example of FIG. It is a drawing.

The circuit of FIG. 10 is substantially the same as the circuit of FIG. 6, but the parasitic components affecting stability are also shown. For example, the capacitor Co2 is the input capacitance of the gate terminal of the second transistor M2, the resistor Ro1 is the output impedance of the fourth transistor, and the capacitor Co1 is the input of the gate terminal of the fifth transistor M5. Capacitance, capacitor Cp may be understood as the input capacitance of the gate terminal of pass transistor 300. These parasitic components may be understood as parasitic components inherent in transistors, not separately added elements, but additional resistors or capacitors may be added as necessary. In addition, a transistor is specified for each of these parasitic components and described as being a parasitic component of the transistor, which illustrates a typical element contributing to the parasitic component and may include parasitic components such as other adjacent elements or wiring.

Referring to FIG. 10, a feedback loop (loop 1) may be formed in the output stage 20. The first node voltage Vn1 affects the output signal Vao through the fifth transistor M5, and the output signal Vao again affects the first node voltage Vn1 through the third transistor M3. The feedback loop (loop 1) may be formed in a manner to give.

When the frequency characteristics of the feedback loop (loop 1) are obtained by considering the parasitic components illustrated in FIG. 10, Equations 1 to 3 are as follows.

[Equation 1]

DC gain = gm_m5·Ro1

[Equation 2]

fp2 = gm_m3 /(Cp·2·π)

[Equation 3]

fp3 = 1 / (Co1·Ro1·2·π)

Here, gm_m5 is the transconductance of the fifth transistor M5, and gm_m3 is the transconductance of the third transistor M3. For reference, in order to reduce confusion in comparison with the present embodiment through FIG. 13, the first pole frequency fp1 is omitted and the second pole frequency fp2 and the third pole frequency are omitted for two pole frequencies of the comparative example. It is called the pole frequency (fp3).

11 exemplarily shows the feedback loop gain 1101 obtained using Equations 1 to 3 and the transfer function 1102 of the output signal Vao for the input signal Vgso. Since the feedback loop gain 1101 includes two poles fp2 and fp3 in the unity gain frequency (UGF), the phase margin may be insufficient because the phase approaches 180 degrees near the UGF. . When the phase margin of the feedback loop (loop 1) is insufficient, a peak (peak) 1103 may occur in the UGF in the input-output transfer function 1102. Since the magnitude of the peak 1103 is affected by the phase margin, the smaller the phase margin, the larger the peak 1103 may be. The occurrence of the peak 113 in the transfer function 1102 is undesirable in terms of the system stability of the regulator.

Next, the stability of the embodiment illustrated in FIG. 4 will be described with reference to FIGS. 12 and 13. FIG. 12 is a diagram illustrating an equivalent circuit for analyzing the stability of the output stage according to the embodiment of FIG. 4, and FIG. 13 compares the loop gain and the input-output transfer function of the output stage circuit according to the embodiment of FIG. 4 It is a figure exemplifying in contrast to an example.

The circuit of FIG. 12 is substantially the same as the circuit of FIG. 4, but with the parasitic components affecting stability. 12, the feedback loop (loop 1) is formed in a similar manner to the comparative example, but in the present embodiment, additional poles and zeros occur due to the addition of resistors (Rs) and capacitors (Cs), and the location of the existing poles Can be changed.

The frequency characteristics of the feedback loop (loop 1) for the circuit of FIG. 12 are obtained from Equations 4 to 8 below.

[Equation 4]

DC gain = gm_m5·Ro1

[Equation 5]

fp1 = 1 / (Cs·(Ro1 + Rs)·2·π)

[Equation 6]

fz1 = 1 / (Cs·Rs·2·π)

[Equation 7]

fp2 = gm_m3 /(Cp·2·π)

[Equation 8]

fp3 = 1 / ((Co1 + Co2)·(Ro1∥Rs)·2·π)

Here, Ro1∥Rs means the resistance value when the resistor Ro1 and the resistor Rs are connected in parallel.

In the case of this embodiment, the first pole (fp1) and the first zero point (fz1) are generated in the UGF, and the frequency of the third pole (fp3) is changed, which is different from the case of the comparative example.

Referring to the loop gain 1301 illustrated in FIG. 13, the first pole fp1 and the first zero point fz1 are formed in a lower frequency region and cancel each other than the second pole fp2, and thus have a different effect on system stability. May not give. The third pole frequency (fp3), as can be seen through Equation 8, increases the capacitance but decreases as the resistance value changes to the parallel resistance value of Ro1 and Rs, so the third pole frequency (fp3) according to the design of Rs ) To a higher frequency than UGF. In this case, two poles (fp1, fp2) and one zero point (fz1) exist in the UGF, so that the phase margin in the UGF can be sufficiently increased. Even if it is difficult to design such that the third pole frequency (fp3) is higher than UGF, the phase margin in UGF increases as the third pole frequency (fp3) increases, which may help to increase stability. . When the third pole frequency (fp3) is moved to a relatively high frequency, the phase margin increases so that the peak 1303 occurring in the UGF of the input (Vgso)-output (Vao) transfer function 1302 is the peak 1103 of the comparative example ).

As described above, in the present embodiment, the third pole frequency fp3 of the feedback loop loop 1 of the output stage 120 may move to a relatively high frequency due to the resistor Rs and the capacitor Cs of the bias adjusting unit, , This can increase the stability of the amplifier and regulator.

14 is a diagram illustrating an output stage circuit of an amplifier according to an embodiment of the present invention.

The circuit illustrated in FIG. 14 illustrates a case where the resistor Rs of FIG. 4 is implemented as a transistor M6. To implement the resistor Rs, the source of the sixth transistor M6 is connected to the gate of the first transistor M1, and the drain and gate of the sixth transistor M6 are interconnected to connect the second transistor M2. It can be connected to the gate. As described above, when the resistor Rs is implemented as the transistor M6, the size can be reduced and manufacturing is easy.

15 is a block diagram schematically illustrating the output stage of an amplifier according to an embodiment of the present invention.

Referring to FIG. 15, the output stage 1520 may further include a power supply noise feed forward unit 1524. The power supply noise feed forward unit 1524 may operate to transfer the low frequency component of the power supply noise to the output node Vao. As described above, the gain stage of the amplifier transfers the low frequency component of the power supply noise to the output stage to some extent, but the power supply noise feed forward unit 1524 may be added to more efficiently transfer the low frequency component of the power supply noise.

16 is a diagram illustrating an output stage circuit according to an embodiment of the present invention. The circuit of FIG. 16 differs in that the power supply noise feedforward unit 1524 is further included compared to the circuit of FIG. 4.

The power supply noise feed forward unit 1524 may include eleventh to fifteenth transistors M11 to M15. The source of the eleventh transistor M11 may be connected to the power supply Vdd, and the gate of the eleventh transistor M11 may be connected to the bias voltage Vbp. The source of the twelfth transistor M12 is connected to ground (GND), the drain of the twelfth transistor M12 is connected to the drain of the eleventh transistor M11, and the gate of the twelfth transistor M12 is the fourteenth transistor It may be connected to the source of (M14). The source of the thirteenth transistor M13 is connected to the power supply Vdd, and the drain of the thirteenth transistor M13 is interconnected with the gate to be connected to the gate of the third transistor M3 as an output signal Vffo. The drain of the fourteenth transistor M14 is connected to the drain of the thirteenth transistor M13, the source of the fourteenth transistor M14 is connected to the gate of the twelfth transistor M12, and the gate of the fourteenth transistor M14 May be connected to the drain of the twelfth transistor M12. The source of the 15th transistor M15 is connected to ground (GND), the drain of the 15th transistor M15 is connected to the gate of the 12th transistor M12, and the gate of the 15th transistor M15 is the gain stage ( It may be connected to the output signal (Vgso) of 110).

The thirteenth transistor M13 may pass both the low-frequency component and the high-frequency component of the power supply noise to the output signal Vffo. The output signal Vffo is connected to the gate of the third transistor M3. Since the input terminal capacitance is present at the gate terminal of the third transistor M3, the output signal Vffo reduces high-frequency components in power supply noise and reduces low-frequency components. This can remain. The power supply noise low-frequency component included in the output signal Vffo may be transmitted to the amplifier output signal Vao through the third transistor M3. Therefore, as described above, the amplifier output signal Vao includes the power supply noise high-frequency component transmitted through the second transistor M2, and the power delivered through the power supply noise feedforward unit 1524 and the third transistor M3. All of the noise low-frequency components may be included, and as a result, the influence of power supply noise may be reduced in the regulator output voltage Vout.

As described above, in order to effectively reduce the power supply noise component of the regulator output voltage Vout, the frequency range of the high frequency component transmitted through the second transistor M2 is the frequency of the low frequency component transmitted through the third transistor M3. It is desirable to design such that power supply noise in the entire frequency range can appear in the output signal Vao without compensating for the range. When the power supply noise feed forward unit 1524 is used, not only can the low frequency component of the power supply noise be effectively transmitted, but also the advantage of being able to adjust the frequency range of the low frequency component transmitted through proper design of the thirteenth transistor M13 is provided. .

So far, the case where the amplifier including the bias adjusting unit according to the present embodiment is used for a regulator has been exemplified, but the bias adjusting unit according to the present embodiment may be used in other circuits or applications. Illustratively, the bias adjuster according to the present embodiment may be used in a general buffer circuit.

17 is a diagram illustrating a case where an embodiment of the present invention is used as a general buffer circuit. Referring to FIG. 17, the gate of the third transistor M3 is connected to the input signal Vi of the buffer circuit 1720 and the output node n0 is connected to the output signal Vo of the buffer circuit 1720. Can operate as a buffer circuit. As described above, the buffer circuit 1720 according to an exemplary embodiment of the present invention is a general buffer circuit that buffers and outputs an input signal and can be utilized in applications requiring excellent dynamic characteristics, PSR characteristics, and/or stability.

As described above, the buffer circuit, amplifier, or regulator including the bias adjusting unit according to the present embodiment has an advantage of excellent transient response characteristics, power supply noise removal performance, and/or stability.

The terms "comprise", "compose" or "have" as described above mean that the component can be inherent, unless otherwise stated, and do not exclude other components. It should be interpreted that it may further include other components. All terms, including technical or scientific terms, have the same meaning as generally understood by a person skilled in the art to which the present invention belongs, unless otherwise defined. Commonly used terms, such as predefined terms, should be interpreted as being consistent with the meaning in the context of the related art, and are not to be interpreted as ideal or excessively formal meanings unless explicitly defined in the present invention.

The above description is merely illustrative of the technical idea of the present invention, and those skilled in the art to which the present invention pertains may make various modifications and variations without departing from the essential characteristics of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, and the scope of the technical spirit of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical spirits within the scope equivalent thereto should be interpreted as being included in the scope of the present invention.

Claims (17)

A reference voltage generation circuit that generates and outputs a reference voltage;
An amplifier for receiving a first input signal corresponding to an output voltage and a second input signal corresponding to the reference voltage, and outputting an output signal amplifying the difference between the first input signal and the second input signal; And
Includes; a pass transistor for adjusting the output voltage in response to the output signal of the amplifier,
The amplifier includes an output stage for generating the output signal,
The output stage,
A bias generator that generates a first bias voltage;
A bias adjusting unit receiving the first bias voltage and generating and outputting a second bias voltage; And
It includes; an output unit that receives the second bias voltage and generates the output signal by using a bias current corresponding to the second bias voltage.
In the rising period of the amplifier output signal, the second bias voltage is lower than the first bias voltage regulator. delete delete The method according to claim 1,
The second bias voltage is a regulator characterized in that the high-frequency component of the power supply noise is reduced compared to the first bias voltage so that the high-frequency component of the power supply noise is increased in the amplifier output signal. The method according to claim 1,
The bias adjustment unit is characterized in that the lowering the peak in the unit gain frequency (UGF) of the output signal transfer function for the input signal of the output stage. The method according to claim 1,
The bias adjustment unit,
A resistor connected between the first bias voltage and the second bias voltage; And
And a capacitor connected between the feedback signal provided from the output unit and the second bias voltage. The method according to claim 6,
The amplifier further includes a gain stage that amplifies the difference between the first input signal and the second input signal and provides it to the output stage.
The feedback signal is a regulator, characterized in that when the output signal of the gain stage rises. The method according to claim 6,
The resistor is a regulator, characterized in that implemented in a transistor. The method according to claim 1,
The output stage further comprises a power supply noise feed forward unit for transmitting a low frequency component of power supply noise to the output signal. The method according to claim 1,
The output unit is a regulator characterized in that it comprises a transconductance boost stage for reducing the output impedance. A gain stage receiving a first input signal and a second input signal, and amplifying the difference between the first input signal and the second input signal to generate a first output signal; And
The output stage receives the first output signal, amplifies the second output signal, and outputs it through an output terminal.
The output stage,
A bias generator that generates a first bias voltage;
A bias adjusting unit receiving the first bias voltage and generating and outputting a second bias voltage; And
And an output unit receiving the second bias voltage and generating the second output signal using a bias current corresponding to the second bias voltage.
The bias generator includes a first transistor and a current source connected in series between the power supply and ground,
The output unit includes a second transistor, a third transistor, and a fourth transistor connected in series between the power supply and the ground,
The bias control unit comprises a resistor connected between the gate of the first transistor and the gate of the second transistor, and a capacitor connected between the gate of the second transistor and the drain of the third transistor. delete The method according to claim 11,
The resistor is characterized in that it is implemented as a transistor. The method according to claim 11,
The output unit further comprises a fifth transistor connected between the output terminal and the ground. The method according to claim 11,
The output stage further comprises a power supply noise feed-forward unit for transmitting a low frequency component of power supply noise to the output unit. In the buffer circuit for generating an output signal amplified the input signal and output through the output node,
A first transistor having a source connected to a power source and a gate and a drain connected to each other;
A current source connected between the drain and ground of the first transistor;
A second transistor having a source connected to the power supply and a drain connected to the output node;
A third transistor having a source connected to the output node, a drain connected to a first node, and receiving the input signal through a gate;
A fourth transistor having a drain connected to the first node and a source connected to the ground;
A fifth transistor having a gate connected to the first node, a drain connected to the output node, and a source connected to the ground;
A resistor connected between the gate of the first transistor and the gate of the second transistor; And
And a capacitor connected between the gate of the second transistor and the first node. The method according to claim 16,
The resistance is,
A buffer circuit, characterized in that a source is connected to the gate of the first transistor, and a gate and a drain are interconnected and connected to the gate of the second transistor.

Images