CN115840486B - Curvature compensation band gap reference circuit - Google Patents
Curvature compensation band gap reference circuit Download PDFInfo
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- CN115840486B CN115840486B CN202211261025.8A CN202211261025A CN115840486B CN 115840486 B CN115840486 B CN 115840486B CN 202211261025 A CN202211261025 A CN 202211261025A CN 115840486 B CN115840486 B CN 115840486B
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Abstract
The invention discloses a curvature compensation band gap reference circuit, which comprises a starting circuit, a compensation band gap reference circuit and a compensation band gap reference circuit, wherein the starting circuit is used for enabling the circuit to deviate from a zero state point and enter a working state; the first-order temperature compensation band-gap reference unit is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate temperature-related primary terms in the band-gap reference voltage; and the second-order temperature compensation band-gap reference unit is used for generating compensation current to eliminate two terms of the band-gap reference voltage. The curvature compensation band gap reference circuit provided by the invention can eliminate the primary term and the secondary term related to temperature in the output reference voltage, reduce the temperature drift coefficient, enhance the stability of the circuit through a negative feedback structure, and obtain higher power supply rejection ratio and good temperature characteristics in a wider temperature range.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a curvature compensation band gap reference circuit.
Background
The bandgap reference circuit is a basic module in the field of analog integrated circuit design, and is used for providing a reference voltage which has small variation with external factors for the whole circuit, and the voltage has good temperature stability and high power supply rejection ratio, i.e. has small variation with temperature and power supply voltage.
The traditional band gap reference circuit utilizes bipolar junction transistor BJT and operational amplifier clamping technology to obtain a current IPTAT which is positively correlated with temperature and a current ICTAT which is negatively correlated with temperature, and then the current IPTAT and the current ICTAT are added and multiplied by a resistor to obtain reference voltage. By this scheme, the primary term of the temperature coefficient is eliminated.
However, the above method only performs first-order compensation on the temperature characteristic curve, and the obtained reference voltage still contains a higher term related to temperature, so that the temperature characteristic curve presents a parabolic shape with a dominant quadratic term, and the temperature coefficient obtained by calculating the reference voltage generally still has tens or tens of coefficients, which generally is difficult to meet the high stability requirement proposed in the design of high-precision analog integrated circuits.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a curvature compensation bandgap reference circuit. The technical problems to be solved by the invention are realized by the following technical scheme:
a curvature compensated bandgap reference circuit comprising:
the starting circuit is used for enabling the circuit to be separated from a zero state point and enter a working state;
the first-order temperature compensation band-gap reference unit is used for generating positive temperature coefficient current and negative temperature coefficient current and summing the positive temperature coefficient current and the negative temperature coefficient current so as to eliminate temperature-related primary terms in the band-gap reference voltage;
and the second-order temperature compensation band-gap reference unit is used for generating compensation current to eliminate two terms of the band-gap reference voltage.
In one embodiment of the present invention, the start-up circuit includes a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1 and an NMOS tube NM2; wherein,
The source electrode of the PMOS tube PM1 is connected with the power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected and commonly connected with the source electrode of the PMOS tube PM 2;
The grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid electrode of the NMOS tube NM1 is connected with a band gap reference output voltage vref;
The source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground terminal;
The drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit to be connected with the input end of the first-order temperature compensation band gap reference unit.
In one embodiment of the present invention, the first-order temperature compensated bandgap reference unit includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2; wherein,
The grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then used as the input end of the first-order temperature compensation band gap reference unit to be connected with the output end of the starting circuit;
the source electrode of the PMOS tube PM3, the source electrode of the PMOS tube PM4 and the source electrode of the PMOS tube PM5 are all connected with a power supply voltage VDD end;
The drain electrode of the PMOS tube PM3 is connected with the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter electrode of the PNP transistor Q1;
the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
The other end of the resistor R0 is connected with the emitter of the PNP transistor Q2;
the output end VOUT of the operational amplifier OPA1 is connected to the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM 5;
The other end of the resistor R1, the base and collector of the PNP type transistor Q2 and the other end of the resistor R2 are all connected to a common ground terminal;
The drain electrode of the PMOS tube PM5 is connected with a common ground end through the resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit to be connected with the input end of the second-order temperature compensation band gap reference unit;
the drain electrode of the PMOS tube PM5 is also used as the output end of the band-gap reference circuit to output band-gap reference voltage vref.
In one embodiment of the invention, the operational amplifier OPA1 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,
The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 1;
The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal.
In one embodiment of the present invention, the PMOS pipe PM3, the PMOS pipe PM4, and the PMOS pipe PM5 have the same size.
In one embodiment of the present invention, the second-order temperature compensated bandgap reference unit includes a PMOS tube PM6, an operational amplifier OPA2, an NMOS tube NM3, a capacitor C1, a resistor R4, and a resistor R5; wherein,
The source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
The negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit to be connected with the output end of the first-order temperature compensation band gap reference unit;
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground terminal;
the resistor R4 and the resistor R5 are connected in series between the drain electrode of the PMOS tube PM6 and the common ground;
the grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5.
In one embodiment of the invention, the operational amplifier OPA2 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,
The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
The grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 2;
The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 2;
The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal.
The invention has the beneficial effects that:
1. According to the curvature compensation band gap reference circuit provided by the invention, the first-order temperature compensation band gap reference unit is utilized to generate band gap reference voltage without a primary term related to temperature, and the second-order temperature compensation band gap reference unit is utilized to generate compensation current to eliminate a secondary term related to temperature in the reference voltage, so that a lower temperature drift coefficient is obtained;
2. The second-order temperature compensation band gap reference unit in the curvature compensation band gap reference circuit simultaneously forms a negative feedback structure, and when the band gap reference voltage vref is greatly changed due to external factors, the band gap reference voltage vref can be kept stable through the negative feedback structure, so that a lower temperature drift coefficient and a higher power supply rejection ratio are further obtained.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a curvature compensated bandgap reference circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an operational amplifier according to an embodiment of the present invention;
FIG. 3 is a graph of test results of a band gap reference voltage output by a curvature compensation band gap reference circuit according to an embodiment of the present invention with temperature change;
FIG. 4 is a graph of the power supply rejection ratio versus frequency for a curvature compensated bandgap reference circuit according to an embodiment of the invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a curvature (second order) compensated bandgap reference circuit according to an embodiment of the invention, which includes:
starting the circuit 1, which is used for enabling the circuit to be separated from a zero state point and enter a working state;
A first-order temperature compensation bandgap reference unit 2 for generating a positive temperature coefficient current and a negative temperature coefficient current and summing them to eliminate a temperature-dependent primary term in the bandgap reference voltage;
A second-order temperature compensated bandgap reference unit 3 for generating a compensation current to cancel both terms of the bandgap reference voltage.
Specifically, in this embodiment, the start-up circuit 1 includes a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1, and an NMOS tube NM2; wherein,
The source electrode of the PMOS tube PM1 is connected with the power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected and commonly connected with the source electrode of the PMOS tube PM 2;
The grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid electrode of the NMOS tube NM1 is connected with a band gap reference output voltage vref;
The source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground terminal;
The drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit 1 to be connected with the input end of the first-order temperature compensation band gap reference unit 2.
Further, please continue to refer to fig. 1, wherein the first-order temperature compensated bandgap reference unit 2 includes a PMOS transistor PM3, a PMOS transistor PM4, a PMOS transistor PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP transistor Q1, and a PNP transistor Q2; wherein,
The grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then used as the input end of the first-order temperature compensation band gap reference unit 2 to be connected with the output end of the starting circuit 1;
The source electrode of the PMOS tube PM3, the source electrode of the PMOS tube PM4 and the source electrode of the PMOS tube PM5 are all connected with the power supply voltage VDD end;
The drain electrode of the PMOS tube PM3 is connected with the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter electrode of the PNP transistor Q1;
The drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
The other end of the resistor R0 is connected with the emitter of the PNP transistor Q2;
The output end VOUT of the operational amplifier OPA1 is connected to the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM 5;
The other end of the resistor R1, the base and collector of the PNP transistor Q2 and the other end of the resistor R2 are all connected to a common ground terminal;
The drain electrode of the PMOS tube PM5 is connected with a common ground end through a resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit 2 to be connected with the input end of the second-order temperature compensation band gap reference unit 3;
The drain of the PMOS tube PM5 also serves as the output of the bandgap reference circuit for outputting a bandgap reference voltage vref.
In this embodiment, the operational amplifier OPA1 adopts a two-stage amplifying structure, so that a higher gain can be obtained, the clamping effect is better, and the power supply rejection ratio is higher.
For example, the present embodiment can implement the operational amplifier OPA1 in the first-order temperature-compensated bandgap reference cell 2 using the operational amplifier structure shown in fig. 2. Specifically, it includes: PMOS tube PM2-1, PMOS tube PM2-2, PMOS tube PM2-3, PMOS tube PM2-4, PMOS tube PM2-5, PMOS tube PM2-6, NMOS tube NM2-1, NMOS tube NM2-2, NMOS tube NM2-3, NMOS tube NM2-4, NMOS tube NM2-5, capacitor C2-1, resistor R2-1 and resistor R2-2; wherein,
The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
The source electrode of the NMOS tube NM2-2 is connected with a common ground end through a resistor R2-1;
the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;
The drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
The grid electrode of the PMOS tube PM2-4 is used as the negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through a resistor R2-2;
The grid electrode of the PMOS tube PM2-5 is used as the positive input end VIP of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
the source of NMOS tube NM2-1, the source of NMOS tube NM2-3, the source of NMOS tube NM2-4 and the source of NMOS tube NM2-5 are all connected to a common ground terminal.
Further, please continue to refer to fig. 1, wherein the second-order temperature compensated bandgap reference unit 3 includes a PMOS tube PM6, an operational amplifier OPA2, an NMOS tube NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein,
The source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
The negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit (3) to be connected with the output end of the first-order temperature compensation band gap reference unit 2;
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground terminal;
The resistor R4 and the resistor R5 are connected in series between the drain electrode of the PMOS tube PM6 and the common ground end;
The gate of the NMOS transistor NM3 is also connected to the common terminal of the resistor R4 and the resistor R5.
In this embodiment, the operational amplifier OPA2 may have the same circuit structure as the operational amplifier OPA1, that is, the circuit structure shown in fig. 2, and in fig. 2, the gate of the PMOS tube PM2-4 is used as the negative input terminal VIN of the operational amplifier OPA2, the gate of the PMOS tube PM2-5 is used as the positive input terminal VIP of the operational amplifier OPA2, and the drain of the PMOS tube PM2-6 is connected with the drain of the NMOS tube NM2-5 and is used as the output terminal VOUT of the operational amplifier OPA 2.
The curvature compensation band gap reference circuit provided in this embodiment has the following working principle:
In the starting circuit, when the power is on, the gate voltage of the NMOS tube NM2 becomes high, the gate potentials of the PMOS tube PM3 and the PMOS tube PM4 are pulled down, the first-order temperature compensation band gap reference unit starts to work, and then the output reference voltage vref controls the NMOS tube NM1 to be opened, so that the gate potential of the NMOS tube NM2 is pulled down to enable the NMOS tube NM2 to be turned off, and the starting process is completed.
In the first-order temperature compensation bandgap reference unit, by the clamping action of the operational amplifier OPA1, the potentials of the positive and negative input ends are equal, and the current flowing through the resistor R2 is a negative temperature coefficient current ICTAT:
wherein V be1 is the base and emitter voltage of PNP transistor Q1.
The current flowing through resistor R0 is a positive temperature coefficient current:
Wherein, V be2 is the base and emitter voltages of the PNP transistor Q2, V T is the triode thermal voltage, I 0、NI0 is the collector currents of the PNP transistor Q1 and the PNP transistor Q2, I S1、IS2 is the saturation currents of the PNP transistor Q1 and the PNP transistor Q2, and N is the ratio of the emitter areas of the PNP transistor Q2 and the PNP transistor Q1.
In this embodiment, the sizes of the PMOS transistor PM3, the PMOS transistor PM4 and the PMOS transistor PM5 are equal, so that the currents of the branches where the three PMOS transistors are located are equal, and are the sum of the positive temperature coefficient current and the negative temperature coefficient current, i.e. the current without the primary term related to temperature.
In the second-order temperature compensation bandgap reference unit, through the clamping action of the operational amplifier OPA2, the positive and negative input end potentials of the operational amplifier OPA2 are equal, that is, the positive input end potential of the operational amplifier OPA2 is equal to the bandgap reference output voltage vref, and the NMOS transistor NM3 works in a saturation region by adjusting the magnitudes of the resistor R4 and the resistor R5, so that the current I 1 flowing through the NMOS transistor NM3 is:
mu N is the carrier mobility of the NMOS tube, C ox is the gate oxide capacitance of unit area, W is the width of the NMOS tube NM3, L is the length of the NMOS tube NM3, and V TH is the threshold voltage of the NMOS tube NM 3.
Wherein the vref voltage formula is:
Vref can be further expressed by this formula as:
Wherein k is I 0 is the sum of the positive temperature coefficient current I PTAT and the negative temperature coefficient current I CTAT, and contains a temperature-dependent quadratic term.
Therefore, the primary term relation of the temperature contained in V TH can be utilized, and the secondary term relation of vref and the temperature in the above formula can be eliminated, so that a lower temperature drift coefficient is obtained.
In addition, the second-order temperature compensation band gap reference unit simultaneously forms a negative feedback loop, namely the operational amplifier OPA2, the PMOS tube PM6, the resistor R4, the capacitor C1 and the NMOS tube NM3 form a negative feedback structure, so that the stability of the circuit can be improved, when the output band gap reference voltage vref is greatly changed due to temperature improvement or other external factors, the current of the NMOS tube NM3 can be increased, so that the current flowing through the resistor R3 is pumped, the output band gap reference voltage vref is stably reduced, the temperature drift coefficient is further reduced, and the power supply rejection ratio is greatly improved.
To further verify the beneficial effects of the present invention, the present embodiment also tested the temperature-dependent bandgap reference voltage and the power supply rejection ratio of the curvature compensation bandgap reference circuit, and the results thereof are shown in fig. 3 and 4. Wherein, FIG. 3 is a graph of test results of band gap reference voltage output by the curvature compensation band gap reference circuit according to the embodiment of the invention along with temperature change, which mainly shows a temperature characteristic curve of the output reference voltage within a wider temperature change range (-40 ℃ to 160 ℃), and the result shows that the temperature drift coefficient of the curvature compensation band gap reference circuit according to the embodiment of the invention can be as low as 00440000 ℃. In addition, as can be seen from fig. 3, the reference voltage is kept stable within-40 ℃ to 160 ℃, and the voltage is only changed by 10607uV, which indicates that the band gap reference voltage output by the invention can be kept stable within a wider temperature range.
FIG. 4 is a graph of the power supply rejection ratio versus frequency for a curvature compensated bandgap reference circuit according to an embodiment of the invention. As can be seen from fig. 4, the power supply rejection ratio of the present invention is-77 dB at low frequencies, illustrating that the present invention has a higher power supply rejection ratio.
In summary, the curvature compensation band gap reference circuit provided by the invention can eliminate the primary term and the secondary term related to temperature in the output reference voltage, reduce the temperature drift coefficient, enhance the stability of the circuit through the negative feedback structure, and obtain higher power supply rejection ratio and good temperature characteristics in a wider temperature range.
In another embodiment of the present invention, the operational amplifier OPA2 in the second-order temperature compensated bandgap reference unit 3 may be replaced by a cascode negative feedback structure, so as to achieve the clamping effect, and thus obtain the same voltage as the output reference voltage variation to control the gate of the NMOS transistor NM 3. The specific implementation is not described in detail here.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (2)
1. A curvature compensated bandgap reference circuit, comprising:
The starting circuit (1) is used for enabling the circuit to be separated from a zero state point and enter a working state;
a first-order temperature compensated bandgap reference unit (2) for generating a positive temperature coefficient current and a negative temperature coefficient current and summing to eliminate a temperature dependent primary term in the bandgap reference voltage;
a second-order temperature-compensated bandgap reference unit (3) for generating a compensation current to cancel two terms of the bandgap reference voltage;
The starting circuit (1) comprises a PMOS tube PM1, a PMOS tube PM2, an NMOS tube NM1 and an NMOS tube NM2; wherein,
The source electrode of the PMOS tube PM1 is connected with the power supply voltage VDD end, and the grid electrode and the drain electrode of the PMOS tube PM1 are connected and commonly connected with the source electrode of the PMOS tube PM 2;
The grid electrode and the drain electrode of the PMOS tube PM2, the drain electrode of the NMOS tube NM1 and the grid electrode of the NMOS tube NM2 are connected;
the grid electrode of the NMOS tube NM1 is connected with a band gap reference output voltage vref;
The source electrode of the NMOS tube NM1 and the source electrode of the NMOS tube NM2 are both connected with a common ground terminal;
The drain electrode of the NMOS tube NM2 is used as the output end of the starting circuit (1) to be connected with the input end of the first-order temperature compensation band gap reference unit (2);
the first-order temperature compensation band gap reference unit (2) comprises a PMOS tube PM3, a PMOS tube PM4, a PMOS tube PM5, an operational amplifier OPA1, a resistor R0, a resistor R1, a resistor R2, a resistor R3, a PNP type transistor Q1 and a PNP type transistor Q2; wherein,
The grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM5 are connected and then used as the input end of the first-order temperature compensation band gap reference unit (2) to be connected with the output end of the starting circuit (1);
the source electrode of the PMOS tube PM3, the source electrode of the PMOS tube PM4 and the source electrode of the PMOS tube PM5 are all connected with a power supply voltage VDD end;
The drain electrode of the PMOS tube PM3 is connected with the positive input end VIP of the operational amplifier OPA1, one end of the resistor R1 and the emitter electrode of the PNP transistor Q1;
the drain electrode of the PMOS tube PM4 is connected with the negative input end VIN of the operational amplifier OPA1, one end of the resistor R0 and one end of the resistor R2;
The other end of the resistor R0 is connected with the emitter of the PNP transistor Q2;
the output end VOUT of the operational amplifier OPA1 is connected to the grid electrode of the PMOS tube PM3, the grid electrode of the PMOS tube PM4 and the grid electrode of the PMOS tube PM 5;
The other end of the resistor R1, the base and collector of the PNP type transistor Q2 and the other end of the resistor R2 are all connected to a common ground terminal;
The drain electrode of the PMOS tube PM5 is connected with a common ground end through the resistor R3, and the drain electrode of the PMOS tube PM5 is used as the output end of the first-order temperature compensation band gap reference unit (2) to be connected with the input end of the second-order temperature compensation band gap reference unit (3);
The drain electrode of the PMOS tube PM5 is also used as the output end of the band-gap reference circuit to output band-gap reference voltage vref;
The operational amplifier OPA1 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,
The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 1;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
the grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 1;
The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 1;
The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal;
The second-order temperature compensation band gap reference unit (3) comprises a PMOS tube PM6, an operational amplifier OPA2, an NMOS tube NM3, a capacitor C1, a resistor R4 and a resistor R5; wherein,
The source electrode of the PMOS tube PM6 is connected with a power supply voltage VDD end, the grid electrode of the PMOS tube PM6 is connected with the output end VOUT of the operational amplifier OPA2, and the drain electrode of the PMOS tube PM6 is connected with the positive input end VIP of the operational amplifier OPA 2;
The negative input end VIN of the operational amplifier OPA2 is connected with the drain electrode of the NMOS tube NM3 and is used as the input end of the second-order temperature compensation band gap reference unit (3) to be connected with the output end of the first-order temperature compensation band gap reference unit (2);
the capacitor C1 is connected between the drain electrode and the grid electrode of the NMOS tube NM 3;
the drain electrode of the NMOS tube NM3 is connected with a common ground terminal;
the resistor R4 and the resistor R5 are connected in series between the drain electrode of the PMOS tube PM6 and the common ground;
The grid electrode of the NMOS tube NM3 is also connected with the common end of the resistor R4 and the resistor R5;
The operational amplifier OPA2 comprises a PMOS tube PM2-1, a PMOS tube PM2-2, a PMOS tube PM2-3, a PMOS tube PM2-4, a PMOS tube PM2-5, a PMOS tube PM2-6, an NMOS tube NM2-1, an NMOS tube NM2-2, an NMOS tube NM2-3, an NMOS tube NM2-4, an NMOS tube NM2-5, a capacitor C2-1, a resistor R2-1 and a resistor R2-2; wherein,
The source electrode of the PMOS tube PM2-1, the source electrode of the PMOS tube PM2-2, the source electrode of the PMOS tube PM2-3 and the source electrode of the PMOS tube PM2-6 are all connected with a power supply voltage VDD end;
the drain electrode of the PMOS tube PM2-1, the drain electrode and the grid electrode of the NMOS tube NM2-1 and the grid electrode of the NMOS tube NM2-2 are connected;
the grid electrode of the PMOS tube PM2-1, the grid electrode and the drain electrode of the PMOS tube PM2-2, the drain electrode of the NMOS tube NM2-2, the grid electrode of the PMOS tube PM2-3 and the grid electrode of the PMOS tube PM2-6 are connected;
The source electrode of the NMOS tube NM2-2 is connected with a common ground end through the resistor R2-1;
the drain electrode of the PMOS tube PM2-3 is connected with the source electrode of the PMOS tube PM2-4 and the source electrode of the PMOS tube PM 2-5;
the drain electrode of the PMOS tube PM2-4, the drain electrode and the grid electrode of the NMOS tube NM2-3 and the grid electrode of the NMOS tube NM2-4 are connected;
the grid electrode of the PMOS tube PM2-4 is used as a negative input end VIN of the operational amplifier OPA 2;
the drain electrode of the PMOS tube PM2-5 is connected with the drain electrode of the NMOS tube NM2-4, one end of the capacitor C2-1 and the grid electrode of the NMOS tube NM 2-5;
the other end of the capacitor C2-1 is connected with the drain electrode of the NMOS tube NM2-5 through the resistor R2-2;
The grid electrode of the PMOS tube PM2-5 is used as a positive input end VIP of the operational amplifier OPA 2;
The drain electrode of the PMOS tube PM2-6 is connected with the drain electrode of the NMOS tube NM2-5 and is used as the output end VOUT of the operational amplifier OPA 2;
The source electrode of the NMOS tube NM2-1, the source electrode of the NMOS tube NM2-3, the source electrode of the NMOS tube NM2-4 and the source electrode of the NMOS tube NM2-5 are all connected to a common ground terminal.
2. The curvature compensated bandgap reference circuit of claim 1, wherein said PMOS tube PM3, said PMOS tube PM4 and said PMOS tube PM5 are equal in size.
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| CN102541149A (en) * | 2010-12-31 | 2012-07-04 | 无锡华润上华半导体有限公司 | Reference power circuit |
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| US8461912B1 (en) * | 2011-12-20 | 2013-06-11 | Atmel Corporation | Switched-capacitor, curvature-compensated bandgap voltage reference |
| CN104298293B (en) * | 2013-07-17 | 2016-01-20 | 北京兆易创新科技股份有限公司 | A kind of bandgap voltage reference with curvature compensation |
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| US11088699B1 (en) * | 2020-06-05 | 2021-08-10 | Texas Instruments Incorporated | Piecewise compensation method for ultra-low temperature drift |
| CN114840049A (en) * | 2022-05-17 | 2022-08-02 | 西安水木芯邦半导体设计有限公司 | Band-gap reference circuit with second-order curvature compensation |
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