CN111796625B - Ultra-low power consumption CMOS voltage reference circuit - Google Patents

Ultra-low power consumption CMOS voltage reference circuit Download PDF

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CN111796625B
CN111796625B CN202010733523.2A CN202010733523A CN111796625B CN 111796625 B CN111796625 B CN 111796625B CN 202010733523 A CN202010733523 A CN 202010733523A CN 111796625 B CN111796625 B CN 111796625B
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temperature coefficient
operational amplifier
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CN111796625A (en
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邓禹辰
吴建辉
吴志强
谢祖帅
周全才
瞿剑
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Southeast University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

Abstract

The invention discloses a CMOS voltage reference circuit with ultra-low power consumption, which generates delta V by connecting MOS tubes in series with a traditional single branchTHThe transformation form is generated by two branches, namely current is copied through a current mirror, so that the threshold voltages of two threshold tubes are subtracted to generate a negative temperature coefficient voltage, and then the negative temperature coefficient voltage is added with a positive temperature coefficient voltage to realize first-order and second-order temperature coefficient compensation of output voltage, and the reference voltage with better temperature characteristics is obtained. The trimming process is realized by adding the output MOS tubes connected in parallel, and the circuit can still output stably under different PVT conditions. Meanwhile, the width-to-length ratio W/L of key tubes in the circuit is designed to be smaller than 1, so that the quiescent current is greatly reduced, all MOS tubes except the current mirror MOS tube work in a subthreshold region, the power consumption is further reduced, and the chip area can be effectively saved by adopting single-stage differential operational amplifier.

Description

Ultra-low power consumption CMOS voltage reference circuit
Technical Field
The invention belongs to the field of voltage reference, and particularly relates to a Complementary Metal Oxide Semiconductor (CMOS) voltage reference circuit capable of realizing ultra-low power consumption.
Background
Voltage reference modules are an important basic module in both analog and digital-analog hybrid circuits, and the voltage reference needs to provide a reference voltage that does not change with process, supply voltage, and temperature. With the development of high integration and low power consumption, the design of voltage reference is more strict. The design of the voltage reference has more difficulties under the conditions of low voltage, limited area and low energy consumption. Therefore, the invention provides a CMOS voltage reference circuit capable of realizing low power consumption, and the circuit can be applied to low-voltage circuits such as energy collection circuits.
The main voltage references can now be divided into bandgap reference voltages and CMOS reference voltages. Due to the need to use BJT (Bipolar junction transistor) devices in the bandgap reference voltageThe bandgap reference circuit is difficult to operate at a low voltage due to the characteristics of the BJT device itself. Voltage reference circuits operating at low voltages therefore typically employ CMOS architectures. Most conventional Δ VTHThe (threshold difference) type CMOS voltage reference is formed by connecting two MOS tubes with different thresholds in the same branch in series, namely a 2T type CMOS voltage reference, and the main idea is that the currents flowing through a high threshold NMOS (N-type metal oxide semiconductor) and a standard threshold NMOS are equal, so that an expression of a reference voltage is obtained, the expression of the reference voltage comprises a positive temperature coefficient term formed by the difference value of the threshold voltages of the two tubes with different types and a negative temperature term formed by adjusting the size of the tubes, and the reference voltage with a zero temperature coefficient is obtained by adjusting the size of the tubes. Since the structure can only compensate the temperature coefficient brought by the threshold value for the adjustment size, the high-order term in the temperature coefficient cannot be processed, and the temperature characteristic of the output voltage is poor. The invention provides a CMOS voltage reference which is approximate to temperature independence and low in power consumption, and the main idea of the design is that the threshold voltages of different threshold tubes of two branches can be subtracted by copying current through a PMOS current mirror, and a positive temperature coefficient voltage V is introducedPTATThe offset temperature coefficient is further compensated, so that better temperature characteristics are realized. In addition, the width-to-length ratio of a key tube in the designed circuit is less than 1, so that the quiescent current can be greatly reduced, and the power consumption of the circuit is reduced. The compensation capacitor Cc and the output capacitor Co can improve the PSRR (power supply ripple rejection ratio) characteristics of the output voltage.
Disclosure of Invention
The technical problem is as follows: the invention aims to provide a CMOS voltage reference circuit capable of realizing ultra-low power consumption, which is used as a basic unit of an analog circuit and can realize a voltage reference with lower static power consumption.
The technical scheme is as follows: in order to solve the technical problem, the ultra-low power consumption CMOS voltage reference circuit adopts the following technical scheme:
the reference circuit comprises a positive temperature coefficient voltage VPTATA generating part, a differential operational amplifier and a PMOS current mirror; the first transistor-the fourth transistor are positive temperature coefficient voltage VPTATThe generating part comprises an operational amplifier formed by a ninth transistor and a fourteenth transistor, wherein the fifth transistor and the sixth transistor are PMOS current mirrors, the seventh transistor is a normal threshold NMOS transistor, and the eighth transistor is a high threshold NMOS transistor;
positive temperature coefficient voltage VPTATOutputting the current at the drain terminal of the eighth transistor through differential operational amplifier voltage clamping and PMOS current mirror current copying; threshold difference Δ V between the seventh transistor and the eighth transistor generated during current replicationTHAnd a positive temperature coefficient voltage V is introducedPTATPerforming more precise temperature coefficient compensation, and simultaneously using an output capacitor Co and a compensation capacitor Cc to improve the power supply ripple rejection ratio PSRR; input signal VDDIntegral output signal V of circuitref。
The fifth transistor, the sixth transistor, the eleventh transistor, the twelfth transistor, the thirteenth transistor and the fourteenth transistor are PMOS tubes, and the rest are NMOS tubes.
The second transistor and the fourth transistor are identical in size and are connected in parallel, the drain electrodes of the second transistor and the fourth transistor are connected with a power supply voltage, the grid electrodes and the source electrodes of the second transistor and the fourth transistor are connected with the drain electrodes of the first transistor in series, and then the source electrodes of the first transistor are grounded.
The drain electrode of the first transistor is connected with the negative polarity input end VN, and the drain electrode of the seventh transistor is connected with the positive polarity input end VP.
In the differential operational amplifier, the ninth transistor, the eleventh transistor, the thirteenth transistor branch and the tenth transistor, the twelfth transistor and the fourteenth transistor branch are completely symmetrical, but the gates of the eleventh transistor and the thirteenth transistor are connected with the drains of the eleventh transistor and the thirteenth transistor to realize biasing, so that the stacked differential operational amplifier is formed.
The output signal of the differential operational amplifier is C: the output signal of the whole circuit is Vref(ii) a The compensating capacitor Cc is connected between a power supply and the grid electrode of the fifth transistor, the output C of the differential operational amplifier is also connected with the grid electrode of the fifth transistor, then the source electrode and the drain electrode of the fifth transistor are respectively connected with the power supply and the drain electrode of the seventh transistor, the source electrode of the seventh transistor is grounded, and the grid electrode of the seventh transistor is connected with the drain electrode of the seventh transistor.
The grid electrode of the sixth transistor is connected with the grid electrode of the fifth transistor, and the source electrode and the drain electrode of the sixth transistor are respectively connected with the power supply and the drain electrode of the eighth transistor; the grid of the eighth transistor is connected with the drain of the eighth transistor, the source of the eighth transistor is grounded, and the output capacitor Co is connected between the drain of the eighth transistor and the ground.
Has the advantages that: compared with the prior art, the invention has the following advantages:
the low-power-consumption CMOS voltage reference circuit provided by the invention is in a 2T type delta V stateTHThe CMOS voltage reference idea is structurally changed, the series connection is changed into the parallel connection, the voltage reference with lower temperature coefficient can be realized, the power consumption is greatly reduced, and meanwhile, the structure is simple, fewer MOS tubes are used, the area of a chip can be reduced, and the circuit cost is saved. Although the differential operational amplifier is used, compared with a voltage reference circuit with the same structure, the single-stage differential operational amplifier reduces the layout area, reduces the power consumption of the circuit and can work under low input voltage.
Drawings
FIG. 1 is a circuit topology of the present invention;
FIG. 2 is a linear sensitivity characteristic curve of a CMOS voltage reference implemented using the present invention at different process angles;
fig. 3 is a PSRR characteristic curve of a CMOS voltage reference implemented by the present invention at different process corners.
Fig. 4 shows temperature profiles of CMOS voltage references implemented using the present invention at different process corners.
The figure shows that: a first transistor M1-a fourteenth transistor M14, a compensation capacitor Cc and an output capacitor Co, an input signal VDDOutput signal VrefThe differential operational amplifier comprises a positive polarity input end VP of the differential operational amplifier, a negative polarity input end VN of the differential operational amplifier and an output end C of the differential operational amplifier.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in FIG. 1, the ultra-low power consumption CMOS voltage reference circuit of the present invention comprises an input signal VDDAnd an output signal Vref. Positive temperature coefficient voltage VPTATVoltage clamp and current mirror through differential operational amplifierStream replication, Δ V generated at the output for this processTHTemperature coefficient compensation is performed, and the compensation capacitor Cc and the output capacitor Co are used to improve the PSRR characteristic of the output voltage.
The fifth transistor M5, the sixth transistor M6, the eleventh transistor M11, the twelfth transistor M12, the thirteenth transistor M13 and the fourteenth transistor M14 are PMOS transistors, and the rest are NMOS transistors. Positive temperature coefficient voltage VPTATThe differential operational amplifier is generated by a first transistor M1-a fourteenth transistor M4, a ninth transistor M9-a fourteenth transistor M14, a fifth transistor M5 and a sixth transistor M6 are PMOS current mirrors, and an eighth transistor M8 is a high-threshold NMOS transistor. The second transistor M2-the fourth transistor M4 are the same in size and are connected in parallel, the drain electrodes are connected with a power supply voltage, the grid electrodes and the source electrodes of the second transistor M2-the fourth transistor M4 are connected with the drain electrodes of the first transistor M1 in series, and then the source electrodes of the first transistor M1 are grounded; the positive polarity input end VP of the differential operational amplifier, the negative polarity input end VN of the differential operational amplifier, and the drains of the first transistor M1 and the seventh transistor M7 are respectively connected with the VN and VP ends of the differential operational amplifier, the branches of the ninth transistor M9, the eleventh transistor M11, the thirteenth transistor M13 and the branches of the tenth transistor M10, the twelfth transistor M12 and the fourteenth transistor M14 are completely symmetrical, but the gates of the eleventh transistor M11 and the thirteenth transistor M13 are connected with the drains of the eleventh transistor M11 and the thirteenth transistor M13 to realize biasing, so as to form a stacked differential operational amplifier, and the output end C of the differential operational amplifier is connected with the output end C of the stacked differential operational amplifier; the compensating capacitor Cc is connected between a power supply and the grid electrode of the fifth transistor M5, the output end C of the differential operational amplifier is also connected with the grid electrode of the fifth transistor M5, then the source electrode and the drain electrode of the fifth transistor M5 are respectively connected with the power supply and the drain electrode of the seventh transistor M7, the source electrode of the seventh transistor M7 is grounded, and the grid electrode of the seventh transistor M7 is connected with the drain electrode of the seventh transistor M7; the sixth transistor M6 is connected with the gate of the fifth transistor M5, and the source and the drain of the sixth transistor M6 are respectively connected with the power supply and the drain of the eighth transistor M8; the gate of the eighth transistor M8 is connected to its drain and the source is grounded, and the output capacitor Co is connected between the drain of the eighth transistor M8 and ground.
The low-power-consumption CMOS voltage reference circuit provided by the invention can effectively reduce the power and temperature coefficient of the voltage reference circuit, thereby meeting the requirements of the existing integrated circuit on low power consumption and stable output, reducing the requirement of large input voltage, simultaneously reducing the layout area and saving the cost. The proposed circuit structure can be applied to low supply voltage applications such as energy harvesting. The operation principle of the simulation method is described in detail below with reference to specific circuits and simulation results.
As shown in FIG. 1, the present invention mainly comprises a differential operational amplifier and a positive temperature coefficient voltage VPTATThe generating circuit and the PMOS current mirror circuit, and all the tubes work in the subthreshold region. Since the currents flowing through the first transistor M1 and the second transistor M2-the fourth transistor M4 are equal, the current formula of the sub-threshold region is shown in formula 1.
Figure BDA0002604172970000061
Where K ═ W/L denotes the width-to-length ratio of the transistor, μ denotes the mobility of the transistor, COXRepresenting the oxide capacitance per unit area, m represents the subthreshold slope factor, VTkT/q denotes a thermal voltage, where k, T, and q are a boltzmann constant, an absolute temperature, and a basic charge amount, respectively. VGSAnd VTHRespectively, the gate-source voltage and the threshold voltage of the transistor.
The current equality of the first transistor M1 and the second transistor M2-the fourth transistor M4 can be expressed as formula 2.
Figure BDA0002604172970000062
The parameters of the second transistor M2-the fourth transistor M4 are the same, where K is1、K2Respectively, the width-to-length ratios, μ, of the first transistor M1 and the second transistor M21、μ2Respectively, mobility, C, of the first transistor M1 and the second transistor M2OX1、COX2Respectively, the oxide capacitances M of the first transistor M1 and the second transistor M2 per unit area1、m2Respectively, the sub-threshold slope factors, V, of the first transistor M1 and the second transistor M2TH1、VTH2Respectively showing a first transistor M1 and a second transistor M1Threshold voltage, V, of transistor M2PTATIs the resulting positive temperature coefficient voltage.
V can be obtained by simplifying equation 2PTATThe expression of (c) is shown in equation 3.
Figure BDA0002604172970000071
Wherein suppose COX1＝COX2，m1＝m2，μ1＝μ2，VTH1＝VTH2。K1、K2Is the width-to-length ratio, V, of the first transistor M1 and the second transistor M2, respectivelyPTATIs positively correlated with temperature by adjusting K1And K2The value of (b) may be a positive temperature coefficient with a constant temperature coefficient. Then, because VN is the same as VP due to the clamping effect of the differential operational amplifier, the current flowing through the seventh transistor M7 is expressed as formula 4.
Figure BDA0002604172970000072
Since the currents flowing through the eighth transistor M8 and the seventh transistor M7 are equal due to the 1:1 current copying function of the current mirror of the fifth transistor M5 and the sixth transistor M6, the current flowing through the eighth transistor M8 is expressed as formula 5.
Figure BDA0002604172970000073
Wherein VrefIs the output voltage. Because of I7And I8Theoretically, the values are equal, and V can be obtained by simplifying the formula 5refThe expression of (c) is shown in equation 6.
Figure BDA0002604172970000081
Wherein K7'＝K7μ7COX7(m7-1)，K8'＝K8μ8COX8(m8-1) by fixing K1And K2Regulating K7And K8Can compensate VTH8And VTH7The temperature coefficient of the final output voltage is a three-order minimum term due to the primary and secondary temperature coefficients caused by subtraction, so that better temperature characteristics are realized, namely the reference voltage is considered to be unrelated to the temperature. Compared with the traditional 2-tube series connection type delta VTHA reference voltage generating circuit, the present invention introduces a positive temperature coefficient voltage VPTATMore temperature coefficient related quantities can be adjusted, so that the primary and secondary temperature coefficients can be compensated better, and the low temperature coefficient can be realized. In addition, by designing the width-to-length ratio of the transistors of the first transistor M1, the seventh transistor M7 and the eighth transistor M8 to be less than 1, the quiescent current can be reduced to greatly reduce the power consumption.
Since all transistors operate in the subthreshold region, the present invention can operate at power supply voltages as low as 687 mV.
Fig. 2 is a linear sensitivity characteristic curve of the CMOS voltage reference implemented by the present invention, and it is obvious from the graph that the proposed voltage reference has a poor linear sensitivity, and the linear sensitivity under the TT process angle is 0.1%/V at room temperature, mainly because the width-to-length ratio of the first transistor M1, the seventh transistor M7 and the eighth transistor M8 is less than 1, a large impedance characteristic is presented under direct current, and the change of the power supply will be reflected in the output voltage to a large extent, so the linear sensitivity is not good enough.
Fig. 3 is a PSRR characteristic curve of a CMOS voltage reference implemented using the present invention, with a power supply rejection ratio of about 44.96dB at a frequency of 10Hz, 31.79dB at a frequency of 1kHz, and 32dB at a frequency of 1 MHz. Simulation results show that the CMOS voltage reference has a poor power supply rejection ratio, and also due to the size and the working state of the key tube, the zero point of the output voltage is very small, so that the low-frequency PSRR characteristic is poor; and the most part of the fluctuation of the power supply under the high-frequency condition appears at the output end, the influence of the power supply voltage on the output voltage cannot be effectively inhibited, and in order to weaken the influence, the output capacitor Co is connected in parallel at the output end to play an inhibiting role.
FIG. 4 shows the temperature coefficient of the output reference mainly presents cubic terms, and the average temperature drift coefficient under TT process angle is 6.86 ppm/DEG C, compared with the traditional 2T type delta VTHThe type reference circuit has better temperature characteristic and meets the required zero temperature coefficient reference voltage.
In addition, the invention is characterized in that a reverse tube design is adopted, and except that M5 and M6 are used as current mirrors, all MOS tubes work in a depth subthreshold region, so that the static current is very small. The simulation test shows that when the circuit works under the 687mV power supply voltage, the corresponding power consumption under TT, FF, FS, SF and SS process corners is respectively 0.182nW, 0.356nW, 0.305nW, 0.124nW and 0.089nW, obviously lower than the power consumption of the similar reference circuit adopting the operational amplifier structure, and better accord with the current mainstream IC design concept.
The above description is only a preferred embodiment of the present invention, and the scope of the present invention is not limited to the above embodiment, but equivalent modifications or changes made by those skilled in the art according to the present disclosure should be included in the scope of the present invention as set forth in the appended claims.

Claims (5)

1. An ultra-low power CMOS voltage reference circuit, characterized in that the reference circuit comprises a positive temperature coefficient voltage VPTATA generating part, a differential operational amplifier and a PMOS current mirror; the first transistor (M1) -the fourth transistor (M4) are positive temperature coefficient voltage VPTATThe generating part comprises a ninth transistor (M9) -a fourteenth transistor (M14) which form a differential operational amplifier, a fifth transistor (M5) and a sixth transistor (M6) are PMOS current mirrors, a seventh transistor (M7) is a normal threshold NMOS transistor, and an eighth transistor (M8) is a high threshold NMOS transistor;
positive temperature coefficient voltage VPTATThrough differential operational amplifier voltage clamp and PMOS current mirror current copy, output at the drain terminal of the eighth transistor (M8); a threshold difference Δ V between the seventh transistor (M7) and the eighth transistor (M8) generated during the current copying processTHAnd a positive temperature coefficient voltage V is introducedPTATPerforming more precise temperature coefficient compensation, and simultaneously using an output capacitor (Co) and a compensation capacitor (Cc) to improve the power supply ripple rejection ratio PSRR; input signal (V)DD) The circuit outputs signal (V) as a wholeref）；
The second transistor (M2) -the fourth transistor (M4) are the same in size and are connected in parallel, the drain electrodes are connected with the power supply voltage, the grid electrodes and the source electrodes of the second transistor (M2) -the fourth transistor (M4) are connected with the drain electrode of the first transistor (M1) in series, and then the source electrode of the first transistor (M1) is grounded;
the drain of the first transistor (M1) is connected with the negative polarity input end (VN) of the differential operational amplifier, and the drain of the seventh transistor (M7) is connected with the positive polarity input end (VP) of the differential operational amplifier.
2. The ultra-low power consumption CMOS voltage reference circuit as claimed in claim 1, wherein the fifth transistor (M5), the sixth transistor (M6), the eleventh transistor (M11), the twelfth transistor (M12), the thirteenth transistor (M13) and the fourteenth transistor (M14) are PMOS transistors, and the rest are NMOS transistors.
3. The ultra-low power consumption CMOS voltage reference circuit as claimed in claim 1, wherein in said differential operational amplifier, the branch of the ninth transistor (M9), the eleventh transistor (M11), the thirteenth transistor (M13) and the branch of the tenth transistor (M10), the twelfth transistor (M12), the fourteenth transistor (M14) are completely symmetrical, but the gates of the eleventh transistor (M11) and the thirteenth transistor (M13) are connected to their own drains to realize biasing, so as to form the stacked differential operational amplifier.
4. The ultra-low power CMOS voltage reference circuit of claim 1, wherein the output signal of the differential op-amp is C: the output signal of the whole circuit is Vref(ii) a The compensation capacitor (Cc) is connected between the power supply and the grid electrode of the fifth transistor (M5), the output (C) of the differential operational amplifier is also connected with the grid electrode of the fifth transistor (M5), and then the source electrode of the fifth transistor (M5) and the grid electrode of the fifth transistor (M5)The drain electrodes are respectively connected with the power supply and the drain electrode of the seventh transistor (M7), the source electrode of the seventh transistor (M7) is grounded, and the grid electrode of the seventh transistor is connected with the drain electrode of the seventh transistor.
5. The ultra-low power consumption CMOS voltage reference circuit as claimed in claim 1, wherein the sixth transistor (M6) is connected to the gate of the fifth transistor (M5), and the source and drain of the sixth transistor (M6) are connected to the power supply and the drain of the eighth transistor (M8), respectively; the gate of the eighth transistor (M8) is connected to its drain and the source is grounded, and the output capacitor (Co) is connected between the drain of the eighth transistor (M8) and ground.
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