CN115469704A - High PSRR sub-threshold CMOS reference voltage source - Google Patents

High PSRR sub-threshold CMOS reference voltage source Download PDF

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CN115469704A
CN115469704A CN202211030575.9A CN202211030575A CN115469704A CN 115469704 A CN115469704 A CN 115469704A CN 202211030575 A CN202211030575 A CN 202211030575A CN 115469704 A CN115469704 A CN 115469704A
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tube
pmos
pmos tube
temperature coefficient
nmos
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宋树祥
曾范洋
蒋品群
蔡超波
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Guangxi Normal University
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/567—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for temperature compensation

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Abstract

The invention relates to the technical field of CMOS transistor circuits, in particular to a high PSRR sub-threshold CMOS reference voltage source; the self-bias circuit comprises a self-bias circuit and positive and negative temperature coefficient voltage generation modules, wherein two ends of the self-bias circuit are respectively electrically connected with the positive and negative temperature coefficient voltage generation modules, and the self-bias circuit is used for reducing power supply voltage V DDL The influence of medium ripple noise on the bias current, and the positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage V is generated by adopting a subthreshold region PMOS structure difference PTAT The reference voltage V with zero temperature coefficient can be improved by the structure REF The accuracy of the method.

Description

High PSRR sub-threshold CMOS reference voltage source
Technical Field
The invention relates to the technical field of CMOS transistor circuits, in particular to a high PSRR sub-threshold CMOS reference voltage source.
Background
The reference voltage source is an important component of the modern analog integrated circuit, provides reference voltage for a series voltage stabilizing circuit, an A/D converter and a D/A converter, is also a voltage stabilizing power supply or an excitation source of most sensors, and can also be used as a standard battery, a scale standard of an instrument head and a precise current source
Zero temperature currently obtained using an output reference voltage sourceReference voltage V of degree coefficient REF Is not accurate.
Disclosure of Invention
The invention aims to provide a high PSRR sub-threshold CMOS reference voltage source, which solves the problem of obtaining a reference voltage V with zero temperature coefficient REF The problem of inaccuracy.
In order to achieve the above object, the high PSRR sub-threshold CMOS reference voltage source adopted in the present invention includes a self-bias circuit and a positive and negative temperature coefficient voltage generating module, wherein two ends of the self-bias circuit are electrically connected to the positive and negative temperature coefficient voltage generating module, respectively;
the self-bias circuit is used for reducing the supply voltage V DDL The influence of medium ripple noise on the bias current;
the positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT Adopting sub-threshold region PMOS structure to generate positive temperature coefficient voltage V PTAT ；
Passing voltage V CTAT And voltage V PTAT The superposition and summation obtain the reference voltage V with zero temperature coefficient REF 。
Wherein the positive and negative temperature coefficient voltage generating module comprises a negative temperature coefficient voltage generating module and a positive temperature coefficient voltage generating module, the negative temperature coefficient voltage generating module is electrically connected with one end of the self-biasing circuit, the positive temperature coefficient voltage generating module is electrically connected with the other end of the self-biasing circuit,
the negative temperature coefficient voltage generation module is used for generating a negative temperature coefficient voltage V CTAT ；
The positive temperature coefficient voltage generating module is used for generating positive temperature coefficient voltage V PTAT 。
Wherein, the positive and negative temperature coefficient voltage generating module comprises a PMOS tube PM 3 PMOS tube PM 4 PMOS tube PM 5 PMOS tube PM 6 PMOS tube PM 7 PMOS tube PM 8 PMOS tube PM 9 PMOS tube PM 10 PMOS tube PM 11 And NMOS tube NM 7 PM of the PMOS tube 3 And the PMOS tube PM is electrically connected with the self-bias circuit 4 And the PMOS tube PM 3 Electrically connected, the PMOS tube PM 5 Respectively connected with the PMOS tube PM 4 And the PMOS pipe PM 3 Electrically connected, the PMOS tube PM 5 The PMOS tube PM 6 The PMOS tube PM 7 The PMOS tube PM 8 The PMOS tube PM 9 And the PMOS pipe PM 10 Cascade of said PMOS tubes PM 11 And the PMOS tube PM 10 Electrical connection, the NMOS tube NM 7 Respectively connected with the PMOS tube PM 11 And the PMOS pipe PM 4 And (6) electrically connecting.
The high PSRR sub-threshold CMOS reference voltage source further comprises a low-pass filter, and the low-pass filter and the NMOS tube NM 7 Electrically connecting;
the low-pass filter is used for converting a reference voltage V REF To ground, reducing the reference voltage V REF High frequency noise of (2).
Wherein the self-bias circuit comprises an NMOS tube NM 1 NMOS tube NM 2 NMOS tube NM 3 NMOS tube NM 4 NMOS tube NM 5 NMOS tube NM 6 NMOS tube NM 8 NMOS tube NM 9 PMOS tube PM 1 PMOS tube PM 2 PMOS tube PM 12 PMOS tube PM 13 PMOS tube PM 14 MOS transistor M R1 And MOS tube M B1 PM of the PMOS tube 1 And the PMOS pipe PM 2 Respectively connected with the PMOS tube PM 3 Electric connection, the NMOS tube NM 9 And said NMOS tube NM 8 Electrically connected, the PMOS tube PM 14 And said NMOS tube NM 9 Electrically connected, the PMOS tube PM 13 And the PMOS tube PM 14 Electrically connected, PMOS transistor PM 12 And the PMOS tube PM 13 Electrically connected, the PMOS tube PM 1 Are respectively connected with NMOS tube NM 3 And the PMOS pipe PM 12 Electrically connected, the PMOS tube PM 2 Are respectively connected with NMOS tube NM 4 And the PMOS pipe PM 12 Electric connection, the NMOS tube NM 1 Respectively connected with the NMOS tubes NM 3 And stationThe NMOS tube NM 9 Electric connection, the NMOS tube NM 2 Are respectively connected with the NMOS tube NM 4 And the MOS transistor M R1 Electric connection, the MOS tube M R1 And said NMOS tube NM 9 Electric connection, the NMOS tube NM 5 Respectively connected with the MOS transistor M R1 And said NMOS tube NM 6 Electrical connection, the MOS tube M B1 Respectively connected with the MOS transistor M R1 And said NMOS tube NM 6 And (6) electrically connecting.
According to the high-PSRR sub-threshold CMOS reference voltage source, the self-bias circuit reduces the supply voltage V DDL The positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage V is generated by adopting a subthreshold region PMOS structure difference PTAT Passing voltage V CTAT And voltage V PTAT The superposition and summation obtain the reference voltage V with zero temperature coefficient REF Obtaining a reference voltage V with zero temperature coefficient REF Accurate data and obtaining the reference voltage V for improving the zero temperature coefficient REF The accuracy of the method.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the prior art descriptions will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a schematic circuit diagram of a high PSRR sub-threshold CMOS reference voltage source of the present invention.
Fig. 2 is a schematic circuit diagram of the positive and negative temperature coefficient voltage generating module of the present invention.
Fig. 3 is a circuit schematic of the self-biasing circuit of the present invention.
Fig. 4 is a circuit schematic of the preconditioning circuit of the present invention.
Fig. 5 is a power supply rejection ratio simulation graph of the reference voltage source of the present invention.
Fig. 6 is a schematic circuit diagram of the reference voltage trimming module according to the present invention.
Fig. 7 is a graph showing a simulation of the temperature characteristic of the reference voltage source of the present invention.
The device comprises a 1-self-bias circuit, a 2-negative temperature coefficient voltage generation module, a 3-positive temperature coefficient voltage generation module, a 4-low-pass filter, a 5-pre-regulation circuit and a 6-reference voltage trimming module.
Detailed Description
Referring to fig. 1 to 7, fig. 1 is a schematic circuit diagram of a high PSRR sub-threshold CMOS reference voltage source, fig. 2 is a schematic circuit diagram of a positive and negative temperature coefficient voltage generating module, fig. 3 is a schematic circuit diagram of a self-bias circuit, fig. 4 is a schematic circuit diagram of a pre-regulator circuit, fig. 5 is a simulation graph of a power supply rejection ratio of the reference voltage source, fig. 6 is a schematic circuit diagram of a reference voltage trimming module, and fig. 7 is a simulation graph of a temperature characteristic of the reference voltage source. The invention provides a high PSRR sub-threshold CMOS reference voltage source, which comprises a self-bias circuit 1 and a positive and negative temperature coefficient voltage generation module, wherein two ends of the self-bias circuit 1 are respectively electrically connected with the positive and negative temperature coefficient voltage generation module;
the self-bias circuit 1 is used for reducing the supply voltage V DDL The influence of medium ripple noise on the bias current;
the positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage V is generated by adopting a subthreshold region PMOS structure difference PTAT ；
Passing voltage V CTAT And voltage V PTAT The superposition and summation obtain the reference voltage V with zero temperature coefficient REF 。
In the present embodiment, the self-bias circuit 1 reduces the supply voltage V DDL The positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage V is generated by adopting a subthreshold region PMOS structure difference PTAT Passing voltage V CTAT And voltage V PTAT The superposition and summation obtain the reference voltage V with zero temperature coefficient REF Obtaining a reference voltage V with zero temperature coefficient REF Accurate data and reference voltage V for improving zero temperature coefficient REF The accuracy of the method.
Further, the positive and negative temperature coefficient voltage generating module comprises a negative temperature coefficient voltage generating module 2 and a positive temperature coefficient voltage generating module 3, the negative temperature coefficient voltage generating module 2 is electrically connected with one end of the self-bias circuit 1, the positive temperature coefficient voltage generating module 3 is electrically connected with the other end of the self-bias circuit 1,
the negative temperature coefficient voltage generation module 2 is used for generating a negative temperature coefficient voltage V CTAT ；
The positive temperature coefficient voltage generating module 3 is used for generating a positive temperature coefficient voltage V PTAT 。
In the present embodiment, the negative temperature coefficient voltage generation module 2 generates a negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage generating module 3 generates a positive temperature coefficient voltage V PTAT 。
Furthermore, the positive and negative temperature coefficient voltage generating module comprises a PMOS tube PM 3 PMOS tube PM 4 PMOS tube PM 5 PMOS tube PM 6 PMOS tube PM 7 PMOS tube PM 8 PMOS tube PM 9 PMOS tube PM 10 PMOS tube PM 11 And NMOS tube NM 7 PM of the PMOS tube 3 Electrically connected with the self-bias circuit 1, the PMOS tube PM 4 And the PMOS tube PM 3 Electrically connected, the PMOS tube PM 5 Respectively connected with the PMOS tube PM 4 And the PMOS pipe PM 3 Electrically connected, the PMOS tube PM 5 The PMOS tube PM 6 The PMOS tube PM 7 The PMOS tube PM 8 The PMOS tube PM 9 And the PMOS pipe PM 10 Cascade, the PMOS tube PM 11 And the PMOS tube PM 10 Electrical connection, the NMOS tube NM 7 Respectively connected with the PMOS tube PM 11 And the PMOS pipe PM 4 And (6) electrically connecting.
In this embodiment, the gate-source voltage V of the sub-threshold MOS transistor GS The expression is as follows:
Figure BDA0003817046230000041
wherein, mu represents the carrier mobility of the MOS tube, C ox The gate oxide capacitance per unit area is expressed, K represents the width-to-length ratio,
Figure BDA0003817046230000042
representing a sub-threshold slope factor. V T = kt/q denotes a thermal voltage, where κ is a boltzmann constant and q denotes an amount of electron charge. Wherein the MOS transistor has a threshold voltage V TH The expression of (a) is:
Figure BDA0003817046230000051
the negative temperature coefficient voltage drives the PMOS tube PM by bias current 4 The generation, according to formula (1), can be:
Figure BDA0003817046230000052
the positive temperature coefficient voltage is controlled by the PMOS tube PM 5 -PMOS tube PM 10 Three classes of differential structures are cascaded, which can be obtained according to equation (1):
Figure BDA0003817046230000053
the positive and negative temperature coefficient voltages are superposed to obtain a reference voltage V REF The expression of (a) is:
Figure BDA0003817046230000054
PM flowing through PMOS tube by reasonable design 4 On quiescent current ofAnd the size of the rest MOS tubes, namely the reference voltage V approximately independent of the temperature change in a certain range can be obtained REF 。
Further, the high PSRR sub-threshold CMOS reference voltage source further includes a low-pass filter 4, and the low-pass filter 4 and the NMOS transistor NM 7 Electrically connecting;
the low-pass filter 4 is used for converting the reference voltage V REF To ground, reducing the reference voltage V REF High frequency noise of (2).
In the present embodiment, the low-pass filter 4 converts the reference voltage V into the voltage V REF To ground, reducing the reference voltage V REF High frequency noise of (2).
Further, the self-bias circuit 1 comprises an NMOS tube NM 1 NMOS tube NM 2 NMOS tube NM 3 NMOS tube NM 4 NMOS tube NM 5 NMOS tube NM 6 NMOS tube NM 8 NMOS tube NM 9 PMOS tube PM 1 PMOS tube PM 2 PMOS tube PM 12 PMOS tube PM 13 PMOS tube PM 14 MOS transistor M R1 And MOS transistor M B1 PM of the PMOS tube 1 And the PMOS pipe PM 2 Respectively connected with the PMOS tube PM 3 Electric connection, the NMOS tube NM 9 And said NMOS transistor NM 8 Electrically connected, the PMOS tube PM 14 And said NMOS tube NM 9 Electrically connected, the PMOS tube PM 13 And the PMOS tube PM 14 Electrically connected, PMOS transistor PM 12 And the PMOS tube PM 13 Electrically connected, the PMOS tube PM 1 Are respectively connected with NMOS tube NM 3 And the PMOS pipe PM 12 Electrically connected, the PMOS tube PM 2 Are respectively connected with NMOS tube NM 4 And the PMOS pipe PM 12 Electrical connection, the NMOS tube NM 1 Respectively connected with the NMOS tubes NM 3 And said NMOS tube NM 9 Electric connection, the NMOS tube NM 2 Are respectively connected with the NMOS tube NM 4 And the MOS transistor M R1 Electric connection, the MOS tube M R1 And said NMOS tube NM 9 Electrical connection, the NMOS tube NM 5 Respectively with said MOS tube M R1 And said NMOS tube NM 6 Electric connection, the MOS tube M B1 Respectively connected with the MOS transistor M R1 And said NMOS tube NM 6 And (6) electrically connecting.
In this embodiment, a cascode device and a differential operational amplifier feedback structure are added to the self-bias circuit 1 with an all-MOS structure, so as to reduce the supply voltage V DDL The influence of medium ripple noise on the bias current improves the precision of the output reference voltage, and the NMOS tube NM 8 The NMOS tube NM 9 The PMOS tube PM 12 The PMOS tube PM 13 And the PMOS pipe PM 14 The combination obtains starting circuit, and starting circuit can produce the current path fast and break away from the zero current steady state, makes the circuit normally start, and simultaneously, starting circuit will be after reference voltage source core circuit normal operating self-closing, reduces quiescent current's consumption, and starting circuit's working process is: at supply voltage rising from zero to V DDL When, V REF At low level, the PMOS transistor PM 12 The PMOS tube PM 13 And the PMOS pipe PM 14 Is turned on to make the NMOS tube NM 8 And the PMOS pipe PM 1 And the circuit is conducted and starts to work normally. When V is DDL After the electrification is finished and the reference voltage source enters a normal working state, the reference voltage V REF Make the PMOS tube PM 14 Off and said NMOS transistor NM 9 Conducting to make the NMOS tube NM 8 And turning off the starting circuit.
Further, the high PSRR sub-threshold CMOS reference voltage source further includes a pre-regulation circuit 5, the pre-regulation circuit 5 is electrically connected to the positive and negative temperature coefficient voltage generation module and the self-bias circuit 1, the pre-regulation circuit 5 is configured to primarily stabilize the power supply voltage, and reduce ripple noise of the low-frequency power supply from the reference voltage V REF The influence of (c).
In this embodiment, the pre-regulation circuit 5 primarily stabilizes the power supply voltage to reduce the ripple noise of the low-frequency power supply to the reference voltage V REF The influence of (c).
Further, the pre-conditioning circuit 5 comprises a MOS transistor M 1 、MOS tube M 2 MOS tube M 3 MOS transistor M 4 MOS transistor M 5 MOS transistor M 6 MOS tube M 7 MOS tube M 8 MOS transistor M 9 MOS transistor M 10 MOS transistor M 11 MOS transistor M 12 MOS transistor M 13 MOS transistor M 14 MOS transistor M 15 MOS transistor M 16 MOS transistor M 17 MOS transistor M 18 And MOS transistor M 19 The MOS transistor M 15 And the MOS transistor M 16 Respectively connected with the PMOS tube PM 3 The PMOS tube PM 1 The PMOS tube PM 2 The PMOS tube PM 12 Electric connection, the MOS tube M 2 Respectively connected with the MOS transistor M 1 And the MOS transistor M 3 Electrical connection, the MOS tube M 4 Respectively connected with the MOS transistor M 3 And the MOS transistor M 7 Electrical connection, the MOS tube M 6 Respectively connected with the MOS transistor M 5 And the MOS transistor M 7 Electric connection, the MOS tube M 8 Respectively connected with the MOS transistor M 9 And the MOS transistor M 5 Electric connection, the MOS tube M 10 Respectively connected with the MOS transistor M 8 And the MOS transistor M 11 The MOS transistor M 12 Respectively connected with the MOS transistor M 9 The MOS tube M 11 And the MOS transistor M 14 Electric connection, the MOS tube M 13 And the MOS tube M 11 Electric connection, the MOS tube M 16 Respectively connected with the MOS transistor M 15 The MOS tube M 18 And the MOS transistor M 19 Electric connection, the MOS tube M 17 Respectively connected with the MOS transistor M 15 The MOS tube M 18 And the MOS transistor M 19 And (6) electrically connecting.
In the present embodiment, the preconditioning circuit 5 is capable of applying the supply voltage V DD After regulation, a controlled V is generated DD Supply voltage V with little influence DDL The power supply voltage of the reference voltage source is isolated from the power supply voltage of the whole circuit, so that the influence of low-frequency power supply ripple noise on a reference source core circuit is reduced, and the power supply rejection ratio of the reference voltage source is improved.
Feedback voltage V of operational amplifier FB Is equal toSupply voltage V DDL In the MOS transistor M 17 And the MOS tube M 18 The expression of the partial pressure of (c) is:
Figure BDA0003817046230000071
output voltage V OUT The expression of (c) is:
V OUT ＝(V FB -V GSS )A OP ＝V GS16 +V DDL #(7)
in the formula, A OP V can be obtained by substituting equation (7) into equation (6) representing the gain of the differential operational amplifier DDL The expression of (a) is:
Figure BDA0003817046230000072
when A is OP When large enough, equation (8) can be simplified as:
Figure BDA0003817046230000073
from the equation (9), as the gain of the differential operational amplifier increases, V DDL And V DD The smaller the correlation of (a), the stronger the power supply rejection capability of the reference voltage source. In addition, because of the influence of parasitic effect, the power supply rejection performance of the reference voltage source is sharply reduced in a high frequency band, the low pass filter 4 composed of a MOS resistor and a capacitor is added to the output end of the reference voltage source, and the transfer function of the low pass filter 4 is:
Figure BDA0003817046230000074
according to the equation (10) and the power supply rejection ratio simulation graph of the reference voltage source, after the low-pass filter 4 is added, the high-frequency noise signal in the circuit can directly flow into the ground, so that the capability of the reference voltage source for suppressing the high-frequency power supply ripple noise is improved.
Further, the high PSRR sub-threshold CMOS reference voltage source further includes a reference voltage trimming module 6, and the reference voltage trimming module 6 is electrically connected to the self-bias circuit 1 and the negative temperature coefficient voltage generating module 2, respectively;
the reference voltage trimming module 6 is used for adjusting reference voltages V under different process angles REF Size.
In this embodiment, as can be seen from expressions (1) and (2), the PMOS transistor PM can be changed by a MOS transistor substrate voltage driving technique 4 Substrate voltage V SUB Adjusting its threshold voltage V TH,PM4 Can be applied to negative temperature coefficient voltage | V GS,PM4 I, trimming and maintaining output reference voltage V REF The stability of (3).
In the reference voltage trimming module 6, bit [ x ]]For the input signal, dx]B and D [ x ]]Is the output signal. When D [0 ]]When the voltage is high potential, the trimming circuit is turned off, and the PMOS tube PM 4 Lining source short circuit of V SUB ＝V CTAT (ii) a When D [0 ]]When the potential is low, the trimming circuit starts to work. At D [1 ]]Is at a high potential, D2]At low potential, V SUB ＝V TRIM1 At this time V BS,MPM4 Is positive; when D [1 ]]Is low potential, D2]At a high potential, V SUB ＝V TRIM2 At this time V BS,MPM4 Is negative, D [3 ]]～D[6]The current flowing through the MOS resistor can be controlled, so that the reference voltage trimming module 6 can meet the deviation of the reference power supply generated at different process corners. According to the temperature characteristic simulation curve chart of the reference voltage source under different process angles, under SS and FF process angles, the performance parameters obtained by simulation are listed as follows:
Figure BDA0003817046230000081
wherein the deviation ratio represents a ratio of a deviation of the reference voltage at the SS or FF process corner to an average value of the reference voltage at the TT process corner.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (5)

1. A high PSRR sub-threshold CMOS reference voltage source,
the device comprises a self-bias circuit and a positive and negative temperature coefficient voltage generation module, wherein two ends of the self-bias circuit are respectively electrically connected with the positive and negative temperature coefficient voltage generation module;
the self-bias circuit is used for reducing the supply voltage V DDL The influence of medium ripple noise on the bias current;
the positive and negative temperature coefficient voltage generation module adopts a sub-threshold region PMOS tube to generate negative temperature coefficient voltage V CTAT The positive temperature coefficient voltage V is generated by adopting a subthreshold region PMOS structure difference PTAT ；
Passing voltage V CTAT And voltage V PTAT The superposition and summation obtain the reference voltage V with zero temperature coefficient REF 。
2. The high PSRR sub-threshold CMOS reference voltage source of claim 1,
the positive and negative temperature coefficient voltage generating module comprises a negative temperature coefficient voltage generating module and a positive temperature coefficient voltage generating module, the negative temperature coefficient voltage generating module is electrically connected with one end of the self-biasing circuit, the positive temperature coefficient voltage generating module is electrically connected with the other end of the self-biasing circuit,
the negative temperature coefficient voltage generation module is used for generating negative temperature coefficient voltage V CTAT ；
The positive temperature coefficient voltage generating module is used for generating positive temperature coefficient voltage V PTAT 。
3. The high PSRR sub-threshold CMOS reference voltage source of claim 1,
the positive and negative temperature coefficient voltage generation module comprises a PMOS (P-channel metal oxide semiconductor) tube PM 3 PMOS tube PM 4 PMOS tube PM 5 PMOS tube PM 6 PMOS tube PM 7 PMOS tube PM 8 PMOS tube PM 9 PMOS tube PM 10 PMOS tube PM 11 And NMOS tube NM 7 PM of the PMOS tube 3 And the PMOS tube PM is electrically connected with the self-bias circuit 4 And the PMOS tube PM 3 Electrically connected, the PMOS tube PM 5 Respectively connected with the PMOS tube PM 4 And the PMOS pipe PM 3 Electrically connected, the PMOS tube PM 5 The PMOS tube PM 6 The PMOS tube PM 7 The PMOS tube PM 8 The PMOS tube PM 9 And the PMOS pipe PM 10 Cascade of said PMOS tubes PM 11 And the PMOS tube PM 10 Electrical connection, the NMOS tube NM 7 Respectively connected with the PMOS tube PM 11 And the PMOS tube PM 4 And (6) electrically connecting.
4. The high PSRR sub-threshold CMOS reference voltage source of claim 3,
the high PSRR sub-threshold CMOS reference voltage source further comprises a low-pass filter, and the low-pass filter and the NMOS tube NM 7 Electrically connecting;
the low-pass filter is used for converting a reference voltage V REF To ground, reducing the reference voltage V REF High frequency noise of (2).
5. The high PSRR sub-threshold CMOS reference voltage source of claim 3,
the self-bias circuit comprises an NMOS tube NM 1 NMOS tube NM 2 NMOS tube NM 3 NMOS tube NM 4 NMOS tube NM 5 NMOS tube NM 6 NMOS tube NM 8 NMOS tube NM 9 PMOS tube PM 1 PMOS tube PM 2 PMOS tube PM 12 PMOS tube PM 13 PMOS tube PM 14 MOS transistor M R1 And MOS transistor M B1 PM of the PMOS tube 1 And the PMOS tube PM 2 Respectively connected with the PMOS tube PM 3 Electrical connectionSaid NMOS tube NM 9 And said NMOS tube NM 8 Electrically connected, the PMOS tube PM 14 And said NMOS tube NM 9 Electrically connected, the PMOS tube PM 13 And the PMOS tube PM 14 Electrically connected, PMOS transistor PM 12 And the PMOS tube PM 13 Electrically connected, the PMOS tube PM 1 Are respectively connected with NMOS tube NM 3 And the PMOS pipe PM 12 Electrically connected, the PMOS tube PM 2 Are respectively connected with NMOS tube NM 4 And the PMOS pipe PM 12 Electric connection, the NMOS tube NM 1 Respectively connected with the NMOS tubes NM 3 And said NMOS tube NM 9 Electrical connection, the NMOS tube NM 2 Are respectively connected with the NMOS tube NM 4 And the MOS transistor M R1 Electric connection, the MOS tube M R1 And said NMOS tube NM 9 Electric connection, the NMOS tube NM 5 Respectively connected with the MOS transistor M R1 And said NMOS tube NM 6 Electric connection, the MOS tube M B1 Respectively connected with the MOS transistor M R1 And said NMOS transistor NM 6 And (6) electrically connecting.
CN202211030575.9A 2022-08-26 2022-08-26 High PSRR sub-threshold CMOS reference voltage source Withdrawn CN115469704A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116225142A (en) * 2023-05-06 2023-06-06 上海灵动微电子股份有限公司 Non-resistance band gap reference voltage source, reference voltage generating method and integrated circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116225142A (en) * 2023-05-06 2023-06-06 上海灵动微电子股份有限公司 Non-resistance band gap reference voltage source, reference voltage generating method and integrated circuit

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Application publication date: 20221213