CN115933795B - Ultra-low power consumption reference current source circuit applied to power management unit - Google Patents
Ultra-low power consumption reference current source circuit applied to power management unit Download PDFInfo
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Abstract
The invention discloses an ultra-low power consumption reference current source circuit applied to a power management unit, which relates to the technical field of analog integrated circuit design and comprises a process angle compensation bias circuit, a negative temperature coefficient bias generation circuit and a current reference output stage circuit, wherein the process angle compensation bias circuit is used for generating bias voltages to compensate different process angle changes of threshold voltages; the negative temperature coefficient bias generating circuit is used for generating a voltage which is inversely related to the absolute temperature; the current reference output stage circuit is used for outputting reference current, so that current references based on threshold voltage temperature coefficients of the grid compensation MOS tube are introduced for different process angles, the pA-level reference current is obtained, the chip area is reduced, and the working performance of the system is improved.
Description
Technical Field
The invention relates to the technical field of analog integrated circuit design, in particular to an ultralow-power consumption reference current source circuit applied to a power management unit.
Background
The chip in different electronic products is composed of different modules, each module has a specific function, the function of the electronic product chip is realized by combining the modules together, the current reference has wide application in integrated circuits, and is an important basic module in a power management unit for providing reference current which is not influenced by working voltage, load current, temperature, time or other factors for the whole circuit.
For ultra-low power consumption internet of things sensing devices, these devices can only be powered by a battery or an energy harvesting system that provides limited energy, where the current reference circuit consumes a significant portion of the power in sleep mode in order to be able to operate at 100% duty cycle, and therefore it is of great importance for the power management unit in the energy harvesting system to study the pA level current reference.
At present, the structure of a reference current source is mainly divided into two types, wherein the first type is a structure that a bias circuit is connected with a resistor, the structure needs 1G omega or more resistor to generate pA class current, which occupies a large layout area, and the structure needs an additional starting circuit to avoid degeneracy points of the circuit; the second is a voltage reference and resistor structure, which introduces an operational amplifier, generates current by resistor voltage division, has larger power consumption, and the process variation amplitude of polysilicon resistor is up to +/-25%, which can cause larger fluctuation of the generated reference current along with the process variation.
Because the traditional ultra-low power consumption current reference circuit has the problems of large process deviation, large area, high power consumption and the like, the requirement of power supply of an energy acquisition system cannot be met, and in order to obtain ultra-low power consumption pA-level current, a plurality of current reference technologies based on sub-threshold MOS (metal oxide semiconductor) tubes are sequentially proposed, but the process deviation of the sub-threshold MOS tubes also changes along with the changes of temperature, voltage and process angle, so that fluctuation of output current is caused, and it is important to research a sub-threshold process angle deviation compensation to obtain the ultra-low power consumption pA-level current reference circuit.
In summary, the present invention is directed to providing a current reference based on a threshold voltage temperature coefficient of a gate-compensated MOS transistor to overcome the above-mentioned drawbacks.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides an ultra-low power consumption reference current source circuit applied to a power management unit, comprising
The process angle compensation bias circuit is used for generating bias voltage VREFB to compensate the change of threshold voltage at different process angles, and the subthreshold current formula is as follows:
wherein μ represents carrier mobility, C ox Represents a gate oxide layer per unit area, m represents a subthreshold slope factor, V T =kt/q denotes thermal voltage, proportional to temperature; W/L represents the width-to-length ratio of MOS tube, V GS Representing MOS gate-source voltage, V TH Represents the threshold voltage of the MOS transistor, due to mu and V T、 V TH All will change with temperature and V GS Also with temperature, the subthreshold current is:
wherein T is r Absolute room temperature, k 1 、k 2 Mu and V respectively TH Is used for the temperature coefficient of (a),
at T r The threshold voltage at temperature is V obtained by the formula (2) GS Inversely related to temperature, to compensate for the temperature coefficient of the threshold voltage, let V be GS The expression is:
to make dI D dT at temperature T r When equal to 0, can be obtained:
as can be seen from the formula (4),
the initial value is->
Influence (S)>
Can be changed along with the change of the process angle, and different +.>
；
A negative temperature coefficient bias generating circuit for generating a voltage inversely related to an absolute temperature,
a current reference output stage circuit for outputting a reference current I independent of temperature and input voltage REF 。
The technical scheme of the invention is as follows:
further, the process corner compensation bias circuit comprises an N-type field effect transistor M1, an N-type field effect transistor M2 and an N-type field effect transistor M3, and the bias voltage V is adjusted by adjusting the sizes of the N-type field effect transistor M1, the N-type field effect transistor M2 and the N-type field effect transistor M3 REFB Is a process angle deviation of (2);
the drain electrode of the N-type field effect transistor M1 is connected with the power supply VDD, the grid electrode is connected with the source electrode of the N-type field effect transistor M1, and the source electrode outputs bias voltage V REFB ；
The drain electrode of the N-type field effect transistor M2 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M3, and the source electrode is connected with the drain electrode of the N-type field effect transistor M3;
the gate of the N-type field effect transistor M3 is connected with the drain thereof, and the source thereof is connected with the ground GND.
In the aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, the N-type field effect transistor M1 is set as a low threshold NMOS transistor, the threshold voltage of the low threshold NMOS transistor is set to be lower than 200mv, the N-type field effect transistor M2 and the N-type field effect transistor M3 are both set as high threshold NMOS transistors, and the threshold voltage of the high threshold NMOS transistor is set to 750-950 mv.
The aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, the negative temperature coefficient bias generating circuit comprises an N-type field effect transistor M4, an N-type field effect transistor M5 and an N-type field effect transistor M6, and the sizes of the N-type field effect transistor M4, the N-type field effect transistor M5 and the N-type field effect transistor M6 are adjusted to enable the N-type field effect transistor M4 to have a negative temperature coefficient;
the drain electrode of the N-type field effect transistor M4 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M5, and the source electrode is connected with the drain electrode of the N-type field effect transistor M5;
the drain electrode of the N-type field effect transistor M5 is connected to the grid electrode of the N-type field effect transistor M6, and the source electrode of the N-type field effect transistor M5 is connected to the drain electrode of the N-type field effect transistor M6;
the drain of the N-type field effect transistor M6 is connected to the gate and the source is connected to ground GND.
In the aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, the N-type field effect transistor M4, the N-type field effect transistor M5 and the N-type field effect transistor M6 are all set as high threshold NMOS transistors, and the threshold voltage of the high threshold NMOS transistors is set to 750-950 mv.
In the aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, the aspect ratio of the N-type field effect transistor M5 and the N-type field effect transistor M6 is set to be the same.
The aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, wherein the current reference output stage circuit comprises a P-type field effect transistor M7 and an N-type field effect transistor M8, the gate voltage VG of the N-type field effect transistor M8 has a negative temperature coefficient for counteracting the temperature coefficient of the threshold voltage of the N-type field effect transistor M8, thereby obtaining a current with zero temperature coefficient, and finally the obtained reference current is copied and output through the gate of the P-type field effect transistor M7;
the source electrode of the P-type field effect transistor M7 is connected with a power supply VDD, and the grid electrode is connected with the drain electrode of the P-type field effect transistor M7;
the source of the N-type field effect transistor M8 is connected to the drain of the P-type field effect transistor M7, the gate is connected to the drain of the N-type field effect transistor M5, and the source is grounded GND.
In the aforementioned ultra-low power consumption reference current source circuit applied to the power management unit, the P-type field effect transistor M7 is set as a standard threshold PMOS transistor, the N-type field effect transistor M8 is set as a standard threshold NMOS transistor, and the threshold voltages of the standard threshold PMOS transistor and the standard threshold NMOS transistor are both set to 360-460 v.
The beneficial effects of the invention are as follows:
(1) In the invention, a process angle compensation bias circuit is used for generating a bias voltage V REFB To compensate for different process angle variations, wherein V is trimmed by N-type field effect transistor M1, N-type field effect transistor M2, and N-type field effect transistor M3 REFB Is a process angle deviation of (2); then the negative temperature coefficient bias generating circuit is used for generating voltage which is inversely related to absolute temperature, and finally the current reference output stage circuit is used for outputting reference current I REF The method comprises the steps of carrying out a first treatment on the surface of the Within the range of 0-1.5V of power supply voltage, V is under the technological angle of FF to TT REFB Phase difference of 105mV to provide process angle compensation; at TT Process corner, I REF About 100pA with a temperature coefficient of 412 ppm/DEG C; at normal temperature, within all process angle ranges, I REF The current range of (1) is 91-131 pA; therefore, after the process angle is compensated, the current reference in the invention can generate reference current with smaller phase difference under all process angles without trimming a regulating circuit, and the current reference designed in the embodiment is only 651pA under the process angles of 1V, 25 ℃ and TT of power supply voltage, thereby being suitable for the application scene of ultra-low power in an energy acquisition system;
(2) The invention effectively solves the problems of large deviation and large power consumption of the output current of the traditional current reference circuit along with the change of different process angles, has simple structure, realizes pA-level reference current by only few MOS transistors with different thresholds, occupies small chip area and is beneficial to layout.
Drawings
FIG. 1 is a block diagram of the overall principle of an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of an embodiment of the present invention;
FIG. 3 is a schematic diagram showing the variation of threshold voltage according to the process corner variation in the embodiment of the invention;
FIG. 4 is a simulation diagram of bias voltages at different process angles in an embodiment of the present invention;
FIG. 5 is a simulation diagram of reference current at different process angles in an embodiment of the present invention.
Detailed Description
The ultralow power consumption reference current source circuit applied to the power management unit provided in this embodiment, as shown in fig. 1, includes a process corner compensation bias circuit, a negative temperature coefficient bias generating circuit and a current reference output stage circuit, where the process corner compensation bias circuit is used to generate a bias voltage V REFB To compensate for different process angle variations, and to fine tune V by using N-type field effect transistor M1, N-type field effect transistor M2 and N-type field effect transistor M3 REFB Is a process angle deviation of (2); the negative temperature coefficient bias generating circuit is used for generating a voltage which is inversely related to the absolute temperature; the current reference output stage circuit is used for outputting reference current I irrelevant to temperature, input voltage and the like REF 。
The process angle compensation bias circuit generates different bias voltages under different process angles to compensate the change of the process angles, and the subthreshold current formula is as follows:
wherein μ represents carrier mobility, C ox Represents a gate oxide layer per unit area, m represents a subthreshold slope factor, V T =kt/q denotes thermal voltage, proportional to temperature; W/L represents the width-to-length ratio of MOS tube, V GS Representing MOS gate-source voltage, V TH Represents the threshold voltage of the MOS transistor, due to mu and V T 、V TH All will change with temperature and V GS Also with temperature, the subthreshold current is:
wherein T is r Absolute room temperature, k 1 、k 2 Mu and respectivelyV TH Is used for the temperature coefficient of (a),
at T r The threshold voltage at temperature is V obtained by the formula (2) GS Inversely related to temperature, to compensate for the temperature coefficient of the threshold voltage, let V be GS The expression is:
to make dI D dT at temperature T r When equal to 0, can be obtained:
as can be seen from the formula (4),
the initial value is->
Influence (S)>
Will vary with the process angle, so that a process angle compensation bias circuit is needed to generate different +.>
The method comprises the steps of carrying out a first treatment on the surface of the Under different process angles, the range of the threshold voltage of the MOS tube of different types along with the change of the process angle is different, and the process sensitivity of the threshold voltage of the MOS tube of small size is larger.
Generating pA-level ultra-low power consumption current by adopting a method based on a gate compensation MOS tube threshold voltage temperature coefficient; the threshold voltage of the MOS transistor of the current reference output stage is compensated by the process angle compensation bias circuit and the negative temperature coefficient bias generating circuit, so that zero temperature coefficient current is generated.
As shown in FIG. 2, the process corner compensation bias circuit comprises an N-type field effect transistor M1, an N-type field effect transistor M2 and an N-type field effect transistor M3, wherein the drain electrode of the N-type field effect transistor M1 is connected with a power supply VDD, the grid electrode is connected with the source electrode thereof, and the source electrode outputs a bias voltage V REFB The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the N-type field effect transistor M2 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M3, and the source electrode is connected with the drain electrode of the N-type field effect transistor M3; the gate of the N-type field effect transistor M3 is connected with the drain thereof, and the source thereof is connected with the ground GND.
The threshold voltage of the high threshold MOS transistor has a larger variation range under the SS-FF process angle, so that the N-type field effect transistor M2 and the N-type field effect transistor M3 select the high threshold transistor with the threshold voltage range of 750-950 mV; the low threshold transistor has smaller variation of threshold voltage at different process angles than the standard threshold transistor in the voltage reference, so that the N-type field effect transistor M1 adopts a low threshold transistor with threshold voltage lower than 200mV, and the V is finely adjusted by adjusting the sizes of the N-type field effect transistor M1, the N-type field effect transistor M2 and the N-type field effect transistor M3 REFB Is a process angle deviation of (2).
As shown in fig. 2, the negative temperature coefficient bias generating circuit includes an N-type field effect transistor M4, an N-type field effect transistor M5 and an N-type field effect transistor M6, wherein the drain electrode of the N-type field effect transistor M4 is connected with the source electrode of the N-type field effect transistor M1, the gate electrode is connected with the drain electrode thereof, and the source electrode is connected with the drain electrode of the N-type field effect transistor M5; the drain electrode of the N-type field effect transistor M5 is connected to the grid electrode of the N-type field effect transistor M6, and the source electrode of the N-type field effect transistor M5 is connected to the drain electrode of the N-type field effect transistor M6; the drain of the N-type field effect transistor M6 is connected to the gate and the source is connected to ground GND.
The N-type field effect transistor M4, the N-type field effect transistor M5 and the N-type field effect transistor M6 are all high threshold transistors with the threshold voltage range of 750-950 mV, the width-to-length ratio of the N-type field effect transistor M5 to the N-type field effect transistor M6 is set to be the same, and the N-type field effect transistor M4 and the N-type field effect transistor M5 and the N-type field effect transistor M6 are adjusted in size so that the N-type field effect transistor M4 has a negative temperature coefficient.
As shown in fig. 2, the current reference output stage circuit includes a P-type field effect transistor M7 and an N-type field effect transistor M8, wherein the source of the P-type field effect transistor M7 is connected to the power supply VDD, and the gate is connected to the drain thereof; the source of the N-type field effect transistor M8 is connected to the drain of the P-type field effect transistor M7, the gate is connected to the drain of the N-type field effect transistor M5, and the source is grounded GND.
The P-type field effect transistor M7 and the N-type field effect transistor M8 are respectively standard threshold transistors with the threshold voltage range of 360-460 mV, the grid voltage VG of the N-type field effect transistor M8 connected with the source electrode of the N-type field effect transistor M4 has a negative temperature coefficient to offset the temperature coefficient of the threshold voltage of the N-type field effect transistor M8, the current with zero temperature coefficient can be obtained, and finally the obtained reference current can be copied and output through the grid electrode of the P-type field effect transistor M7.
As shown in fig. 2 and 3, the present embodiment adds a process corner compensation bias circuit to compensate for the variation of the SS-FF threshold voltage process corner, wherein the process corner compensation bias circuit comprises an N-type field effect transistor M1, an N-type field effect transistor M2 and an N-type field effect transistor M3; the drain electrode of the N-type field effect transistor M1 is connected with the power supply VDD, the grid electrode is connected with the source electrode of the N-type field effect transistor M1, and the source electrode outputs bias voltage V REFB The method comprises the steps of carrying out a first treatment on the surface of the The drain electrode of the N-type field effect transistor M2 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M3, and the source electrode is connected with the drain electrode of the N-type field effect transistor M3; the gate of the N-type field effect transistor M3 is connected with the drain thereof, and the source thereof is connected with the ground GND.
Under different process angles, the change rate of the threshold voltage is reduced along with the increase of the length or the width of the MOS transistor, so that the process sensitivity of the threshold voltage of the small-size MOS transistor is larger, and therefore, when the N-type field effect transistor M1 and the N-type field effect transistor M2 are selected, V is needed TH2 With process angle change faster, V TH1 The process angle variation with the threshold voltage of the N-type field effect transistor M8 is compensated for by the slower process angle variation.
As shown in FIG. 4, the V generated by the process angle compensation bias circuit is in the range of 0-100 ℃ under different process angles REFB As shown in FIG. 5, the reference current I is outputted within the temperature range of 0 ℃ to 100 DEG C REF In fig. 4 and 5, SF, SS, TT, FS and FF represent different process corners, respectively, where SF represents slow NFET and fast PFET, SS represents slow NFET and slow PFET, TT represents a typical NFET typical PFET, FS represents fast NFET and slow PFET, and FF represents fast NFET and fast PFET; it can be seen in FIG. 4 that V at the FF to TT process corner REFB Phase difference of 105mV to provide process angle compensation; it can be seen in FIG. 5 that at the TT process corner, I REF About 100pA, and a temperature coefficient of 412 ppm/DEG C.
At normal temperature, within all process angle ranges, I REF After the process angle is compensated, the current reference in the embodiment can generate reference current with smaller phase difference under all process angles without trimming circuits, and the current reference designed in the embodiment is only 651pA under the process angles of 1V, 25 ℃ and TT of power supply voltage, thus being suitable for the application scene of ultra-low power in radio frequency energy collection.
Therefore, the problems of large deviation and large power consumption of the output current of the traditional current reference circuit along with different process angles are effectively solved, the structure is simple, the pA-level reference current is realized only by a few MOS transistors with different thresholds, the occupied chip area is small, and the layout is facilitated.
In addition to the embodiments described above, other embodiments of the invention are possible. All technical schemes formed by equivalent substitution or equivalent transformation fall within the protection scope of the invention.
Claims (6)
1. An ultra-low power consumption reference current source circuit applied to a power management unit is characterized in that: comprising
Process corner compensation bias circuit for generating bias voltage V REFB To compensate the variation of threshold voltage at different process angles, the subthreshold current formula is:
wherein μ representsCarrier mobility, C ox Represents a gate oxide layer per unit area, m represents a subthreshold slope factor, V T =kt/q represents thermal voltage, is proportional to temperature, k represents boltzmann constant, T represents thermodynamic temperature, and q represents charge amount of electrons; W/L represents the width-to-length ratio of MOS tube, V GS Representing MOS gate-source voltage, V TH Represents the threshold voltage of the MOS transistor, due to mu and V T、 V TH All will change with temperature and V GS Also with temperature, the subthreshold current is:
wherein T is r Absolute room temperature, k 1 、k 2 Mu and V respectively TH Is used for the temperature coefficient of (a),
at T r The threshold voltage at temperature is V obtained by the formula (2) GS Inversely related to temperature, to compensate for the temperature coefficient of the threshold voltage, let V be GS The expression is:
wherein k is 3 Represents V GS To be dI D dT at temperature T r When equal to 0, can be obtained:
as can be seen from the formula (4),
the initial value is->
Influence (S)>
Can be changed along with the change of the process angle, and different +.>
；
A negative temperature coefficient bias generating circuit for generating a voltage inversely related to an absolute temperature,
a current reference output stage circuit for outputting a reference current I independent of temperature and input voltage REF ；
The process angle compensation bias circuit comprises an N-type field effect transistor M1, an N-type field effect transistor M2 and an N-type field effect transistor M3, and the bias voltage V is adjusted by adjusting the sizes of the N-type field effect transistor M1, the N-type field effect transistor M2 and the N-type field effect transistor M3 REFB Is a process angle deviation of (2);
the drain electrode of the N-type field effect transistor M1 is connected with the power supply VDD, the grid electrode is connected with the source electrode of the N-type field effect transistor M1, and the source electrode outputs bias voltage V REFB ；
The drain electrode of the N-type field effect transistor M2 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M3, and the source electrode is connected with the drain electrode of the N-type field effect transistor M3;
the grid electrode of the N-type field effect transistor M3 is connected with the drain electrode of the N-type field effect transistor M, and the source electrode of the N-type field effect transistor M is connected with the ground GND;
the negative temperature coefficient bias generating circuit comprises an N-type field effect transistor M4, an N-type field effect transistor M5 and an N-type field effect transistor M6, and the sizes of the N-type field effect transistor M4, the N-type field effect transistor M5 and the N-type field effect transistor M6 are adjusted so that the N-type field effect transistor M4 has a negative temperature coefficient;
the drain electrode of the N-type field effect transistor M4 is connected with the source electrode of the N-type field effect transistor M1, the grid electrode is connected with the drain electrode of the N-type field effect transistor M5, and the source electrode is connected with the drain electrode of the N-type field effect transistor M5;
the drain electrode of the N-type field effect transistor M5 is connected to the grid electrode of the N-type field effect transistor M6, and the source electrode of the N-type field effect transistor M5 is connected to the drain electrode of the N-type field effect transistor M6;
the drain of the N-type field effect transistor M6 is connected to the gate and the source is connected to ground GND.
2. An ultra-low power consumption reference current source circuit for a power management unit according to claim 1, wherein: the N-type field effect transistor M1 is set to be a low-threshold NMOS transistor, the threshold voltage of the low-threshold NMOS transistor is set to be lower than 200mV, the N-type field effect transistor M2 and the N-type field effect transistor M3 are both set to be high-threshold NMOS transistors, and the threshold voltage of the high-threshold NMOS transistor is set to be 750-950 mV.
3. An ultra-low power consumption reference current source circuit for a power management unit according to claim 1, wherein: the N-type field effect transistor M4, the N-type field effect transistor M5 and the N-type field effect transistor M6 are all set to be high-threshold NMOS transistors, and the threshold voltage of the high-threshold NMOS transistors is set to be 750-950 mV.
4. An ultra-low power consumption reference current source circuit for a power management unit according to claim 3, wherein: the aspect ratio of the N-type field effect transistor M5 and the N-type field effect transistor M6 are set to be the same.
5. An ultra-low power consumption reference current source circuit for a power management unit according to claim 1, wherein: the current reference output stage circuit comprises a P-type field effect transistor M7 and an N-type field effect transistor M8, wherein the grid voltage VG of the N-type field effect transistor M8 has a negative temperature coefficient and is used for counteracting the temperature coefficient of the threshold voltage of the N-type field effect transistor M8, so that a current with a zero temperature coefficient is obtained, and finally the obtained reference current is copied and output through the grid electrode of the P-type field effect transistor M7;
the source electrode of the P-type field effect transistor M7 is connected with a power supply VDD, and the grid electrode is connected with the drain electrode of the P-type field effect transistor M7;
the source of the N-type field effect transistor M8 is connected to the drain of the P-type field effect transistor M7, the gate is connected to the drain of the N-type field effect transistor M5, and the source is grounded GND.
6. An ultra-low power consumption reference current source circuit for a power management unit according to claim 5, wherein: the P-type field effect transistor M7 is set as a standard threshold PMOS tube, the N-type field effect transistor M8 is set as a standard threshold NMOS tube, and the threshold voltages of the standard threshold PMOS tube and the standard threshold NMOS tube are set to 360-460V.
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| JPH02149014A (en) * | 1988-11-30 | 1990-06-07 | Nec Corp | Temperature compensated level shift circuit |
| WO2018032308A1 (en) * | 2016-08-16 | 2018-02-22 | 深圳市汇顶科技股份有限公司 | Linear regulator |
| CN110377095A (en) * | 2019-07-22 | 2019-10-25 | 天津理工大学 | A kind of subthreshold value reference voltage generating circuit of super low-power consumption low-voltage Low Drift Temperature |
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| CN104579172B (en) * | 2014-11-28 | 2017-06-06 | 上海华虹宏力半导体制造有限公司 | Resistance circuit with tc compensation |
| CN109240407B (en) * | 2018-09-29 | 2020-07-31 | 北京兆易创新科技股份有限公司 | Reference source |
| CN115328262A (en) * | 2022-09-01 | 2022-11-11 | 中国科学技术大学 | Low-voltage low-power-consumption CMOS reference voltage source with process compensation and debugging method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02149014A (en) * | 1988-11-30 | 1990-06-07 | Nec Corp | Temperature compensated level shift circuit |
| WO2018032308A1 (en) * | 2016-08-16 | 2018-02-22 | 深圳市汇顶科技股份有限公司 | Linear regulator |
| CN110377095A (en) * | 2019-07-22 | 2019-10-25 | 天津理工大学 | A kind of subthreshold value reference voltage generating circuit of super low-power consumption low-voltage Low Drift Temperature |
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