JPH02149014A - Temperature compensated level shift circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit to operate stably even in the environment of high temperature by providing plural level shift circuits, and providing a bias circuit with the diodes of the same characteristics as the parasitic diodes of the constant current source EMESFETs (normally-off type Schottky junction FETs) of each level shift circuit. CONSTITUTION:To the source electrode of the EMESFET 101 whose drain electrode and gate electrode are connected respectively to ground potential and an input terminal VIN, the anode electrode of the diode 106 is connected. To the cathode electrode of the diode 106, the drain electrode of the EMESFET 102 is connected, and a gate electrode is connected to a contact 120, and the source electrode is connected to a negative power source VSS through a resistor element 109, and a first level shift circuit is constituted. Besides, the EMESFET 103 to whose source electrode the anode electrode of the diode 107 is connected and the EMESFET 104 whose drain electrode and source electrode are connected respectively to the cathode electrode of the diode 107 and the negative power source VSS constitute a second level shift circuit.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a temperature compensated level shift circuit.

More specifically, the present invention relates to a temperature-compensated level shift circuit that is constructed of a Schottky junction field effect transistor and a Schottky junction diode, particularly for a differential amplifier circuit, and that can operate stably even in a high temperature environment.

2. Related Art A conventional level shift circuit and its operation will be described with reference to FIGS. 5(a) to 5(C), FIGS. 6 and 7.

Examples of conventional level shift circuits are shown in FIGS. 5(a) to 5(C). FIGS. 5(a) to 5(C) each show a circuit diagram of a level shift circuit. Conventional level shift circuits will be explained below, focusing on the level shift circuit shown in the circuit diagram of FIG. 5(a).

The level shift circuit shown in the circuit diagram of FIG. 5(a) consists of a normally-on Schottky junction field effect transistor (hereinafter abbreviated as DMESFET) 501 whose drain electrode is connected to a ground potential and whose gate electrode is an input terminal. Schottky junction diodes (hereinafter abbreviated as diodes) 503 each having an anode electrode connected to a source electrode;
A DMESFET 502 whose drain electrode is connected to the cathode electrode of the diode 503, and whose gate electrode and source electrode are connected to the negative power supply vsl;
Output terminal 506 connected to Er2O3 drain electrode
It mainly consists of.

Hereinafter, with reference to both FIGS. 6 and 7, FIG.
The operation of the level shift circuit a) will be explained.

FIG. 6 shows the temperature characteristics of the current-voltage characteristics of the diode 503 at junction temperatures (hereinafter abbreviated as T) of 25°C and 1.
The case of 00°C is shown. In addition, Fig. 5 (a) is shown in Fig. 7.
) to FIG. 5(C) show the input/output DC transfer characteristics of each level shift circuit.

In the level shift circuit of FIG. 5(a), DMES
The FET502 normally has an open channel and operates in a saturation region, so it exhibits constant current property. diode 503
7. = 25° C., it exhibits the characteristics of curve 601 in FIG. 6, and generates a forward voltage VfOM according to the constant current value of DME S F Er2O3. For example, if the above constant current value is 50 μA, v toN is approximately 0.7V. D
ME S F Er2O3 forms a source follower,
DME SF Er2O3 is turned on for a constant current value, and vcsaM(a) is present between the gate and source electrodes.
A voltage is generated. The DMESFET 501 has a gate electrode potential that is at a threshold voltage Vto(
<OV), saturation region operation is performed. Therefore, for example, the gate widths of the DME S F Er2O3, 502 are equal, and the potential VX8 of the input terminal 504 is VrM<V? D
In this case, VcsoN(a)=OV, and a level shift of vro (a) is achieved with respect to the potential V□ of the input terminal 504. As a result, the potential Vo of the output terminal 506
υT(a) follows the change in V I )I, and shows the input/output DC transfer characteristic shown by curve 705 in FIG.

The level shift circuit shown in Fig. 5, etc.) is as shown in Fig. 5(a).
The DMESF Er2O3 of the Leher shift circuit is replaced with a normally-off Schottky junction field effect transistor (hereinafter abbreviated as EMESFET) 507. Furthermore, the level shift circuit shown in FIG. 5(C) is similar to the DMESFE of the level shift circuit in FIG. 5(a).
T501 and 502 are each EMESFET513
and 514, and the EME
The potential difference between the gate and source electrodes V b i a is generated by the Mehias power supply 519 to open the channel of the S FET 514.
s is applied.

The level shift circuit shown in Fig. 5 et al.) and (C) is as follows:
Both operate in the same manner as the level shift circuit shown in FIG. 5(a) above. That is, both the DME SF Er2O3 and the EME SF ET514 normally have open channels and operate in the saturation region, so they exhibit constant current properties. Diodes 509 and 515 are diode 5
Similar to 03, when TJ = 25°C, it shows the characteristics of curve 601 in Fig. 6, and DME SF Er2O3 and EME
Forward voltage VfON according to the constant current value of SFET514
occurs. EME S F Er2O3 and 513
form the source followers, and each DMESFE T
508 and EMESFET 514 with constant current values, and there is V a s between each gate and source electrode.
The voltages ox (b) and V c s o s (C) are generated. EMESFETs 507 and 513 have their gate electrodes at a threshold voltage V with respect to the ground potential.
If rE (>Qv) or less, saturation region operation is performed, and Vcsow (b
) and Vas O)l (C), and with respect to the potentials of input terminals 510 and 516, Vas
ox(b)+VraN(b) and VcsoN(C)+
A level shift operation called VroN(C) is performed. As a result, the level shift circuits shown in FIGS. 5(5) and 5(C) exhibit input/output DC transfer characteristics shown by curves 708 and 7090 in FIG. 7. In the level shift circuit of FIG. 5(C), when the gate widths of EMESFETs 513 and 514 are equal, the bias voltage V b i a a and VaS.

, (C) are equal.

In each of the above level shift circuits, DMESFET
501, the gate electrode potential of EMESFET507.513 is Vo>v, or v, >v with respect to the ground potential.
TI: When it comes to the potential relationship, DME SFET,
The EMESFET performs non-saturation region operation. Therefore VI
With respect to N, the source electrode potential does not follow, and the level shift is not performed sufficiently, and as shown in Fig. 7, the VIN of Voυ
The so-called DC gain decreases.

Problems to be Solved by the Invention In general, a circuit in which the above-mentioned level shift circuit and differential amplifier circuit are connected is widely used as an input circuit of a memory circuit, a sense amplifier, and the like.

In this case, the level shift circuit is required to operate the differential amplifier circuit driving transistor in a saturation region operating state. However, when the above conventional level shift circuit is used, it has the following drawbacks for a small amplitude input signal in which the ground potential is set to H level.

(1) When using the level shift circuit shown in Fig. 5(a), the DMESFET 501 operates in the non-saturation region with respect to the human input signal level, so no human output gain is obtained, the input amplitude is attenuated, and the differential Decreases the operating margin of the circuit. For example, as shown in Figure 7, CML human power level (H=Ov
, L=0.5 v), the human output gain is 0.65.
It becomes a degree.

(2) When using the level shift circuit shown in Fig. 5 et al., EME S F Er2O3 and DME S F E
Since r2O3 is manufactured in a different process, imbalance in device characteristics is likely to occur. Especially EME S F Er2O3
When the capacity of DME S FET50g becomes lower than that of DME S FET50g,
This is the on-voltage of the diode 521 parasitic to S F Er2O3. Therefore, the gate electrode responds to the input signal by
This may result in low impedance and cause input signal amplitude deterioration.

(3) When the level shift circuit shown in FIG. 5(C) is used, V reflecting the bias voltage V b tas. ,. N (C) is generated between the gate and source electrodes of the EME SFET 513, and the parasitic diode 522 is turned off, for example, V, ) Sol (C) = 0.5 V
It is possible to set it to .

However, as Tj increases to 100° C., the characteristics of diode 515 change as shown by curve 602 in FIG. Therefore, VGS. Even at o(C)=0.5 V, the parasitic diode is turned on, so the gate electrode becomes low impedance. In order not to reduce human power impedance even in high temperature environments, EMESFE
There is a method of making the gate width of T513 sufficiently large, but this increases the element size.

Therefore, an object of the present invention is to provide a level shift circuit which solves the problems of the prior art and whose input impedance does not decrease even in a high temperature environment.

Means for Solving the Problems According to the present invention, the drain electrode is connected to ground potential,
A normally-on Schottky junction field effect transistor whose gate electrode and source electrode are short-circuited to serve as a bias terminal, and a Schottky junction diode whose anode electrode is connected to the bias terminal and whose cathode electrode is connected to a negative power supply. a first normally-off Schottky junction field effect transistor whose drain electrode is connected to the ground potential and whose gate electrode is an input terminal, and whose anode electrode is connected to the first
a Schottky junction diode connected to a source electrode of a normally-off Schottky junction field effect transistor, a gate electrode connected to the bias terminal of the bias generation circuit, and a drain electrode connected to the cathode electrode of the Schottky junction diode. a second normally-off Schottky junction field effect transistor serving as an output terminal, a source electrode of the second normally-off Schottky junction field effect transistor, and the negative power supply. A temperature-compensated level shift circuit, comprising a plurality of level shift circuits each including a resistive element, and a voltage between the gate and source electrodes of each of the normally-off Schottky junction field effect transistors is temperature-compensated. is provided.

It is preferable that the temperature compensated level shift circuit of the present invention includes two sets of the level shift circuits, and each output terminal is connected to a pair of input terminals of a differential amplifier circuit. Further, it is preferable that the normally-off Schottky junction field effect transistor and the Schottky junction diode are manufactured by the same manufacturing process.

Operation The temperature compensated level shift circuit of the present invention includes a plurality of level shift circuits, and a constant current source EM of each level shift circuit.
The bias generation circuit includes a diode having the same characteristics as the parasitic diode of the ESFET. Since this diode controls the gate electrode bias of the level shift circuit constant current source EMESFET, it operates stably even in a high temperature environment.

EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to examples, but the following disclosure is merely an example of the present invention, and does not similarly limit the technical scope of the present invention.

Embodiment 1 A temperature compensated level shift circuit according to the present invention will be explained with reference to FIG.

FIG. 1 shows a circuit diagram of a circuit in which an example of the temperature compensation level shift circuit of the present invention and a differential amplifier circuit are connected. The circuit of the present invention shown in FIG. 1 is constructed of a first and second level shift circuit and a bias generation circuit, each of which inputs manually input signals from the input terminals VHI and m of the corrective and corrective dual-phase inputs. A temperature compensated level shift circuit and a differential amplifier circuit are connected through contacts 117 and 118, respectively.

In the circuit shown in FIG. 1, the DMESFET 115 whose drain electrode is connected to the ground potential is used as a constant current element with its gate and source electrodes short-circuited. DME
A diode 10 is connected to the source electrode of the SFET 115.
The anode electrode of the diode 8 is connected to a contact 120 serving as a bias terminal, and the cathode electrode of the diode 108 is connected to a negative power supply VSS. With the above configuration, DME S
The FET 115 # and the diode 108 form a bias generation circuit with the contact 120 as a bias terminal.

EME S F ETIO whose drain electrode is connected to ground potential and whose gate electrode is connected to input terminal VIN
The anode electrode of the diode 106 is connected to the source electrode of I. The drain electrode of EMESFET 102 is connected to the cathode electrode of diode 106,
The gate electrode of the EMESFET 102 is connected to the contact 120, and the source electrode is connected to the negative power supply v through the resistive element 109.
ss to constitute a first level shift circuit. Further, similarly to the first level shift circuit, the drain electrode is connected to the ground potential, the gate electrode is connected to the input terminal ■π, and the source electrode is connected to the diode 10.
EMESFET10 with 7 anode electrodes connected
3, the drain electrode is connected to the cathode electrode of the diode 107, the gate electrode is connected to the contact 120,
Further, the source electrode is connected to the negative power supply V through the resistive element 110.
EMESFET 104 connected to SS constitutes a second level shift circuit.

The first and second level shift circuits are connected to a pair of input terminals of the differential circuit at contacts 117 and 119, respectively.

The operation of the above temperature compensated level shift circuit will be described below with reference to FIGS. 2 and 3.

FIG. 2 is a diagram showing the human output transfer characteristics of the temperature compensation level shift circuit of this embodiment, and FIG. 3 is a diagram showing the level relationship at each contact point in FIG. 1. In FIG. 2, straight lines 201 and 201' represent Tj =25°C and 'r, =100, respectively, of the above level shift circuit.
The source electrode potential of EME SF ETIOI at ℃ is shown. Further, straight lines 202 and 202' indicate the output potentials of the first level shift circuit when TJ=25° C. and T,+=lOO° C., respectively. In FIG. 3, curves 301 and 301' are respectively T'=2
EMESFETI at 5℃ and TJ = 100℃
Indicates the source electrode potential of OI, and the curvilinear and πr′ are
The source electrode potentials of EMESFET 103 are shown when TJ = 25°C and TJ = 100°C, respectively. Furthermore, curves 302 and 302' are each TJ = 2
The output potential of the first level shift circuit is shown at 5° C. and Tj=100° C., and the curves πT and ? ' teeth,
The output potentials of the second level shift circuit are shown when T = 25°C and TJ = 100°C, respectively. Also, straight lines 303 and 303' are TJ = 25
EME S F Er when °C and T, = 100 °C
The gate electrode potential of 2O3 is shown, and the straight lines 304 and 30
4' is T respectively.

EME S when = 25℃ and TJ = 100℃
F indicates the source electrode potential of Er2O3.

The DME SFET115 is gated as described above.
It is a constant current element whose source electrode is short-circuited, and the contact 1
A constant current is supplied to the diode 108 regardless of the potential of the diode 20. In this state, the diode 108 shows curve 6 in FIG.
01, the forward rising voltage V, at TJ = 25°C. , occurs.

In the EMESFET 102, the gate electrode is biased to V foe with respect to the potential of the negative power supply VSS, so the EMESF Er2O3 operates in the saturation region and exhibits constant current property. The resistance value of the resistance element 109 is such that when this constant current flows through the resistance element 109, the potential difference Vcsos+02 between the gate and source electrodes does not reach the on-voltage of the parasitic diode 1240.
The potential of 21 is selected to be higher than Vss. On the other hand, the potential difference between the gate and source electrodes of EME SF ETIOI is VGSO. 1 is the conventional example shown in FIG. 5 (C
), a voltage reflecting VO50N+02 is generated. For example EMESFETlol
and 102 have the same gate width, ■. ,
. □. 2" vas.8..1, and therefore, the parasitic diode 123 is in the off state like the parasitic diode 124. EME S F Er2O3 performs constant current operation even if the resistive element 109 is present, so the input With respect to the potential V IH, the potential v117 of the contact 117, which is the output potential of the first level shift circuit, is expressed by the straight line 202 in FIG.
As shown in V117 = V1)I VGliO)1+01
Becomes Vrox.

When T increases to 100° C., the rising voltage in the forward direction of the diode 108 decreases as shown by curve 602 in FIG. It becomes 'I'. At this time, EM
The gate electrode potential of E S F Er2O3 is also V fON
to v ray'. Therefore, E M ESF
The potential difference between the gate and source electrodes of ET102 is also VGSO1
02', and the parasitic diode 124 becomes the resistance element 10.
It is turned off by the voltage generation mechanism 9.

Therefore, the parasitic diode 123 of EME SF ETIOI is also biased to Vasow+o+' and turned off.

At this time, the potential V117' of the contact 117, which is the output potential of the first level shift circuit with respect to the input potential VIN, is the second level shift circuit.
As shown in Figure 202', V+tt' = VIll Vesox+o+
It becomes Vros.

Therefore, in the level shift circuit described above, even if T increases, the potential difference between the gate and source electrodes of the EMESFETIO I 102 is temperature compensated by the temperature characteristics of the diode 108.

In the second level shift circuit, a signal vπ having the opposite phase to the input of the first level shift circuit is input to the gate electrode of EMESFET 103, and the EME SF Er2O3 gate electrode is connected to the EMESFET 102 of the first level shift circuit.
It is connected to a contact point 120 in common with the gate electrode of. Therefore, the second level shift circuit also follows the curve πr1 in FIG.
As shown in πr13...1 and Santo-, they operate in the same manner as the first level shift circuit described above.

In the temperature compensated level shift circuit of this embodiment, the temperature compensation level shift circuit shown in FIG.
) The input leakage current of the conventional level shift circuit shown in ) was approximately 70 μA at TJ = 100°C.
It became possible to reduce it to 1/7.

Therefore, the first and second level shift circuits described above are
Level shift voltages are generated at contacts 117 and 119 in response to the positive and negative phase inputs 1 and ffi. Junction temperature T
The level shift voltage decreases due to the increase in ``, but the differential amplifier circuit has a gain of almost 0 for the common-mode input component.''
Therefore, it operates stably.

Embodiment 2 FIG. 4 shows a circuit diagram of another embodiment of the temperature compensated level shift circuit of the present invention. The temperature compensated level shift circuit of the present invention shown in FIG. It is composed of a level shift circuit.

That is, a DME whose drain electrode is connected to ground potential
S F Er2O3 has its gate and source electrodes short-circuited and is used as a constant current element. DMESFET
The anode electrode of the diode 402 is connected to the source electrode of the diode 401 through a contact 404, and the cathode electrode of the diode 4020 is connected to the negative power supply vis. Further, a resistive element 403 is connected to the contact 404, and the above DM
Together with the E S F Er2O3 and the diode 402, it constitutes a bias generation circuit using the contact 405 as a bias terminal.

Further, the drain electrodes are connected to the ground potential, and the gate electrodes are connected to the input terminals V□Ml, Vl-2 and V! ■
EME SF ET411.413 connected to
A diode 4 is connected to the source electrode of 415 and 415, respectively.
The anode electrodes 17, 418 and 419 are connected. The drain electrodes of EMESFET412.414 and 416 are connected to the cathode electrodes of diodes 417.41B and 419,
The gate electrodes of T412.414 and 416 are connected to the bias terminal 405, respectively, and the source electrodes are connected to the negative power supply Vll through resistive elements 420.421 and 422, respectively, to connect the first, second and third levels. It constitutes a shift circuit.

The operation of each level shift circuit is similar to that of the level shift circuit of the first embodiment described above. In the temperature compensated level shift circuit of this embodiment, since the first, second and third level shift circuits are connected to the bias terminal 405, the parasitic diode leakage of each of the constant current EME SFETs 412, 414 and 416 is reduced. A superimposed current flows through the resistance element 403. Therefore, the potential of the bias terminal 405 becomes lower than that of the contact 404, and the constant current EME S F
ET412.414 and 416 respective gates -
The potential difference between the source electrodes is further reduced compared to the case where the resistance element 403 is not used. Therefore, input terminal V11I
The input leakage current flowing into each of I, VIN□ and VIN3 is also lower than when the resistor element 403 is not used.
Further decrease. Furthermore, even if the junction temperature T rises, the diode 40
Due to the temperature characteristics of 2, EME SF ET412.4
The potential difference between the gate and source electrodes 14 and 416 is temperature compensated.

As described in the detailed description of the invention, the temperature compensated level shift of the present invention comprises:
Even when the junction temperature becomes high, it is possible to prevent the input impedance of the level shift circuit from decreasing, and the level shift is performed without attenuating the amplitude of a small signal near the ground potential.

This is because the temperature compensated level shift circuit of the present invention biases the gate voltage of the constant current source EMESFET of the level shift circuit with the conventional EMESFET configuration by the forward voltage of the diode, and connects the source electrode of the constant current source EMESFET with the negative power source. This is because the structure includes a resistance between the two.

Therefore, the present invention provides a level shift circuit for inputting a differential amplifier circuit, which has a small input leakage current and little amplitude deterioration, so that malfunction of the differential amplifier circuit can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of a circuit in which a temperature compensated level shift circuit and a differential amplifier circuit of the present invention are connected, and FIG. 2 is an input/output DC transmission of the temperature compensated level shift circuit of FIG. FIG. 3 is a level relationship diagram of the temperature compensation level shift circuit of FIG. 1; FIG. 4 is a circuit diagram of another embodiment of the temperature compensation level shift circuit of the present invention; Figures 5(a) to (C) are circuit diagrams of conventional level shift circuits, respectively, and Figure 6 shows the voltage-current characteristics and temperature dependence of a Schottky junction diode used in the level shift circuit. FIG. 7 is an input/output DC transfer characteristic of a conventional level shift circuit. [Main reference number] 101.102.103 411.412 50? , 513 113.115.401. 104.111.112. 413.414.415.4161 . 514 ・ ・ ・EMESFET. , 501.502.508 ・ ・ ・DMESFET. 106.107.108. 402. 417.418. 419. 503. 5
09. 515 ・ ・ ・Diode, 109.1
10, R1, R2, 403, 420, 421, 422...resistance element, 12
3.124.520.521.522...parasitic diode,

Claims (3)

[Claims] (1) A normally-on Schottky junction field effect transistor in which the drain electrode is connected to the ground potential, the gate electrode and the source electrode are short-circuited, and serve as a bias terminal; the anode electrode is connected to the bias terminal, and the cathode electrode a bias generating circuit comprising a Schottky junction diode connected to a negative power supply; and a first normally-off Schottky junction field effect circuit having a drain electrode connected to the ground potential and a gate electrode serving as an input terminal. a Schottky junction diode whose anode electrode is connected to the source electrode of the first normally-off Schottky junction field effect transistor;
a second normally-off Schottky junction field effect transistor whose gate electrode is connected to the bias terminal of the bias generation circuit and whose drain electrode is an output terminal connected to the cathode electrode of the Schottky junction diode; a plurality of level shift circuits each configured with a resistive element connected between the source electrode of the second normally-off Schottky junction field effect transistor and the negative power supply; 1. A temperature compensated level shift circuit characterized in that the voltage between the gate and source electrodes of a Schottky junction field effect transistor is temperature compensated. (2) The temperature compensated level shift according to claim (1), characterized in that two sets of the level shift circuits are provided, and each output terminal is connected to a pair of input terminals of a differential amplifier circuit. circuit. (3) The temperature compensated level shift circuit according to claim (1) or (2), wherein the normally-off Schottky junction field effect transistor and the Schottky junction diode are manufactured by the same manufacturing process. .