CN108345341B - Linear voltage regulator with self-adaptive enhanced power supply suppression - Google Patents

Linear voltage regulator with self-adaptive enhanced power supply suppression Download PDF

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CN108345341B
CN108345341B CN201711442181.3A CN201711442181A CN108345341B CN 108345341 B CN108345341 B CN 108345341B CN 201711442181 A CN201711442181 A CN 201711442181A CN 108345341 B CN108345341 B CN 108345341B
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common
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operational amplifier
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CN108345341A (en
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王永寿
何德军
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3Peak Inc
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3Peak Inc
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor

Abstract

The invention discloses a linear voltage regulator with self-adaptive enhanced power supply rejection, which is composed of a reference voltageThe module, the self-adaptive enhanced EA module, the PMOS power tube, the two voltage division feedback resistors and the load impedance, wherein the input end of the linear voltage stabilizer is respectively connected to the reference voltage module and the source electrode of the power tube MP, and the output end of the reference voltage module and the N of the self-adaptive enhanced EA modulePThe ends are connected, the voltage division feedback resistor is connected in series and is connected in parallel with the load impedance, one end point of the parallel connection is grounded, the other end point of the parallel connection is connected with the drain electrode of the power tube MP to be used as the output end of the linear voltage stabilizer, and the voltage division node is connected with the N of the self-adaptive enhanced EA moduleFThe ends are connected, and the output end of the self-adaptive enhanced EA module is connected with the grid electrode of the power tube MP. The self-adaptive PSRR characteristic enhancement technology provided by the invention enables the main pole of the loop to adaptively follow the change of the output pole according to the load condition of the LDO, and simultaneously utilizes the dynamic zero tracking technology to keep the loop stable and keep higher PSR characteristic in a wider frequency range.

Description

Linear voltage regulator with self-adaptive enhanced power supply suppression
Technical Field
The invention relates to a voltage conversion module designed for a high-precision system, in particular to a self-adaptive PSR (power system response) enhanced low dropout regulator.
Background
In the design of a high-precision system, the power supply is required to have high initial precision and high precision, and the voltage is required to have a strong inhibiting effect on medium-high frequency noise on the power supply. Especially in the fields of video monitoring, communication systems and the like, the requirements on the power supply voltage are more strict. The LDO module is a commonly used voltage conversion module, and has very general application in high-precision systems. Therefore, it is very meaningful to realize a high PSR LDO design. An LDO design with adaptive PSR enhancement techniques is presented herein that can meet this requirement well. The LDO architecture is shown in fig. 1, and is composed of a reference voltage generation module VREF, an error amplifier EA, a power tube MP, and voltage dividing resistors RF1 and RF 2; in order to improve the PSR characteristics of the LDO, the optimal design of the PSR characteristics of the VREF and the EA module needs to be considered.
Now, researchers have proposed some new architecture schemes for improving the PSRR characteristics by improving the low frequency gain, which is briefly described as follows.
The architecture circuit shown in fig. 2 is mainly a means for increasing the low frequency gain to improve the PSRR characteristic of the whole system. Namely, a high-gain bandgap and an error amplifier are required to be designed to improve the PSRR of the LDO. Therefore, the system has better PSRR characteristics at low frequency, almost has no inhibition capability at a middle frequency band, and improves the PSRR completely by virtue of off-chip capacitance. Please see in detail: yan Asia east, Yan Roc, "a low noise and high power supply rejection ratio CMOS low dropout linear regulator," Vol.33, N.6, Dec.2013.
The structure of the architecture circuit shown in fig. 3 can effectively improve the PSRR characteristic of the LDO system, and a feed-forward amplifier is required to amplify noise in a certain frequency band of the signal source noise, and then the sum amplifier is used to perform subtraction operation on the power supply noise of the main path and the feed-forward path through a certain proportion adjustment, so as to improve the PSRR characteristic of the LDO output voltage. Therefore, the structure is not only complex in circuit, but also high in cost and power consumption due to the fact that two operational amplifiers are additionally arranged; it is also worth noting that the PSR is greatly affected by the mismatch of the resistors and the offset voltage of the operational amplifier. Please see in detail: EI-NozahM, TorresJ, EntesariK, Sanchez-SinencioE, "High PSR Low Drop Out Regulator with Feed-forward Ripple Cancellation Technique," IEEE J.Solid-StateCalculates, vol.45, pp.565-577, Feb 2010.
The architecture circuit shown in fig. 4 can improve the stability of the LDO system by effectively compensating the varying external pole with an adaptive zero generated as the load increases by the adaptive miller capacitance compensation technique. Due to the adoption of dynamic compensation, the system bandwidth is increased, and the PSRR characteristic of the LDO intermediate frequency band is improved to a certain extent. Please see in detail: XinqanLai, Jianping Guo, Zuozhi Sun, Jianzhang, Xie "A3-A CMOS low-drop regulator with adaptive Miller compensation" Analog integer Circuit Sig Process (2006)49: 5-10, DOI 10.1007/s 10470-006-.
However, it is easy to find that some of the new architectures proposed by the low dropout linear regulator for improving the low frequency gain and PSRR characteristics have more or less one or more limitations, and cannot fully and reliably enhance the PSR performance of the low dropout linear regulator.
Disclosure of Invention
In view of the above, the present invention is directed to a linear regulator with adaptive enhanced power supply rejection to meet the requirement of high-precision system design.
The invention realizes the technical scheme that the linear voltage stabilizer for the self-adaptive enhanced power supply suppression consists of a reference voltage module, a self-adaptive enhanced EA module, a PMOS power tube, two voltage division feedback resistors and a load impedance, wherein the input end of the linear voltage stabilizer is respectively connected to the source electrodes of the reference voltage module and the PMOS power tube MP, and the output end of the reference voltage module and the N of the self-adaptive enhanced EA modulePThe two voltage division feedback resistors are connected in series and connected in parallel with the load impedance, one end point of the parallel connection is grounded, the other end point of the parallel connection is connected with the drain electrode of the PMOS power tube MP to serve as the output end of the linear voltage stabilizer, and the voltage division nodes of the two voltage division feedback resistors are connected with the N of the self-adaptive enhanced EA moduleFThe output end of the self-adaptive enhanced EA module is connected with the grid electrode of the PMOS power tube MP; the adaptive enhancement EA module is a functional module consisting of a transconductance operational amplifier, a unit gain buffer, a power tube current sensing unit, a dynamic zero tracking compensation unit and an adaptive transconductance operational amplifier, and the N isFTerminal and NPThe ends are connected with two transconductance operational amplifiers, the transconductance operational amplifiers are sequentially connected with a unit gain buffer and a power tube current sensing unit, a dynamic zero tracking compensation unit is respectively connected with the transconductance operational amplifier, the self-adaptive transconductance operational amplifier, the unit gain buffer and the power tube current sensing unit in a converging manner, and a leading-out node N1 between the unit gain buffer and the power tube current sensing unit is connected with a grid electrode of a PMOS power tube MP, and the dynamic zero tracking compensation unit is characterized in that: the dynamic zero tracking compensation unit is formed by connecting NMOS variable resistors M1 and M2 and a zero-setting compensation capacitor CZ, wherein the NMOS variable resistors M1 and M2 are connected in a common-gate mode and grounded in a common-source mode, and the zero-setting compensation capacitor CZ is connected between the drain of the NMOS variable resistor M2 and the common-connection output end of the two transconductance operational amplifiers; the self-adaptive transconductance operational amplifier is formed by connecting an operational amplifier AS and an NMOS induction current tube M3, wherein the drain electrode of the NMOS induction current tube M3 is connected to the operational amplifier AS, the grid electrode of the NMOS induction current tube M3 is connected with the grid electrodes of NMOS variable resistors M1 and M2 in a dynamic zero tracking compensation unit in a common-mode, and the source electrode of the NMOS induction current tube M3 is grounded.
Further, the reference voltage module is adaptively increasedN of strong EA modulePThe output end of the end connection is provided with a filter circuit.
Furthermore, the main structures of the transconductance operational amplifier and the unit gain buffer are both amplifiers, where N isFThe end is connected into the positive input end of the transconductance operational amplifier, NPThe end is connected with the negative input end of the transconductance operational amplifier, the common output end of the two transconductance operational amplifiers is connected with the positive input end of the unit gain buffer, and the output end of the unit gain buffer is connected with the power tube current sensing unit and is fed back to be connected with the negative input end of the unit gain buffer.
The transconductance operational amplifier is formed by connecting eight PMOS tubes MP 211-MP 218 and four NMOS tubes MN 210-MN 213, and has the structure that a common grid of MP213, MP215 and MP217 is connected with a node VB2, a common source is connected with VDD, the common grid of MP214, MP216 and MP218 is connected with a node VB1, the source and drain of MP214 and MP213 are connected, the source and drain of MP216 and MP215 are connected, the source and drain of MP218 and MP217 are connected, the common source of MN211 and MN210 is connected with the ground and the common grid is connected with the drain of MP216, the common grid of MN213 and MN212 is connected with a node VB1, the common drain of MN213 and MP216 is connected with the drain of MP216, the common drain of MN212 and MP218 is connected with an output node VOX21 of the amplifier, the common source of MP211 and MP212 is connected with the drain of MP214, the grid of MP211 is the negative input end Vn of the amplifier, the grid of MP212 is the positive end of the amplifier, the drain of MP211 is connected with the drain of MN211 and the drain of the node MN213 is connected with the drain of the node.
Furthermore, the amplifier of the unity gain buffer is formed by connecting two PMOS tubes MP211 and MP222 and a current source with four NMOS tubes MN 221-MN 224, and the structure of the unity gain buffer is that MN221, MN222, MN223 and MN224 are connected to the common source and the ground, the current source is connected to the drain of MN221 and the common grid of MN221 and MN222, the common drain of MN222 and MN223 is connected to the drain of MP221 and the common grid of MN223 and MN224, MN224 is connected to the drain source of MP221, the source of MP221 is connected to the grid and the drain of MP222 in common, the grid of MP222 is the positive input end, and the grid of MP221 is the output node VOX 22.
Further, the power tube current sensing unit is formed by connecting a drain of a mirror tube MPS of the same type as the PMOS power tube and a source of a clamp tube MP1, wherein a gate-source voltage of the mirror tube MPS is equal to a gate-source voltage of the PMOS power tube MP, a gate lead-out node N1 of the mirror tube MPS, and a drain of the clamp tube MP1 is connected to the dynamic zero tracking compensation unit.
Furthermore, the operational amplifier AS of the self-adaptive transconductance operational amplifier is formed by connecting five PMOS tubes MP 251-MP 255, a gain enhancement amplifier and five NMOS tubes MN 250-MN 253 and MN255, and has the structure that: MP253, MP254 and MP255 are connected in common grid and connected with VDD in common source, the drain of MN255 is connected to the drain and the gate of MP254, the source of MN255 is grounded, and the gate is connected to the drain of NMOS induction current tube M3; MN253 and MN252 are connected in a common-gate mode, the common drain is connected with the drain of MP253, MP251 and MN253 are connected in a common-source mode, the grid electrode of MP251 is the negative input end Vn of a gain enhancement amplifier AS, MP252 and MN252 are connected in a common-source mode, the grid electrode of MP252 is the positive input end Vp of the amplifier AS, MN251 and MP251 are connected in a common-drain mode and connected with the negative input end of the gain enhancement amplifier, MN250 and MP252 are connected in a common-drain mode and connected with the positive input end of the gain enhancement amplifier AS and used AS the output node VOX25 of the amplifier AS, the bias current end of the gain enhancement amplifier is connected with the drain electrode of MP255, and MN251 and MN250 are connected in a common-source.
The linear voltage stabilizer improved structure has the prominent substantive characteristics and remarkable progress: the self-adaptive PSRR characteristic enhancement technology provided by the invention is based on high-gain DC gain design, enables the main pole of a loop to be capable of adaptively following the change of an output pole according to the load condition of an LDO (low dropout regulator), and simultaneously utilizes the dynamic zero tracking technology to keep the loop stable, so that the high PSR characteristic can be kept in a wider frequency range.
Drawings
Fig. 1 is a schematic circuit diagram of a conventional LDO.
FIG. 2 is a schematic diagram of a conventional LDO with high PSR.
FIG. 3 is a schematic diagram of another prior art LDO with improved PSR.
FIG. 4 is a schematic diagram of another prior art LDO with improved PSR.
FIG. 5 is a schematic diagram of an architecture of the adaptive PSR enhanced LDO of the present invention.
Fig. 6 is a functional module architecture diagram of the adaptive enhanced EA module of fig. 5.
Fig. 7 is a schematic diagram of an internal circuit configuration of the adaptive enhanced EA module of fig. 5.
Fig. 8 is a detailed circuit connection schematic diagram of the amplifier a1 in fig. 7.
Fig. 9 is a detailed circuit connection schematic diagram of the amplifier a2 in fig. 7.
Fig. 10 is a detailed circuit connection diagram of the amplifier AS in fig. 7.
FIG. 11 is a diagram of pole-zero of the adaptive PSR enhanced LDO system of the present invention.
Detailed Description
The following detailed description of the embodiments of the present invention is provided in connection with the accompanying drawings for the purpose of understanding and controlling the technical solutions of the present invention, so as to define the protection scope of the present invention more clearly.
In the process of designing a product by a high-precision system, a designer comprehensively analyzes the defects in multiple aspects of the performance of the traditional LDO and the improved structure reported in the prior art, considers and improves the defects in various structures, combines self experience and creative labor, and innovatively provides a linear voltage regulator with self-adaptive enhanced power supply rejection, so that a higher PSR characteristic is kept in a wider frequency range.
As shown in fig. 5, the linear regulator with adaptive enhanced power supply rejection of the present invention mainly comprises a reference voltage module 1, an adaptive enhanced EA module 2, a PMOS power transistor 3, two voltage-dividing feedback resistors 4, and a load impedance 5, wherein an input terminal of the linear regulator is respectively connected to source electrodes of the reference voltage module and the PMOS power transistor MP, an output terminal of the reference voltage module and N of the adaptive enhanced EA modulePThe two voltage division feedback resistors are connected in series and connected in parallel with the load impedance, one end point of the parallel connection is grounded, the other end point of the parallel connection is connected with the drain electrode of the PMOS power tube MP to serve as the output end of the linear voltage stabilizer, and the voltage division nodes of the two voltage division feedback resistors are connected with the N of the self-adaptive enhanced EA moduleFEnd-to-end, adaptively enhanced EA module outputIs connected with the grid of the PMOS power tube MP. As a further preferable design, the reference voltage module 1 is connected to the adaptive enhanced EA module 2 at NPThe output end connected with the end is also provided with a filter circuit.
As a core, the adaptive enhanced EA module 2 is a functional module composed of a transconductance operational amplifier 21, a unity gain buffer 22, a power tube current sensing unit 23, a dynamic zero tracking compensation unit 24, and an adaptive transconductance operational amplifier 25, as shown in fig. 6, where N in fig. 5FTerminal and NPTwo nodes at the end are connected with two transconductance operational amplifiers, the transconductance operational amplifier 21 is sequentially connected with a unit gain buffer 22 and a power tube current sensing unit 23, a dynamic zero tracking compensation unit 24 is respectively connected with the transconductance operational amplifier 21, the self-adaptive transconductance operational amplifier 25, the unit gain buffer 22 and the power tube current sensing unit 23 in a converging manner, and a leading-out node N1 between the unit gain buffer 22 and the power tube current sensing unit 23 is connected with a grid electrode of a PMOS power tube MP.
As shown in FIG. 7, the main structures of the transconductance operational amplifier and the unity gain buffer are both amplifiers, where N isFThe end is connected into the positive input end of the transconductance operational amplifier, NPThe end is connected with the negative input end of the transconductance operational amplifier, the common output end of the two transconductance operational amplifiers is connected with the positive input end of the unit gain buffer, and the output end of the unit gain buffer is connected with the current sensing segment element of the power tube and is fed back to be connected with the negative input end of the unit gain buffer. Node NFTerminal, NPThe ends of the reference voltage module are respectively connected with the output end of the reference voltage module and the voltage division node of the feedback resistor.
The transconductance operational amplifier 21 is mainly composed of an amplifier a1, and the amplifier a1 may be a high gain operational amplifier of any structure. As shown in fig. 8, a schematic diagram of one possible specific circuit connection of the amplifier a1 is shown. It can be seen from the figure that the amplifier is formed by connecting eight PMOS tubes MP and four NMOS tubes MN, and has the structure that MP213, MP215 and MP217 are connected with a common grid at a node VB2 and connected with VDD in a common source, MP214, MP216 and MP218 are connected with a common grid at a node VB1, MP214 and MP213 are connected with a source drain, MP216 and MP215 are connected with a source drain, MP218 and MP217 are connected with a source drain, MN211 and MN210 are connected with a common source and grounded and connected with a drain of MP216, MN213 and MN212 are connected with a common grid at a node VB1 and a common drain of MP216, MN212 and MP218 are connected with a common drain of the amplifier at an output node VOX21, MP211 and MP212 are connected with a drain of MP214 in a common source, the gate of MP211 is a negative input end Vn of the amplifier, the gate of MP212 is a positive input end of the amplifier, the drain of MP211 is connected with a drain source of MN210 and a drain end of NM212 is connected with a source node of the MP 213.
The unity gain buffer 22 is mainly implemented by the amplifier a2, and its structure is a unity gain buffer, which mainly aims to reduce the impedance of the node N1, and to reduce the impedance of the node N1 (i.e. the gate of the power transistor PMOS), so that the pole formed by the node N1 is out of the bandwidth. As shown in fig. 9, a schematic diagram of one possible specific circuit connection of the amplifier a2 is shown. The amplifier is formed by connecting two PMOS tubes MP, a current source and four NMOS tubes MN, and has the structure that MN221, MN222, MN223 and MN224 are connected with the common source to the ground, the current source is connected to the drain of the MN221 and the common grid of the MN221 and the MN222, the common drain of the MN222 and the MN223 is connected to the drain of the MP221 and the common grid of the MN223 and the MN224, the MN224 is connected with the drain source of the MP221, the source of the MP221 is connected with the grid and the drain of the MP222 in common, the grid of the MP222 is a positive input end, and the grid of the MP221 is an output node VOX 22.
Power tube current sensing unit 23: the power transistor is composed of a PMOS transistor MPs (mirror image transistor) and an MP1 (clamping) which are the same as the power PMOS in type, wherein the grid source voltage of the current mirror image transistor MPs is equal to the grid source voltage of the power transistor, the MP1 transistor is used for clamping, so that the drain end voltage of the MPs is also approximately equal to the drain end voltage of the power transistor, and therefore when the number of the power transistor and the MPs transistor is greatly different, the mirror image current in the MPs is still very accurate.
Dynamic zero tracking compensation 24: in order to realize the PSR self-adaption enhancement, the LDO loop needs to be compensated, the requirement can be met through dynamic zero tracking compensation, the circuit is composed of an NMOS variable resistor and a zero adjustment compensation capacitor, and the circuit realization method can be in various forms. A simple implementation is shown in fig. 7, which consists of an NMOS transistor M2 and a capacitor CZ.
Adaptive transconductance operational amplifier: the circuit is composed of an operational amplifier AS and an NMOS induction current tube M3, wherein the M3 is mainly used for providing induction current, the source electrode of the NMOS induction current tube M3 is connected to the operational amplifier AS, the grid electrode of the NMOS induction current tube M3 is connected with the grid electrodes of NMOS variable resistors M1 and M2 in a dynamic zero tracking compensation unit in a common-linkage mode, and the source electrode of the NMOS induction current tube M3 is grounded. The gain of the operational amplifier is determined by the sense current, the operational amplifier is almost not operated when the load current is small, the circuit is operated only when the load current reaches a certain value (Iout = Iset), at this time, the output impedance of a1 is reduced, and the corresponding pole is reduced, so that the bandwidth of the LDO system is increased. AS the load current increases, both the dominant and the next dominant pole of the LDO system start to decrease, and the gain is determined by AS. As long as the system is stable, the PSR characteristic of the LDO will still maintain a large value as the output current increases within the whole bandwidth. AS shown in fig. 10, a schematic diagram of one possible specific circuit connection of the amplifier AS is given. It can be seen from the figure that it is formed by connecting five PMOS transistors MP, one gain enhancement amplifier and five NMOS transistors MN, and its structure is: MP253, MP254 and MP255 are connected in common grid and connected with VDD in common source, the drain of MN255 is connected to the drain and the gate of MP254, the source of MN255 is grounded, and the gate is connected to the drain of NMOS induction current tube M3; MN253 and MN252 are connected in a common grid mode, the common drain is connected with the drain of the MP253, MP251 and MN253 are connected in a common source mode, the grid electrode of the MP251 is the negative electrode input end Vn of the amplifier AS, MP252 and MN252 are connected in a common source mode, the grid electrode of the MP252 is the positive electrode input end Vp of the amplifier AS, the common drain of the MN251 and MP251 is connected with the negative electrode input end of the gain enhancement amplifier, the common drain of the MN250 and MP252 is connected with the positive electrode input end of the gain enhancement amplifier and serves AS the output node VOX25 of the amplifier AS, the bias current end of the gain enhancement amplifier is connected with the drain of the MP255, and the MN251 and MN250 are connected in a common source mode and.
Generally, the channel resistance of the LDO regulator is rds, the output resistance of the parallel open loop to ground is Zo, and the resistance of the feedback loop is Zoreg, then:
Figure 477688DEST_PATH_IMAGE001
；
the PSR of the LDO is as follows in the low frequency band:
Figure 332512DEST_PATH_IMAGE002
，
wherein Al isoop_openFor loop open loop gain, β is the loop coefficient.
And in the middle frequency band, namely, the frequency is near the dominant pole frequency of the LDO:
Figure 112249DEST_PATH_IMAGE003
，
wherein GBW is the system gain bandwidth; it follows that the PSRR starts to drop at the main pole of the loop until, at unity gain frequency, the loop loses regulation capability.
Through the analysis, the low-frequency gain of the loop needs to be designed to be high enough to enhance the PSR characteristic of the DC; the loop bandwidth needs to be large enough to enhance the PSR of the intermediate frequency band; the self-adaptive PSRR characteristic enhancement technology provided by the invention is based on high-gain DC gain design, the dominant pole of a loop can be adaptively changed along with the output pole according to the load condition of an LDO, and meanwhile, the loop is kept stable by utilizing a dynamic zero tracking technology, so that the high PSR characteristic can be kept in a wider frequency range.
The adaptive PSR enhancing LDO system pole-zero diagram shown in fig. 11. The amplitude-frequency characteristic curve marked by the solid line is the distribution condition of the zero poles of the LDO system under the condition of light load; the amplitude-frequency characteristic curve marked by the dotted line is the zero-pole distribution condition of the LDO system under the heavy load condition; the LDO PSR characteristic enhancement technology provided by the invention adaptively adjusts the dominant pole and the zero of the system through the induction of load change, realizes high bandwidth and improves intermediate frequency gain.
The linear voltage stabilizer improved structure has the prominent substantive characteristics and remarkable progress: the self-adaptive PSRR characteristic enhancement technology provided by the invention is based on high-gain DC gain design, enables the main pole of a loop to be capable of adaptively following the change of an output pole according to the load condition of an LDO (low dropout regulator), and simultaneously utilizes the dynamic zero tracking technology to keep the loop stable, so that the high PSR characteristic can be kept in a wider frequency range.

Claims (7)

1. The linear voltage stabilizer consists of a reference voltage module, a self-adaptive enhanced EA (active energy absorption) module, a PMOS (P-channel metal oxide semiconductor) power tube, two voltage division feedback resistors and a load impedance, wherein the input end of the linear voltage stabilizer is respectively connected to the source electrodes of the reference voltage module and the PMOS power tube MP, and the output end of the reference voltage module and the N of the self-adaptive enhanced EA modulePThe two voltage division feedback resistors are connected in series and connected in parallel with the load impedance, one end point of the parallel connection is grounded, the other end point of the parallel connection is connected with the drain electrode of the PMOS power tube MP to serve as the output end of the linear voltage stabilizer, and the voltage division nodes of the two voltage division feedback resistors are connected with the N of the self-adaptive enhanced EA moduleFThe output end of the self-adaptive enhanced EA module is connected with the grid electrode of the PMOS power tube MP; the adaptive enhancement EA module is a functional module consisting of a transconductance operational amplifier, a unit gain buffer, a power tube current sensing unit, a dynamic zero tracking compensation unit and an adaptive transconductance operational amplifier, and the N isFTerminal and NPThe ends are connected with a transconductance operational amplifier and a self-adaptive transconductance operational amplifier, the outputs of the transconductance operational amplifier and the self-adaptive transconductance operational amplifier are sequentially connected with a unit gain buffer and a power tube current sensing unit, a dynamic zero tracking compensation unit is respectively connected with the transconductance operational amplifier, the self-adaptive transconductance operational amplifier, the unit gain buffer and the power tube current sensing unit in a converging manner, and a leading-out node N1 between the unit gain buffer and the power tube current sensing unit is connected with a grid electrode of a PMOS power tube MP, and the self-adaptive transconductance operational amplifier is characterized in that: the dynamic zero tracking compensation unit is formed by connecting NMOS variable resistors M1 and M2 and a zero-setting compensation capacitor CZ, wherein the NMOS variable resistors M1 and M2 are connected in a common-gate mode and grounded in a common-source mode, and the zero-setting compensation capacitor CZ is connected between the drain of the NMOS variable resistor M2 and the common-connection output end of the transconductance operational amplifier and the self-adaptive transconductance operational amplifier; the adaptive transconductance operational amplifier is formed by connecting an operational amplifier AS and an NMOS induction current tube M3, wherein the NMOS induction current tube M3The drain is connected to the operational amplifier AS, the grid of the NMOS induction current tube M3 is connected with the grids of the NMOS variable resistors M1 and M2 in the dynamic zero tracking compensation unit in a common mode, and the source of the NMOS induction current tube M3 is grounded.
2. The adaptive boost supply rejection linear regulator according to claim 1, wherein: the reference voltage module is connected with the adaptive enhanced EA module by NPThe output end of the end connection is provided with a filter circuit.
3. The adaptive boost supply rejection linear regulator according to claim 1, wherein: the main structures of the transconductance operational amplifier and the unit gain buffer are both amplifiers, wherein N isFThe end is connected into the positive input end of the transconductance operational amplifier, NPThe end is connected with the negative input end of the transconductance operational amplifier, the joint output end of the transconductance operational amplifier and the self-adaptive transconductance operational amplifier is connected with the positive input end of the unit gain buffer, and the output end of the unit gain buffer is connected with the power tube current sensing unit and is connected with the negative input end of the unit gain buffer in a feedback mode.
4. The adaptive boost supply rejection linear regulator according to claim 3, wherein: the transconductance operational amplifier is formed by connecting eight PMOS tubes MP 211-MP 218 and four NMOS tubes MN 210-MN 213, and has the structure that MP213, MP215 and MP217 are connected with a common grid at a node VB2 and connected with a common source at VDD, the common grid of MP214, MP216 and MP218 is connected with a node VB1, MP214 is connected with the source and drain of MP213, MP216 is connected with the source and drain of MP215, the source and drain of MP218 is connected with the source and drain of MP217, MN211 is connected with the common source of MN210 and the common grid is connected with the drain of MP216, MN213 and MN212 are connected with a common grid at a node VB1, MN213 is connected with the common drain of MP216, MN212 is connected with the drain of MP218 in common with an output node VOX21 of the amplifier, MP211 and MP212 are connected with the drain of MP214 in common source, the grid of MP211 is the negative input end Vn of the amplifier, the grid of MP212 is the positive input end of the amplifier, the drain of MP211 is connected with the drain of MN211 is connected with the drain end of the drain of MN 211.
5. The adaptive boost supply rejection linear regulator according to claim 3, wherein: the amplifier of the unit gain buffer is formed by connecting two PMOS tubes MP221 and MP222, a current source and four NMOS tubes MN 221-MN 224, and the structure of the amplifier is that the common sources of MN221, MN222, MN223 and MN224 are grounded, the current source is connected to the drain of the MN221 and the common grid of the MN221 and MN222, the common drain of the MN222 and the MN223 is connected to the drain of the MP221 and the common grid of the MN223 and MN224, the MN224 is connected with the drain source of the MP221, the source of the MP221 is connected with the grid and the drain of the MP222 in a common mode, the grid of the MP222 is an anode input end, and the grid of the MP221 is an output node VOX 22.
6. The adaptive boost supply rejection linear regulator according to claim 1, wherein: the power tube current sensing unit is formed by connecting a drain electrode of a mirror image tube MPS and a source electrode of a clamp tube MP1, wherein the drain electrode of the mirror image tube MPS is the same as the PMOS power tube, the gate-source voltage of the mirror image tube MPS is equal to the gate-source voltage of the PMOS power tube MP, a node N1 is led out from the gate electrode of the mirror image tube MPS, and the drain electrode of the clamp tube MP1 is connected to the dynamic zero tracking compensation unit.
7. The adaptive boost supply rejection linear regulator according to claim 1, wherein: the operational amplifier AS of the self-adaptive transconductance operational amplifier is formed by connecting five PMOS tubes MP 251-MP 255, a gain enhancement amplifier and five NMOS tubes MN 250-MN 253 and MN255, and has the structure that: MP253, MP254 and MP255 are connected in common grid and connected with VDD in common source, the drain of MN255 is connected to the drain and the gate of MP254, the source of MN255 is grounded, and the gate is connected to the drain of NMOS induction current tube M3; MN253 and MN252 are connected in a common-gate mode, the common drain is connected with the drain of MP253, MP251 and MN253 are connected in a common-source mode, the grid electrode of MP251 is the negative input end Vn of an amplifier AS, MP252 and MN252 are connected in a common-source mode, the grid electrode of MP252 is the positive input end Vp of the amplifier AS, MN251 and MP251 are connected in a common-drain mode and connected with the negative input end of a gain enhancement amplifier, MN250 and MP252 are connected in a common-drain mode and connected with the positive input end of the gain enhancement amplifier AS the output node VOX25 of the amplifier AS, the bias current end of the gain enhancement amplifier is connected with the drain of MP255, and MN251 and MN250 are connected in a common-source mode and connected with.
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