JP2015146497A - amplifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an amplifier circuit capable of being operated at a high speed when capacity load is connected thereto.SOLUTION: A second amplifying stage 20 has very large output resistance, and a pole frequency fp_L caused by this output resistance and output capacity (capacitor Co) is the lowest pole frequency in a transfer function. Since the pole frequency limiting the upper limit of a frequency band becomes high in comparison with a conventional operational amplifier whose upper limit of the frequency band is limited by the pole frequency fp_L caused by the output resistance and the output capacity, the lowest pole frequency in the transfer function is made possible to be put in a higher frequency.

Description

  The present invention relates to an amplifier circuit that amplifies a signal output from a sensor or the like, and more particularly to an amplifier circuit that drives a capacitive load.

  A capacitive sensor element used for a humidity sensor, an acceleration sensor, or the like is an element whose capacitance changes in accordance with a physical quantity, and the change in capacitance is generally called a capacitance-voltage conversion circuit (CV conversion circuit). ) To be converted into an electrical signal.

  FIG. 5 is a diagram illustrating an example of a sensor device using a capacitive sensor element. FIG. 5A shows a general configuration of a CV conversion circuit that converts the capacitance of the capacitive sensor element into an electric signal. 5B and 5C show waveforms of the drive voltages VP1 and VP2 of the capacitive sensor element. FIG. 5D shows an on / off state of the switch SW1. FIG. 5E shows the waveform of the detection signal VS.

  The capacitive sensor elements 104 and 105 of the sensor unit 106 are configured such that the difference in capacitance changes according to physical quantities such as humidity and acceleration. Opposite phase driving voltages VP1 and VP2 are applied to both ends of the capacitive sensor elements 104 and 105 connected in series, respectively. The drive voltages VP1 and VP2 are output from the inverter circuit 102 and the buffer circuit 103 based on the periodic pulse signal of the pulse generator 101, respectively. The common connection node of the capacitive sensor elements 104 and 105 is connected to the inverting input terminal of the operational amplifier 107 constituting the charge amplifier. A capacitor 108 and a switch SW1 are connected in parallel between the inverting input terminal and the output terminal of the operational amplifier 107. The reference voltage Vref is input to the non-inverting input terminal of the operational amplifier 107. The reference voltage Vref is generally set to an intermediate voltage between the high level and the low level of the drive voltages VP1 and VP2. The output signal (detection signal Vs) of the operational amplifier 107 is converted into a digital signal DAT by the AD converter 109.

  In the sensor device shown in FIG. 5, when the switch SW1 is on (FIG. 5D), one of the drive voltages VP1 and VP2 is at a high level and the other is at a low level (FIGS. 5B and 5C). At this time, the voltage across the capacitor 108 is reset to zero, and the charge is discharged. Almost the same voltage is applied to both ends of the capacitive sensor elements 104 and 105, and charges corresponding to the capacitance are accumulated.

  When the switch SW1 changes from on to off, the levels of the drive voltages VP1 and VP2 are inverted. At this time, substantially the same voltage is applied to both ends of the capacitive sensor elements 104 and 105, respectively, but the polarity of the voltage is reversed with respect to the case where the switch SW1 is on. When the capacitances of the capacitive sensor elements 104 and 105 are not the same, the total amount of charges accumulated in the capacitive sensor elements 104 and 105 is changed by reversing the polarity of the voltage. The electric charge corresponding to this change is accumulated in the capacitor 108. Since the charge accumulated in the capacitor 108 is proportional to the difference in capacitance between the capacitive sensor elements 104 and 105, the detection signal Vs during the period when the switch SW1 is off is the capacitance of the capacitive sensor elements 104 and 105. The voltage depends on the difference. The difference in capacitance appears as a difference from the reference voltage Vref. By periodically inverting the levels of the drive voltages VP1 and VP2 when the switch SW1 is on, the polarity of the difference from the reference voltage Vref is also periodically inverted.

  In order to accurately detect the difference in capacitance between the capacitive sensor elements 104 and 105, it is necessary to reduce noise included in the detection signal Vs, and as many detection signals Vs as possible are sampled and averaged. It is preferable to do. However, if the sampling operation is slow, the time required to obtain one detection result becomes long and the operation time of the circuit becomes long, so that the average current consumption increases. In order to increase the number of samplings while suppressing the average current consumption, it is necessary to speed up the sampling operation. Therefore, the operational amplifier 107 of the CV conversion circuit is required to operate at high speed with a capacitive load connected.

  FIG. 6 is a diagram showing a configuration of a conventional general operational amplifier. The operational amplifier shown in FIG. 6 includes P-type MOS transistors Q101, Q102, Q107, and Q108, N-type MOS transistors Q103, Q104, Q105, and Q106, a constant current source 111, a resistor Rc, and a capacitor Cc. The MOS transistors Q101 and Q102 receive a differential voltage (VIN +, VIN−) at a pair of gates. The constant current source 111 supplies a constant current from the power supply line (VDD) to the commonly connected sources of the MOS transistors Q101 and Q102. A MOS transistor Q103 is provided between the drain of the MOS transistor Q101 and the ground (VSS), and a MOS transistor Q105 is provided between the drain of the MOS transistor Q102 and the ground (VSS). The gate of the MOS transistor Q104 is connected to the gate and drain of the MOS transistor Q103, its source is connected to the ground (VSS), and its drain is connected to the power supply line (VDD) via the MOS transistor Q107. The gate of the MOS transistor Q106 is connected to the gate and drain of the MOS transistor Q105, its source is connected to the ground (VSS), and its drain is connected to the power supply line (VDD) via the MOS transistor Q108. The gate of MOS transistor Q107 is connected to the gate and drain of MOS transistor Q108. Resistor Rc and capacitor Cc are connected in series between the drains of MOS transistors Q104 and Q107 and the drain of MOS transistor Q102. The drains of the MOS transistors Q104 and Q107 serve as an output (OUT) connected to the load.

  A current having a difference corresponding to the differential voltage (VIN +, VIN−) flows through the MOS transistors Q101, Q102. Since the MOS transistors Q103 and Q104 constitute a current mirror circuit, a current corresponding to the current of the MOS transistor Q101 tends to flow through the MOS transistor Q104. On the other hand, since the MOS transistors Q105 and Q106 and the MOS transistors Q107 and Q108 also constitute current mirror circuits, a current corresponding to the current of the MOS transistor Q102 tends to flow through the MOS transistor Q107. When a load is connected to the output (OUT), the load has a current corresponding to the difference between the current flowing through the MOS transistor Q101 and the current flowing through the MOS transistor Q102, that is, a differential voltage (VIN +, VIN−). A corresponding current flows.

  FIG. 7 is a diagram showing the frequency characteristics of the gain and phase of the transfer function of the operational amplifier shown in FIG. In FIG. 7, “fp_M” and “fp_L” indicate the pole frequencies of the transfer function, respectively. The lowest pole frequency fp_M is a pole frequency set by the phase compensation circuit (a series circuit of the resistor Rc and the capacitor Cc), and the second lowest pole frequency fp_L is the output resistance and load capacitance of the operational amplifier (example in FIG. 5). Then, the polar frequency is caused by the input capacitance of the AD converter 109 and the capacitance of the capacitor 108. The pole frequency fp_M by the phase compensation circuit is set so that sufficient phase margin and gain margin can be obtained according to the pole frequency fp_L caused by the load capacitance and the output resistance.

  In the conventional operational amplifier having the transfer characteristics shown in FIG. 7, the upper limit of the frequency band is determined by the pole frequency fp_L caused by the load capacitance and the output resistance, and therefore there is a problem that it is difficult to further extend the frequency band to a high frequency.

  Also, when the pole frequency fp_L is at a low position, if the system stability is to be ensured only by setting the pole frequency fp_M of the phase compensation circuit, the pole frequency fp_M must also be lowered, and the response will be significantly slowed down. End up. In order to avoid this, if the mutual conductance gm of the MOS transistors Q101 and Q102 constituting the differential pair is reduced to reduce the gain, there arises a problem that input noise increases.

  The present invention has been made in view of such circumstances, and an object thereof is to provide an amplifier circuit that can operate at high speed when a capacitive load is connected.

An amplifier circuit according to the present invention includes a pair of first and second transistors constituting a differential pair, a first amplification stage for amplifying a differential signal input to the differential pair, and the first amplification A second amplification stage for further amplifying the differential signal amplified in the stage and an output capacitor connected to the output of the second amplification stage, wherein the lowest pole frequency in the transfer function is The pole frequency is caused by the output resistance of the amplification stage and the capacitance of the output capacitor.
According to said structure, the pole frequency resulting from the said output resistance and the electrostatic capacitance of the said output capacitor is made into the lowest pole frequency in a transfer function. As a result, the pole frequency that limits the upper limit of the frequency band is higher than that of an operational amplifier that limits the upper limit of the frequency band due to the pole frequency caused by the output resistance and the capacitance of the output capacitor, and the highest in the transfer function. A low pole frequency can be placed at a higher frequency.

  Preferably, the first amplification stage includes a constant current source provided in a current path between a common connection node of the pair of first transistor and second transistor and a first power supply line, the first transistor, A first load circuit provided in a current path between two power supply lines, and a second load circuit provided in a current path between the second transistor and the second power supply line. The second amplification stage may amplify a difference between a voltage generated in the first load circuit and a voltage generated in the second load circuit.

Preferably, each of the first load circuit and the second load circuit may be a resistance element.
Thereby, input noise can be suppressed compared with the case where active elements, such as a transistor, are used as a load circuit.

  Preferably, the second amplification stage is provided in a current path between a first node and the second power supply line, and controls a current according to a voltage generated in the first load circuit; A fourth transistor provided in a current path between a second node and the second power supply line and controlling a current according to a voltage generated in the second load circuit; the first node; and the first power supply line Is provided in a current path between the second node and the first power line, and is provided in a current path between the second node and the first power supply line. A sixth transistor in which a current according to the current flows, a seventh transistor provided as a current buffer of a high output resistance in a current path between the third transistor and the first node, the fourth transistor, An eighth transistor provided as a high output resistance current buffer in the current path between the two nodes, and a high output resistance current buffer provided in the current path between the fifth transistor and the first node. A ninth transistor and a tenth transistor provided as a high output resistance current buffer in a current path between the sixth transistor and the second node may be included. The output capacitor may be connected to at least one of the first node and the second node.

  Preferably, a difference between a voltage at a connection node between the third transistor and the seventh transistor and a voltage at a connection node between the fourth transistor and the eighth transistor is amplified, and the amplification result is expressed by the seventh transistor. A first differential amplifying unit that outputs a differential voltage between a control voltage and a control voltage of the eighth transistor may be provided.

  Preferably, the difference between the voltage at the connection node between the fifth transistor and the ninth transistor and the voltage at the connection node between the sixth transistor and the tenth transistor is amplified, and the result of amplification is amplified by the ninth transistor. A second differential amplifier that outputs a differential voltage between the control voltage and the control voltage of the tenth transistor may be included.

  Preferably, the constant voltage is set such that an intermediate voltage between a voltage at a connection node between the first transistor and the first load circuit and a voltage at a connection node between the second transistor and the second load circuit approaches a predetermined voltage. You may have a common mode feedback part which controls the electric current of a current source.

  According to the present invention, it is possible to provide an amplifier circuit that can operate at high speed when a capacitive load is connected.

It is a figure which shows an example of a structure of the amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the frequency characteristic of the gain and phase of a transfer function of the amplifier circuit which concerns on embodiment of this invention. FIG. 2A shows frequency characteristics of a conventional operational amplifier, and FIG. 2B shows frequency characteristics of an amplifier circuit according to an embodiment of the present invention. It is a figure which shows the modification of the amplifier circuit which concerns on embodiment of this invention. It is a figure which shows the other modification of the amplifier circuit which concerns on embodiment of this invention. It is a figure which shows an example of the sensor apparatus using a capacitive sensor element. FIG. 5A shows a general configuration of a CV conversion circuit that converts the capacitance of the capacitive sensor element into an electric signal. 5B and 5C show waveforms of the driving voltage of the capacitive sensor element. FIG. 5D shows the on / off state of the switch. FIG. 5E shows the waveform of the detection signal. It is a figure which shows the structure of the conventional general operational amplifier. It is a figure which shows the frequency characteristic of the gain of a transfer function of the operational amplifier shown in FIG. 6, and a phase.

FIG. 1 is a diagram illustrating an example of a configuration of an amplifier circuit according to an embodiment of the present invention.
The amplifier circuit shown in FIG. 1 includes a first amplification stage 10, a second amplification stage 20, a common mode feedback unit 30, a reference voltage generation unit 40, an output capacitor Co, and an output resistance Ro.

  The first amplification stage 10 is a circuit for amplifying an input differential signal (VIN +, VIN−). In the example of FIG. 1, the pair of first transistor Q1 and second transistor Q2 constituting the differential pair. And a constant current source 11 and resistors R1 and R2. The first transistor Q1 and the second transistor Q2 are P-type MOS transistors.

  One of the differential signals (input signal VIN +) is input to the gate of the first transistor Q1, and the other of the differential signals (input signal VIN−) is input to the gate of the second transistor Q2.

  The constant current source 11 is a current path between a commonly connected source of the first transistor Q1 and the second transistor Q2 and a power supply line for supplying a power supply voltage VDD (hereinafter sometimes referred to as “power supply line VDD”). Is provided. The constant current source 11 allows a constant current to flow from the power supply line to the differential pair (Q1, Q2).

  The resistor R1 is provided in a current path between the drain of the first transistor Q1 and a power supply line that supplies the ground potential VSS (hereinafter, may be referred to as “ground VSS”). The resistor R2 is provided in a current path between the drain of the second transistor Q2 and the ground VSS. The resistor R1 is an example of a first load circuit in the present invention. The resistor R2 is an example of a second load circuit in the present invention.

  The second amplification stage 20 is a circuit that further amplifies the differential signal amplified in the first amplification stage 10, and amplifies the difference between the voltage generated in the resistor R1 and the voltage generated in the resistor R2. In the example of FIG. 1, the second amplification stage 20 includes a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, A ninth transistor Q9; a tenth transistor Q10; a first differential amplifier 21; and a second differential amplifier 22. The third transistor Q3, the fourth transistor Q4, the seventh transistor Q7 and the eighth transistor Q8 are N-type MOS transistors, and the fifth transistor Q5, the sixth transistor Q6, the ninth transistor Q9 and the tenth transistor Q10 are P-type. MOS transistor.

  The third transistor Q3 is provided in the current path between the first node N1 and the ground VSS, and controls the current according to the voltage generated in the resistor R1. The source of the third transistor Q3 is connected to the ground VSS, its drain is connected to the first node N1 via the seventh transistor Q7, and its gate is connected to the drain (seventh node N7) of the first transistor Q1. .

  The fourth transistor Q4 is provided in the current path between the second node N2 and the ground VSS, and controls the current according to the voltage generated in the resistor R2. The source of the fourth transistor Q4 is connected to the ground VSS, the drain thereof is connected to the second node N2 via the eighth transistor Q8, and the gate thereof is connected to the drain of the second transistor Q2 (eighth node N8). .

  The fifth transistor Q5 is provided in a current path between the first node N1 and the power supply line VDD, and a current according to the first bias voltage Vb1 flows. The source of the fifth transistor Q5 is connected to the power supply line VDD, the drain thereof is connected to the first node N1 via the ninth transistor Q9, and the first bias voltage Vb1 is input to the gate thereof.

  The sixth transistor Q6 is provided in a current path between the second node N2 and the power supply line VDD, and a current according to the first bias voltage Vb1 flows. The source of the sixth transistor Q6 is connected to the power supply line VDD, the drain is connected to the second node N2 via the tenth transistor Q10, and the first bias voltage Vb1 is input to the gate.

  The voltage of the second node N2 is applied to the gates of the fifth transistor Q5 and the sixth transistor Q6 as the common first bias voltage Vb1. The fifth transistor Q5 and the sixth transistor Q6 constitute a current mirror circuit that operates so that a current corresponding to the current of the sixth transistor Q6 flows to the fifth transistor Q5.

  The seventh transistor Q7 is provided as a current buffer having a high output resistance in the current path between the third transistor Q3 and the first node N1. The seventh transistor Q7 and the third transistor Q3 constitute a cascode circuit, and the output resistance of the drain of the seventh transistor Q7 viewed from the first node N1 is a very large value.

  The eighth transistor Q8 is provided as a current buffer with a high output resistance in the current path between the fourth transistor Q4 and the second node N2. The eighth transistor Q8 and the fourth transistor Q4 constitute a cascode circuit, and the output resistance of the drain of the eighth transistor Q8 viewed from the second node N2 has a very large value.

  The ninth transistor Q9 is provided as a current buffer having a high output resistance in the current path between the fifth transistor Q5 and the first node N1. The ninth transistor Q9 and the fifth transistor Q5 constitute a cascode circuit, and the output resistance of the drain of the ninth transistor Q9 viewed from the first node N1 has a very large value.

  The tenth transistor Q10 is provided as a current buffer with a high output resistance in the current path between the sixth transistor Q6 and the second node N2. The tenth transistor Q10 and the sixth transistor Q6 constitute a cascode circuit, and the output resistance of the drain of the tenth transistor Q10 viewed from the second node N2 has a very large value.

  The first differential amplifier 21 includes a voltage at a connection node (third node N3) between the third transistor Q3 and the seventh transistor Q7, and a connection node (fourth node N4) between the fourth transistor Q4 and the eighth transistor Q8. ) To amplify the difference with voltage. The first differential amplifier 21 outputs the amplification result of this voltage difference as a differential voltage between the control voltage (gate voltage) of the seventh transistor Q7 and the control voltage (gate voltage) of the eighth transistor Q8. That is, the first differential amplifier 21 adjusts the difference between the gate voltages of the seventh transistor Q7 and the eighth transistor Q8 so that the voltage difference between the third node N3 and the fourth node N4 becomes small.

  The second differential amplifier 22 includes a voltage at a connection node (fifth node N5) between the fifth transistor Q5 and the ninth transistor Q9, and a connection node (sixth node N6) between the sixth transistor Q6 and the tenth transistor Q10. ) To amplify the difference with voltage. The second differential amplifier 22 outputs the amplification result of this voltage difference as a differential voltage between the control voltage (gate voltage) of the ninth transistor Q9 and the control voltage (gate voltage) of the tenth transistor Q10. That is, the second differential amplifying unit 22 adjusts the difference between the gate voltages of the ninth transistor Q9 and the tenth transistor Q10 so that the voltage difference between the fifth node N5 and the sixth node N6 becomes small.

  The output capacitor Co and the output resistor Ro are connected in series between the first node N1 (OUT) from which the amplification result of the differential signal (VIN +, VIN−) is output and the ground VSS.

  The common mode feedback section 30 is intermediate between the voltage at the connection node (seventh node N7) between the first transistor Q1 and the resistor R1 and the voltage at the connection node (eighth node N8) between the second transistor Q2 and the resistor R2. The constant current source 11 is controlled so that the voltage approaches the reference voltage Vref.

  In the example of FIG. 1, the common mode feedback unit 30 includes a resistor Rc1, a resistor Rc2, and a differential amplifying unit 31. The resistor Rc1 and the resistor Rc2 are connected in series between the seventh node N7 and the eighth node N8. The differential amplifier 31 amplifies the difference between the voltage at the common connection node of the resistors Rc1 and Rc2 and the reference voltage Vref, and outputs the amplification result to the constant current source 11. Since the resistance Rc1 and the resistance Rc2 have substantially the same resistance value, the voltage at the common connection node of the resistance Rc1 and the resistance Rc2 is an approximately intermediate voltage between the voltage at the seventh node N7 and the voltage at the eighth node N8. The current of the constant current source 11 is controlled according to the output signal of the differential amplifying unit 31 so that the intermediate voltage becomes substantially equal to the reference voltage Vref.

  The reference voltage generation unit 40 is a circuit that generates a reference voltage Vref to be input to the common mode feedback unit 30. In the example of FIG. 1, the reference voltage generation unit 40 includes a P-type MOS transistor Q15 and a constant current source 41. The source of the MOS transistor Q15 is connected to the power supply line VDD, and the gate and drain thereof are connected to the constant current source 41. The constant current source 41 allows a constant current to flow from the drain of the MOS transistor Q15 to the ground VSS. The voltage generated at the gate of the MOS transistor Q15 is supplied to the common mode feedback unit 30 as the reference voltage Vref.

  Here, the operation of the amplifier circuit shown in FIG. 1 having the above-described configuration will be described.

When the voltage of the input signal VIN + becomes higher than the voltage of the input signal VIN−, the current of the first transistor Q1 becomes smaller than the current of the second transistor Q2, and the voltage of the resistor R1 is lower than the voltage of the resistor R2. Become. Thereby, the current of the third transistor Q3 becomes smaller than the current of the fourth transistor Q4. The fifth transistor Q5 and the sixth transistor Q6 constitute a current mirror circuit, and the fifth transistor Q5 tries to pass the same current as the fourth transistor Q4. Therefore, the current of the third transistor Q3 is the same as that of the fifth transistor Q5. It becomes smaller with respect to the current. Accordingly, a current flows in the direction discharged from the power supply line VDD through the output capacitor Co and the output resistor Ro connected to the first node N1 (OUT), and the voltage of the first node N1 (OUT) rises. As the input signal VIN + increases with respect to the input signal VIN−, the current of the third transistor Q3 decreases with respect to the current of the fifth transistor Q5, so that the current discharged at the first node N1 (OUT) increases.
On the other hand, when the voltage of the input signal VIN + is lower than the voltage of the input signal VIN−, the current of the third transistor Q3 becomes larger than the current of the fifth transistor Q5 due to the reverse operation to the above. A current flows through the 1 node N1 (OUT) in a direction toward the ground VSS, and the voltage of the first node N1 (OUT) decreases. As the input signal VIN + decreases with respect to the input signal VIN−, the current of the third transistor Q3 increases with respect to the current of the fifth transistor Q5, and thus the current drawn at the first node N1 (OUT) increases.
Through the above operation, the result of amplifying the differential signals (VIN +, VIN−) is output as a current from the first node N1 (OUT).

  In the above differential amplification operation, the seventh transistor Q7, the eighth transistor Q8, the ninth transistor Q9, and the tenth transistor Q10 of the second amplification stage 20 each function as a current buffer (gate ground circuit) of the cascode circuit. Therefore, compared with the case where these are not provided, the output resistance of the first node N1 (OUT) becomes very large.

In addition, since the first differential amplifier 21 adjusts the difference in gate voltage between the seventh transistor Q7 and the eighth transistor Q8 so that the voltage difference between the third node N3 and the fourth node N4 is reduced, When the transistor Q3 and the fourth transistor Q4 are viewed as differential current sources, the voltage difference between the third node N3 and the fourth node N4 is constant regardless of the magnitude of the differential current, and the apparent output resistance is further increased. Get higher.
On the other hand, the second differential amplifier 22 adjusts the difference between the gate voltages of the ninth transistor Q9 and the tenth transistor Q10 so that the voltage difference between the fifth node N5 and the sixth node N6 is reduced. The gate voltages of the fifth transistor Q5 and the sixth transistor Q6 are substantially equal and the drain voltages of the fifth transistor Q5 and the sixth transistor Q6 are also substantially equal, and the current difference between the fifth transistor Q5 and the sixth transistor Q6 becomes very small. Therefore, when the fifth transistor Q5 and the sixth transistor Q6 are viewed as a current source of the differential current, the differential current is kept at zero, so that the apparent output resistance becomes very high.
Therefore, by providing the first differential amplifier 21 and the second differential amplifier 22, the output resistance of the first node N1 (OUT) is further increased.

FIG. 2 is a diagram illustrating the frequency characteristics of the gain and phase of the transfer function of the amplifier circuit according to the present embodiment. FIG. 2A shows the frequency characteristics of the conventional operational amplifier, and FIG. 2B shows the frequency characteristics of the amplifier circuit according to this embodiment.
As described above, since the output resistance of the second amplification stage 20 is extremely large in the amplifier circuit shown in FIG. 1, the polar frequency fp_L resulting from the output resistance and the output capacitance (capacitor Cc) of the second amplification stage 20 is as shown in FIG. As shown in comparison with FIG. 2B, the frequency shifts to a lower frequency than that of the conventional operational amplifier (FIG. 5). In the amplifier circuit shown in FIG. 1, there is no pole frequency fp_M due to the phase compensation circuit (capacitor Cc, resistor Rc) like the conventional operational amplifier (FIG. 5), and the pole frequency fp_L is the lowest pole frequency in the transfer function. ing. The second lowest pole frequency fp_F is a pole frequency resulting from the output resistance (R1, R2) of the first amplification stage 10 and the input capacitance (such as the gate capacitance of Q3, Q4) of the second amplification stage 20.

  Comparing the lowest pole frequency in the transfer function, the pole frequency fp_L (FIG. 2B) of the amplifier circuit according to this embodiment is higher than the pole frequency fp_M (FIG. 2A) of the conventional operational amplifier. Therefore, the amplifier circuit according to this embodiment operates at a higher frequency than the conventional operational amplifier.

  As described above, in the amplifier circuit according to the present embodiment, the second amplifier stage 20 has a very large output resistance, and the polar frequency fp_L caused by the output resistance and the output capacitance (capacitor Co) is The lowest pole frequency in the transfer function. That is, by causing the gain decrease due to the pole frequency fp_L to occur from a frequency sufficiently lower than other pole frequencies (fp_F, etc.), the phase compensation circuit for the pole frequency fp_L (FIG. 5) ( A sufficient gain margin and phase margin are obtained without providing the capacitor Cc and the resistor Rc). Thereby, compared with the conventional operational amplifier in which the upper limit of the frequency band is limited by the polar frequency fp_L caused by the output resistance and the output capacitance (capacitor Co), the pole frequency (such as fp_F) that limits the upper limit of the frequency band is reduced. Because it becomes higher, it is possible to place the lowest pole frequency in the transfer function at a higher frequency. Accordingly, when a capacitive load is connected, it is possible to operate at a higher speed than the conventional operational amplifier.

  Further, according to the amplifier circuit according to the present embodiment, the pole frequency (such as fp_F) that limits the upper limit of the frequency band is increased, and therefore, the first transistor Q1 and the second transistor Q2 constituting the differential pair of the first amplifier stage 10 are increased. Even if the mutual conductance gm of the transistor Q2 is increased, sufficient gain margin and phase margin can be obtained. Thereby, the input noise caused by the first transistor Q1 and the second transistor Q2 of the first amplification stage 10 can be reduced.

  Furthermore, since the resistors R1 and R2 are provided as the load of the differential pair (Q1, Q2) of the first amplification stage 10 in the amplifier circuit according to the present embodiment, compared to the case where an active element such as a transistor is used as the load. Thus, input noise can be reduced.

  Further, according to the amplifier circuit according to the present embodiment, the current of the constant current source 11 is controlled by the common mode feedback unit 30 so that the common mode voltage of the drain of the differential pair (Q1, Q2) approaches the reference voltage Vref. Therefore, fluctuations in the bias current of the differential pair (Q1, Q2) due to fluctuations in the power supply voltage VDD and changes in temperature can be suppressed to improve power supply fluctuation removal performance, offset voltage temperature characteristics, and the like.

  In addition, this invention is not limited to embodiment mentioned above, Various modifications are included.

  For example, in the above-described embodiment, an example in which a single signal based on the ground potential VSS is output as an amplification result of the differential signal (VIN +, VIN−) is shown, but the present invention is not limited to this. In another embodiment of the present invention, for example, as shown in FIG. 3, a differential signal may be output as the amplification result of the differential signal (VIN +, VIN−). In the example of FIG. 4, the first bias voltage Vb1 of the gates of the fifth transistor Q5 and the sixth transistor Q6 is generated by a bias voltage generation circuit (not shown). The amplified differential signal is output from both ends of the first node N1 and the second node N2. The output capacitor Cc and the output resistor Rc may be connected between the first node N1 and the second node N2 as shown in FIG. 3, or are connected between these nodes and the power supply line VDD and the ground VSS. May be.

  In the embodiment described above, the resistance elements (R1, R2) are used as the first load circuit and the second load circuit, but the present invention is not limited to this. In another embodiment of the present invention, for example, as shown in FIG. 4, transistors may be used as the first load circuit and the second load circuit. In the example of FIG. 4, a diode-connected N-type MOS transistor Q11 is provided instead of the resistor R1, and a diode-connected N-type MOS transistor Q12 is provided instead of the resistor R2.

  In the above-described embodiment, a circuit that operates with a DC voltage is cited as an example of the common mode feedback unit 30, but the present invention is not limited to this. In another embodiment of the present invention, a circuit for controlling the common mode voltage using a switched capacitor may be provided.

DESCRIPTION OF SYMBOLS 10 ... 1st amplification stage, 11 ... Constant current source, 20 ... 2nd amplification stage 20, 21 ... 1st differential amplification part, 22 ... 2nd differential amplification part, 30 ... Common mode feedback part, 40 ... Reference voltage Generator, Q1 ... first transistor, Q2 ... second transistor, Q3 ... third transistor, Q4 ... fourth transistor, Q5 ... fifth transistor, Q6 ... sixth transistor, Q7 ... seventh transistor, Q8 ... eighth transistor Q9: Ninth transistor, Q10: Tenth transistor, R1, R2: Resistance, Cc: Output capacitor.

Claims (7)

A first amplification stage including a pair of first and second transistors constituting a differential pair, and amplifying a differential signal input to the differential pair;
A second amplification stage for further amplifying the differential signal amplified in the first amplification stage;
An output capacitor connected to the output of the second amplification stage;
The amplifier circuit, wherein the lowest pole frequency in the transfer function is a pole frequency resulting from the output resistance of the second amplification stage and the capacitance of the output capacitor. The first amplification stage includes:
A constant current source provided in a current path between a common connection node of the pair of first and second transistors and a first power supply line;
A first load circuit provided in a current path between the first transistor and a second power supply line;
A second load circuit provided in a current path between the second transistor and the second power supply line,
2. The amplifier circuit according to claim 1, wherein the second amplification stage amplifies a difference between a voltage generated in the first load circuit and a voltage generated in the second load circuit. The amplifier circuit according to claim 2, wherein each of the first load circuit and the second load circuit is a resistance element. The second amplification stage includes
A third transistor provided in a current path between the first node and the second power supply line and controlling a current according to a voltage generated in the first load circuit;
A fourth transistor provided in a current path between a second node and the second power supply line and controlling a current according to a voltage generated in the second load circuit;
A fifth transistor provided in a current path between the first node and the first power supply line, through which a current corresponding to a first bias voltage flows;
A sixth transistor which is provided in a current path between the second node and the first power supply line and through which a current corresponding to the first bias voltage flows;
A seventh transistor provided as a current buffer with a high output resistance in a current path between the third transistor and the first node;
An eighth transistor provided as a current buffer with a high output resistance in a current path between the fourth transistor and the second node;
A ninth transistor provided as a high output resistance current buffer in a current path between the fifth transistor and the first node;
A tenth transistor provided as a high output resistance current buffer in a current path between the sixth transistor and the second node;
The amplifier circuit according to claim 2, wherein the output capacitor is connected to at least one of the first node and the second node. Amplifying a difference between a voltage at a connection node between the third transistor and the seventh transistor and a voltage at a connection node between the fourth transistor and the eighth transistor, and calculating the amplified result as a control voltage of the seventh transistor; The amplifier circuit according to claim 4, further comprising a first differential amplifier that outputs a differential voltage with respect to a control voltage of the eighth transistor. Amplifying a difference between a voltage at a connection node between the fifth transistor and the ninth transistor and a voltage at a connection node between the sixth transistor and the tenth transistor, and calculating the amplified result as a control voltage of the ninth transistor The amplifier circuit according to claim 4, further comprising: a second differential amplifier that outputs a differential voltage with respect to a control voltage of the tenth transistor. The constant current source is configured such that an intermediate voltage between a voltage at a connection node between the first transistor and the first load circuit and a voltage at a connection node between the second transistor and the second load circuit approaches a predetermined voltage. The amplifier circuit according to claim 1, further comprising a common mode feedback unit that controls current.