CN102789256A - Low-pressure-difference linear stabilizer - Google Patents
Low-pressure-difference linear stabilizer Download PDFInfo
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- CN102789256A CN102789256A CN2012103127518A CN201210312751A CN102789256A CN 102789256 A CN102789256 A CN 102789256A CN 2012103127518 A CN2012103127518 A CN 2012103127518A CN 201210312751 A CN201210312751 A CN 201210312751A CN 102789256 A CN102789256 A CN 102789256A
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Abstract
A low-pressure-difference linear stabilizer comprises an error amplifier, a buffer, a first bypass P-type MOS (metal oxide semiconductor) transistor, a first resistor, a second resistor, a series resistor, a series capacitor and a voltage conversion rate increasing circuit. An output end of the error amplifier is connected to an input end of the buffer BF, an output end of the buffer BF is connected to a grid of the first bypass P-type MOS transistor, and a drain of the first bypass P-type MOS transistor serves as an output end of the low-pressure-difference linear stabilizer. The voltage conversion rate increasing circuit comprises a second bypass P-type MOS transistor, a first attachment NMOS (n-channel metal oxide semiconductor) transistor, a second attachment PMOS (p-channel metal oxide semiconductor) transistor, a third attachment PMOS transistor, a third attachment NMOS transistor, a second attachment NMOS transistor and a second current source. By the aid of the low-pressure-difference linear stabilizer, voltage conversion rate can be effectively increased without increasing power consumption. Therefore, the low-pressure-difference linear stabilizer is particularly applicable to low-power-consumption applications with the requirement on quick current load response.
Description
Technical field
The present invention relates to the semiconductor circuit design field, more particularly, the present invention relates to a kind of low pressure difference linear voltage regulator.
Background technology
Low pressure difference linear voltage regulator LDO (low dropout regulator) is a kind of power conversion chip with respect to traditional linear voltage regulator.Traditional linear voltage regulator all requires input voltage to want specific output voltage to exceed more than 2v～3V, otherwise with regard to cisco unity malfunction.But in some cases, can't satisfy input voltage and want specific output voltage to exceed requirement such more than 2v～3V, for example the situation of the output of 3.3v is changeed in the input of 5v, and input has only 1.7v with the pressure reduction of exporting, and does not obviously satisfy condition.To this situation, the power conversion chip of low pressure difference linear voltage regulator LDO class has been proposed.
Fig. 1 schematically shows the block diagram according to the low pressure difference linear voltage regulator of prior art.
As shown in Figure 1, comprise according to the low pressure difference linear voltage regulator of prior art: error amplifier EA, impact damper BF, the first bypass P type MOS transistor Mp1, first resistor R 1, second resistor R 2, resistors in series ESR and series capacitor CL.
Wherein, The output terminal of said error amplifier EA is connected to the input end of said impact damper BF; The output terminal of said impact damper BF is connected to the grid of the said first bypass P type MOS transistor Mp1; The source electrode of the said first bypass P type MOS transistor Mp1 is connected to supply voltage; The drain electrode of the said first bypass P type MOS transistor Mp1 is as the output terminal VOUT of said low pressure difference linear voltage regulator; And the drain electrode of the said first bypass P type MOS transistor Mp1 is connected to first end of said first resistor R 1 and is connected to first end of said resistors in series ESR, and second end of said first resistor R 1 is connected to first end of said second resistor R 2 and is connected to the input end of said error amplifier EA, and second end of said resistors in series ESR is connected to first end of said series capacitor CL; The equal ground connection of second end of second end of said second resistor R 2 and second resistor R 2.
Wherein, said error amplifier EA comprises: the first current source A1, a PMOS transistor M1, the 2nd PMOS transistor M2, the 3rd nmos pass transistor M3 and the 4th nmos pass transistor M4.Wherein, The output terminal of the said first current source A1 is connected to the source electrode of a said PMOS transistor M1 and the source electrode of said the 2nd PMOS transistor M2; The grid of a said PMOS transistor M1 is as the input end of said error amplifier EA; The grid input reference voltage VREF of said the 2nd PMOS transistor M2; The drain electrode of a said PMOS transistor M1 is connected to the source electrode of said the 3rd nmos pass transistor M3, and the drain electrode of said the 2nd PMOS transistor M2 is connected to the source electrode of said the 4th nmos pass transistor M4, the grid that is connected to said the 3rd nmos pass transistor M3 of a said PMOS transistor M1 and the grid of said the 4th nmos pass transistor M4.The source ground of the source electrode of said the 3rd nmos pass transistor M3 and said the 4th nmos pass transistor M4.
For traditional low pressure difference linear voltage regulator, because power consumption, the voltage conversioning rate of impact damper BF is not high.According to for traditional low pressure difference linear voltage regulator,, must increase the electric current of impact damper, thereby cause bigger power consumption if realize bigger voltage conversioning rate.Wherein voltage conversioning rate (Slew Rate is abbreviated as SR) is called for short slew rate, and its definition is the amplitude that voltage raises in 1 microsecond or 1 nanosecond equal time, in other words is that square-wave voltage is raised to the crest required time by trough.
And along with the requirement to the higher voltage conversioning rate of low pressure difference linear voltage regulator, expectation can provide a kind of low pressure difference linear voltage regulator that under the situation that does not increase power consumption, improves voltage conversioning rate.
Summary of the invention
Technical matters to be solved by this invention is to have above-mentioned defective in the prior art, and a kind of low pressure difference linear voltage regulator that can under the situation that does not increase power consumption, improve voltage conversioning rate is provided.
In order to realize above-mentioned technical purpose; The present invention proposes a kind of low pressure difference linear voltage regulator, and it comprises: error amplifier, impact damper, the first bypass P type MOS transistor, first resistor, second resistor, resistors in series, series capacitor and voltage conversioning rate promote circuit; Wherein, The output terminal of said error amplifier is connected to the input end of said impact damper BF; The output terminal of said impact damper BF is connected to the grid of the said first bypass P type MOS transistor; The source electrode of the said first bypass P type MOS transistor is connected to supply voltage; The drain electrode of the said first bypass P type MOS transistor is as the output terminal of said low pressure difference linear voltage regulator; And the drain electrode of the said first bypass P type MOS transistor is connected to first end of said first resistor and is connected to first end of said resistors in series, and second end of said first resistor is connected to first end of said second resistor and is connected to the input end of said error amplifier, and second end of said resistors in series ESR is connected to first end of said series capacitor; The equal ground connection of second end of second end of said second resistor and second resistor; Wherein, said voltage conversioning rate lifting circuit comprises: the second bypass P type MOS transistor, the first additional nmos pass transistor, the second additional PMOS transistor, the 3rd additional PMOS transistor, the 3rd additional nmos pass transistor, second add the nmos pass transistor and second current source; Wherein, the source electrode of the said second bypass P type MOS transistor is connected to the source electrode and the drain electrode of the said first bypass P type MOS transistor respectively with draining; The said the 3rd additional transistorized source electrode of PMOS and grid are connected to the source electrode and the grid of the said second bypass P type MOS transistor respectively; The said the 3rd additional PMOS transistor drain is connected to the drain electrode of the said the 3rd additional nmos pass transistor; The grid of the said the 3rd additional nmos pass transistor is connected to the drain electrode of the output terminal and the said first additional nmos pass transistor of said second current source; The source electrode of the said the 3rd additional nmos pass transistor is connected to the said second additional PMOS transistor drain; The said second additional PMOS transistor connects bias voltage, the said second additional transistorized source electrode of PMOS and the said second additional transistorized source ground of PMOS.
Preferably, said error amplifier comprises: first current source, a PMOS transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor; Wherein, The output terminal of said first current source is connected to transistorized source electrode of a said PMOS and the transistorized source electrode of said the 2nd PMOS; The transistorized grid of a said PMOS is as the input end of said error amplifier; The transistorized grid input reference voltage of said the 2nd PMOS; A said PMOS transistor drain is connected to the source electrode of said the 3rd nmos pass transistor; Said the 2nd PMOS transistor drain is connected to the source electrode of said the 4th nmos pass transistor, the transistorized grid of said the 3rd nmos pass transistor and the grid of said the 4th nmos pass transistor, the source ground of the source electrode of said the 3rd nmos pass transistor and said the 4th nmos pass transistor of being connected to of a said PMOS.
Preferably, said low pressure difference linear voltage regulator is used for the low-power consumption application.
Preferably, said reference voltage is to be provided with according to the incoming level of the expectation of the applied circuit of low pressure difference linear voltage regulator of the said embodiment of the invention and the difference of output level.
Preferably, said bias voltage is that physical features according to the said second additional PMOS transistor Ms2 is provided with.
Can improve voltage conversioning rate effectively and not increase power consumption according to low pressure difference linear voltage regulator of the present invention, thus, low pressure difference linear voltage regulator according to the present invention is particularly useful for the application that requires the fast current load response of low-power consumption.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the block diagram according to the low pressure difference linear voltage regulator of prior art.
Fig. 2 schematically shows the block diagram according to the low pressure difference linear voltage regulator of the embodiment of the invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
Fig. 2 schematically shows the block diagram according to the low pressure difference linear voltage regulator of the embodiment of the invention.
As shown in Figure 2, comprise according to the low pressure difference linear voltage regulator of the embodiment of the invention: error amplifier EA, impact damper BF, the first bypass P type MOS transistor Mp1, first resistor R 1, second resistor R 2, resistors in series ESR, series capacitor CL and voltage conversioning rate promote circuit (shown in the frame of broken lines of Fig. 2).
Wherein, The output terminal of said error amplifier EA is connected to the input end of said impact damper BF; The output terminal of said impact damper BF is connected to the grid of the said first bypass P type MOS transistor Mp1; The source electrode of the said first bypass P type MOS transistor Mp1 is connected to supply voltage; The drain electrode of the said first bypass P type MOS transistor Mp1 is as the output terminal VOUT of said low pressure difference linear voltage regulator; And the drain electrode of the said first bypass P type MOS transistor Mp1 is connected to first end of said first resistor R 1 and is connected to first end of said resistors in series ESR, and second end of said first resistor R 1 is connected to first end of said second resistor R 2 and is connected to the input end of said error amplifier EA, and second end of said resistors in series ESR is connected to first end of said series capacitor CL; The equal ground connection of second end of second end of said second resistor R 2 and second resistor R 2.
Wherein, said voltage conversioning rate lifting circuit comprises: the second bypass P type MOS transistor Mp2, the first additional nmos pass transistor Ms1, the second additional PMOS transistor Ms2, the 3rd additional PMOS transistor Ms3, the 3rd additional nmos pass transistor Msw, second add the nmos pass transistor Ms2 and the second current source A2.Wherein, the source electrode of the said second bypass P type MOS transistor Mp2 is connected to source electrode and the drain electrode of the said first bypass P type MOS transistor Mp1 respectively with draining; The source electrode of the said the 3rd additional PMOS transistor Ms3 and source electrode and the grid that grid is connected to the said second bypass P type MOS transistor Mp2 respectively; The drain electrode of the said the 3rd additional PMOS transistor Ms3 is connected to the drain electrode of the said the 3rd additional nmos pass transistor Msw; The grid of the said the 3rd additional nmos pass transistor Msw is connected to the drain electrode of the output terminal and the said first additional nmos pass transistor Ms1 of the said second current source A2; The source electrode of the said the 3rd additional nmos pass transistor Msw is connected to the drain electrode of the said second additional PMOS transistor Ms2; The said second additional PMOS transistor Ms2 (for example meets bias voltage vb; Can bias voltage vb be set according to the physical features of the said second additional PMOS transistor Ms2, for example, can bias voltage vb be set to the threshold voltage of the said second additional PMOS transistor Ms2; Such as 0.7V), the source ground of the source electrode of the said second additional PMOS transistor Ms2 and the said second additional PMOS transistor Ms2.
Wherein, said error amplifier EA comprises: the first current source A1, a PMOS transistor M1, the 2nd PMOS transistor M2, the 3rd nmos pass transistor M3 and the 4th nmos pass transistor M4.Wherein, The output terminal of the said first current source A1 is connected to the source electrode of a said PMOS transistor M1 and the source electrode of said the 2nd PMOS transistor M2; The grid of a said PMOS transistor M1 is as the input end of said error amplifier EA; The grid input reference voltage VREF of said the 2nd PMOS transistor M2 (for example; Can reference voltage VREF be set according to the incoming level of the expectation of the applied circuit of low pressure difference linear voltage regulator of the embodiment of the invention and the extent of output level; Incoming level and output level poor of expectation that for example can reference voltage VREF be set to the applied circuit of low pressure difference linear voltage regulator of the embodiment of the invention; Such as 2-3V); The drain electrode of a said PMOS transistor M1 is connected to the source electrode of said the 3rd nmos pass transistor M3, and the drain electrode of said the 2nd PMOS transistor M2 is connected to the source electrode of said the 4th nmos pass transistor M4, the grid that is connected to said the 3rd nmos pass transistor M3 of a said PMOS transistor M1 and the grid of said the 4th nmos pass transistor M4.The source ground of the source electrode of said the 3rd nmos pass transistor M3 and said the 4th nmos pass transistor M4.
Operation according to the low pressure difference linear voltage regulator of the embodiment of the invention will be described below.
If current load current is lower; Then the output terminal VOUT according to the low pressure difference linear voltage regulator of the embodiment of the invention is under the normal voltage level; The level of node A can be too not low; The said the 3rd additional nmos pass transistor Msw is by (not conducting), thereby the said the 3rd additional PMOS transistor Ms3 and the said second bypass P type MOS transistor Mp2 end (not conducting), only said first bypass P type MOS transistor Mp1 work.
But, when load current increases suddenly, lower according to the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the invention level that becomes.Generally, the response of error amplifier EA is very fast, thus the quick step-down of the level of node A.Lower node A makes the said the 3rd to add nmos pass transistor Msw conducting, thus the said the 3rd additional PMOS transistor Ms3 and the said second bypass P type MOS transistor Mp2 conducting.Thus, more electric current can be provided according to the low pressure difference linear voltage regulator of the embodiment of the invention, and can be too not low according to the level of the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the invention.After experience a period of time; After error amplifier EA, impact damper BF and the said first bypass P type MOS transistor Mp1 have carried out response; Level according to the output terminal VOUT of the low pressure difference linear voltage regulator of the embodiment of the invention is got back to normal voltage level; Node A level uprises; The said subsequently the 3rd additional nmos pass transistor Msw is by (not conducting), thereby the said the 3rd additional PMOS transistor Ms3 and the said second bypass P type MOS transistor Mp2 end (not conducting), and feasible low pressure difference linear voltage regulator according to the embodiment of the invention gets into low power consumpting state.
Low pressure difference linear voltage regulator according to the embodiment of the invention can improve voltage conversioning rate effectively and not increase power consumption, thus, is particularly useful for the application that requires the fast current load response of low-power consumption according to the low pressure difference linear voltage regulator of the embodiment of the invention.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection domain of technical scheme of the present invention according to technical spirit of the present invention.
Claims (5)
1. a low pressure difference linear voltage regulator is characterized in that comprising: error amplifier, impact damper, the first bypass P type MOS transistor, first resistor, second resistor, resistors in series, series capacitor and voltage conversioning rate lifting circuit;
Wherein, The output terminal of said error amplifier is connected to the input end of said impact damper BF; The output terminal of said impact damper BF is connected to the grid of the said first bypass P type MOS transistor; The source electrode of the said first bypass P type MOS transistor is connected to supply voltage; The drain electrode of the said first bypass P type MOS transistor is as the output terminal of said low pressure difference linear voltage regulator; And the drain electrode of the said first bypass P type MOS transistor is connected to first end of said first resistor and is connected to first end of said resistors in series, and second end of said first resistor is connected to first end of said second resistor and is connected to the input end of said error amplifier, and second end of said resistors in series ESR is connected to first end of said series capacitor; The equal ground connection of second end of second end of said second resistor and second resistor;
Wherein, said voltage conversioning rate lifting circuit comprises: the second bypass P type MOS transistor, the first additional nmos pass transistor, the second additional PMOS transistor, the 3rd additional PMOS transistor, the 3rd additional nmos pass transistor, second add the nmos pass transistor and second current source; Wherein, the source electrode of the said second bypass P type MOS transistor is connected to the source electrode and the drain electrode of the said first bypass P type MOS transistor respectively with draining; The said the 3rd additional transistorized source electrode of PMOS and grid are connected to the source electrode and the grid of the said second bypass P type MOS transistor respectively; The said the 3rd additional PMOS transistor drain is connected to the drain electrode of the said the 3rd additional nmos pass transistor; The grid of the said the 3rd additional nmos pass transistor is connected to the drain electrode of the output terminal and the said first additional nmos pass transistor of said second current source; The source electrode of the said the 3rd additional nmos pass transistor is connected to the said second additional PMOS transistor drain; The said second additional PMOS transistor connects bias voltage, the said second additional transistorized source electrode of PMOS and the said second additional transistorized source ground of PMOS.
2. low pressure difference linear voltage regulator as claimed in claim 1 is characterized in that, said error amplifier comprises: first current source, a PMOS transistor, the 2nd PMOS transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor; Wherein, The output terminal of said first current source is connected to transistorized source electrode of a said PMOS and the transistorized source electrode of said the 2nd PMOS; The transistorized grid of a said PMOS is as the input end of said error amplifier; The transistorized grid input reference voltage of said the 2nd PMOS; A said PMOS transistor drain is connected to the source electrode of said the 3rd nmos pass transistor; Said the 2nd PMOS transistor drain is connected to the source electrode of said the 4th nmos pass transistor, the transistorized grid of said the 3rd nmos pass transistor and the grid of said the 4th nmos pass transistor, the source ground of the source electrode of said the 3rd nmos pass transistor and said the 4th nmos pass transistor of being connected to of a said PMOS.
3. according to claim 1 or claim 2 low pressure difference linear voltage regulator is characterized in that, said low pressure difference linear voltage regulator is used for low-power consumption and uses.
4. according to claim 1 or claim 2 low pressure difference linear voltage regulator is characterized in that said reference voltage is to be provided with according to the incoming level of the expectation of the applied circuit of low pressure difference linear voltage regulator of the said embodiment of the invention and the difference of output level.
5. according to claim 1 or claim 2 low pressure difference linear voltage regulator is characterized in that, said bias voltage is that the physical features according to the said second additional PMOS transistor Ms2 is provided with.
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| CN201210312751.8A CN102789256B (en) | 2012-08-29 | 2012-08-29 | Low pressure difference linear voltage regulator |
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| CN201210312751.8A CN102789256B (en) | 2012-08-29 | 2012-08-29 | Low pressure difference linear voltage regulator |
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| CN102789256A true CN102789256A (en) | 2012-11-21 |
| CN102789256B CN102789256B (en) | 2016-03-23 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107241068A (en) * | 2016-03-28 | 2017-10-10 | 立积电子股份有限公司 | Amplifier |
| CN114460994A (en) * | 2020-11-09 | 2022-05-10 | 扬智科技股份有限公司 | Voltage regulator |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2120123A1 (en) * | 2008-05-12 | 2009-11-18 | Stmicroelectronics SA | Slew rate control |
| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
-
2012
- 2012-08-29 CN CN201210312751.8A patent/CN102789256B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2120123A1 (en) * | 2008-05-12 | 2009-11-18 | Stmicroelectronics SA | Slew rate control |
| CN102279612A (en) * | 2011-05-11 | 2011-12-14 | 电子科技大学 | Low dropout linear regulator |
| CN102331807A (en) * | 2011-09-30 | 2012-01-25 | 电子科技大学 | Low-dropout (LDO) linear regulator of integrated slew rate enhancing circuit |
| CN102385410A (en) * | 2011-11-22 | 2012-03-21 | 电子科技大学 | Slew-rate enhancement circuit and LDO integrating same |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107241068A (en) * | 2016-03-28 | 2017-10-10 | 立积电子股份有限公司 | Amplifier |
| CN114460994A (en) * | 2020-11-09 | 2022-05-10 | 扬智科技股份有限公司 | Voltage regulator |
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| CN102789256B (en) | 2016-03-23 |
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