CN103472880A - Low dropout regulator - Google Patents

Abstract

The invention relates to the power supply circuit technology, in particular to a low dropout regulator (LDO) capable of quick response. Grids of power tubes are driven by an OTA high in pendulum rate, and a pendulum-rate enhancement circuit is adopted to quicken potential changes of the grids of the power tubes, so that when output voltage jumps, the grids of the power tubes can be supplied with large charging and discharging currents in very short period of time, grid voltage of the power tubes is allowed to change rapidly, the shortcoming of low pendulum rate due to large parasitic capacitance of the grids of the power tubes is greatly overcome, the pendulum rate of the LDO is greatly increased, and output voltage spikes are reduced. The low dropout regulator has the advantages that a circuit structure is simple; by the adoption of the on-chip integration technology, large off-chip load capacitance is no longer needed, and cost of peripheral application of a system is lowered.

Description

A kind of low pressure difference linear voltage regulator

Technical field

The present invention relates to the power circuit technology, relate to specifically a kind of quick response low pressure difference linear voltage regulator (Low Dropout Regulator, LDO).

Background technology

Low pressure difference linear voltage regulator is the element of on-chip power supply system, because its cost is low, output noise is little, circuit structure is simple, chip occupying area is little and the advantage such as low-power consumption, be widely used in the radio communication occasion as in the power-supply management systems such as mobile phone, notebook computer.

Traditional low pressure difference linear voltage regulator, in order to meet the system stability requirement, needs to connect a large load capacitance outside the sheet of LDO, can increase like this sheet external component number, has increased the application cost of system simultaneously, and is not suitable for the integrated systems such as OSC.In order to overcome this problem, at present, more and more studied without the outer large electric capacity low pressure difference linear voltage regulator of sheet, for stronger carrying load ability is arranged, in general LDO, the area of power tube is larger, grid at power tube forms the electric capacity up to tens of pF, simultaneously in order to reduce the power consumption of LDO, static working current is very little, make the Slew Rate of LDO very little, it is slower that thereby the grid voltage of power tube changes, cause the drain current of power tube also to change slowly thereupon, when the output current saltus step, output voltage need to be longer recovery stabilization time, and can produce large due to voltage spikes.In order to increase the Slew Rate without the outer large electric capacity LDO of sheet, some LDO are by adopting complicated structure to come the increasing power tube grid to discharge and recharge speed, although optimized to a certain extent the spike situation of output voltage, but complex structure, and upper punch due to voltage spikes and undershoot due to voltage spikes are still larger, therefore traditional technology can not be applied to high-precision application scenario.

Summary of the invention

To be solved by this invention, be exactly for the problems referred to above, a kind of quick response low pressure difference linear voltage regulator is proposed.

The present invention solves the problems of the technologies described above adopted technical scheme: a kind of low pressure difference linear voltage regulator, it is characterized in that, and comprise a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 13 PMOS pipe MP13, power tube PMOS MP, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 18 NMOS pipe MN18, the 19 NMOS pipe MN19, resistance R M and capacitor C M,

The drain electrode of the drain electrode of the drain electrode of the source electrode of the source electrode of the source electrode of the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the tenth PMOS pipe MP10, the source electrode of power tube PMOS MP, a NMOS pipe MN1, the drain electrode of the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the drain electrode of the 4th NMOS pipe MN4, the 16 NMOS pipe MN16 is connected power vd D with the drain electrode of the 17 NMOS pipe MN17;

The grid of the grid of the one NMOS pipe MN1, the 2nd NMOS pipe MN2 is connected input reference voltage VREF with the grid of the 17 NMOS pipe MN17;

The source electrode of the one NMOS pipe MN1 connects the source electrode of a PMOS pipe MP1, and the grid of a PMOS pipe MP1 is connected the grid of the 2nd PMOS pipe MP2, the drain electrode of the 6th NMOS pipe MN6 and the drain electrode of the 7th NMOS pipe MN7 with drain electrode;

The source electrode of the 2nd NMOS pipe MN2 connects the source electrode of the 3rd PMOS pipe MP3, and the source electrode of the 3rd NMOS pipe MN3 connects the source electrode of the 2nd PMOS pipe MP2, and the drain electrode of the 2nd PMOS pipe MP2 connects the drain and gate of the 8th NMOS pipe MN8 and the grid of the 5th NMOS pipe MN5;

The grid of the 3rd PMOS pipe MP3 connects grid and drain electrode, the drain electrode of the tenth NMOS pipe MN10 and the drain electrode of the 11 NMOS pipe MN11 of the 4th PMOS pipe MP4, and the source electrode of the 4th PMOS pipe MP4 connects the source electrode of the 4th NMOS pipe MN4;

The drain electrode of the 3rd PMOS pipe MP3 connects the drain and gate of the 9th NMOS pipe MN9, the grid of the 12 NMOS pipe MN12, the drain electrode that the grid of the drain electrode of drain electrode connection the 6th PMOS pipe MP6 of the 12 NMOS pipe MN12, the end of capacitor C M, power tube PMOS MP, the grid that the tenth PMOS manages MP10 and the 14 NMOS manage MN14, the grid of grid connection the 5th PMOS pipe MP5 of the 6th PMOS pipe MP6 is managed the drain electrode of MN5 with draining with the 5th NMOS;

The grid of the 6th NMOS pipe MN6 connect the grid of the 11 NMOS pipe MN11, the grid of the 13 NMOS pipe MN13 and the drain electrode that drain electrode, the tenth PMOS manage MP10;

The grid of the grid of the grid of the 7th NMOS pipe MN7, the tenth NMOS pipe MN10, the 18 NMOS pipe MN18 is connected input offset voltage VB with the grid of the 19 NMOS pipe MN19;

The end of the other end of capacitor C M and resistance R M is connected, and the tie point of the source electrode of the drain electrode of the grid connection power tube PMOS MP of the grid of the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the other end of resistance R M and the 7th PMOS pipe MP7 is made output terminal VOUT;

The grid of the 7th PMOS pipe MP7 is connected with the source electrode of the 8th PMOS pipe MP8 with drain electrode, and the grid of the 8th PMOS pipe MP8 is connected with the source electrode of the 9th PMOS pipe MP9 with drain electrode;

The grid of the 14 NMOS pipe MN14 connects the grid of the 15 NMOS pipe MN15 and the drain electrode that drain electrode, the 11 PMOS manage MP11, and the grid of the 11 PMOS pipe MP11 connects the drain electrode of the 12 PMOS pipe MP12 and the drain electrode of the 18 NMOS pipe MN18;

The grid of the 12 PMOS pipe MP12 connects the grid of the 13 PMOS pipe MP13 and the drain electrode that drain electrode, the 19 NMOS manage MN19, and the source electrode of the 12 PMOS pipe MP12 connects the source electrode of the 16 NMOS pipe MN16;

The source electrode of the 11 PMOS pipe MP11 connects the source electrode of the 13 PMOS pipe MP13 and the source electrode of the 17 NMOS pipe MN17;

Grid and the drain electrode of the 9th PMOS pipe MP9, the source electrode of the 5th NMOS pipe MN5, the source electrode of the 6th NMOS pipe MN6, the source electrode of the 7th NMOS pipe MN7, the source electrode of the 8th NMOS pipe MN8, the source electrode of the 9th NMOS pipe MN9, the source electrode of the tenth NMOS pipe MN10, the source electrode of the 11 NMOS pipe MN11, the source electrode of the 12 NMOS pipe MN12, the source electrode of the 13 NMOS pipe MN13, the source electrode of the 14 NMOS pipe MN14, the source electrode of the 15 NMOS pipe MN15, the source electrode of the 18 NMOS pipe MN18, the source grounding current potential VSS of the 19 NMOS pipe MN19.

Beneficial effect of the present invention is, with existing LDO, compare, adopt the grid of the OTA driving power pipe of high Slew Rate, and adopt slew rate enhancing circuit to accelerate the potential change of power tube grid, thereby when output voltage generation saltus step, can within the extremely short time, provide large charging and discharging electric current by the grid for power tube, make the gate voltage of power tube can access variation fast, overcome greatly the little problem of Slew Rate that the large electric capacity due to power tube grid parasitism causes, thereby greatly improved the Slew Rate of LDO circuit, reduced the output voltage point, simultaneously, circuit structure of the present invention is simple, and integrated technology on the employing sheet, no longer need the outer load capacitance of large sheet, reduced the system peripherals application cost.

The accompanying drawing explanation

Fig. 1 is low differential voltage linear voltage stabilizer circuit topological structure schematic diagram of the present invention;

Simulation waveform schematic diagram when Fig. 2 is LDO load current generation saltus step of the present invention.

Embodiment

Below in conjunction with accompanying drawing, describe technical scheme of the present invention in detail:

As shown in Figure 1, a kind of low pressure difference linear voltage regulator that the present invention proposes, comprise a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 13 PMOS pipe MP13, power tube PMOS MP, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 18 NMOS pipe MN18, the 19 NMOS pipe MN19, resistance R M and capacitor C M.

For convenient narration, hereinafter a PMOS manages MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 13 PMOS pipe MP13, power tube PMOS MP is successively with MP1, MP2, MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP substitutes, a NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 18 NMOS pipe MN18, the 19 NMOS pipe MN19 is successively with MN1, MN2, MN3, MN4, MN5, MN6, MN7, MN8, MN9, MN10, MN11, MN12, MN13, MN14, MN15, MN16, MN17, MN18, MN19 substitutes.

Wherein, the grid of NMOS pipe MN1, MN2, MN17 is connected to input reference voltage VREF, and the drain electrode of MN1 connects supply voltage VDD, and source electrode connects the source electrode of MP1; The grid of MP1 with drain electrode, the be connected grid that is connected to MP2 and the drain electrode of MN6 and MN7; The drain electrode of the grid of the grid connection MN11 of MN6 and the grid of MN13 and drain electrode, MP10, the grid of the grid of MN7 and the grid of MN10, MN18, the grid of MN19 are connected and are connected to input offset voltage VB, and the source electrode of MN6 and MN7, MN13 all is connected earth potential VSS; The drain electrode of MP2 connects the grid of MN8 and the grid of drain electrode and MN5, and source electrode connects the source electrode of MN3, and the source electrode of MN8 connects earth potential VSS; The grid of MN3 is connected as the output voltage VO UT of LDO with the grid of the grid of MN4, MN16, the source electrode of MP7, the drain electrode of MP and the end of resistance R M, and the drain electrode of MN3 connects supply voltage VDD; The drain electrode of MN4 connects supply voltage VDD, and source electrode connects the source electrode of MP4; The grid of MP4 and the grid that is connected to MP3, the drain electrode of MN10, the drain electrode of MN11 of being connected that drain, the source electrode of MN10 and MN11 all is connected earth potential VSS; The source electrode of MP3 connects the source electrode of MN2, and drain electrode connects the drain and gate of MN9 and the grid of MN12, and the source electrode of MN9 connects earth potential VSS, and the drain electrode of MN2 connects supply voltage VDD; The drain electrode of MN5 connects the grid of MP5 and the grid of drain electrode and MP6, and source electrode connects earth potential VSS, and the source electrode of MP5 all is connected supply voltage VDD with the source electrode of MP6; The drain electrode of MP12 connects drain electrode, the grid of MP, the grid of MP10, the drain electrode of MN14 and the end of capacitor C M of MP6, and the source electrode of MP12 connects earth potential VSS; The other end of the other end contact resistance RM of capacitor C M, the source electrode of MP and MP10 all is connected supply voltage VDD; The grid of MP7 is connected and is connected to the source electrode of MP8 with drain electrode, and the grid of MP8 is connected and is connected to the source electrode of MP9 with drain electrode, and the grid of MP9 is connected and is connected to earth potential VSS with drain electrode; The grid of MN14 connects the grid of MN15 and the drain electrode of drain electrode and MP11, and the source electrode of MN14 and MN15 all is connected earth potential VSS; The grid of MP11 connects the drain electrode of MP12 and the drain electrode of MN18, and source electrode connects the source electrode of MN17 and the source electrode of MP13, and the source electrode of MN18 connects earth potential VSS; The grid of MP12 connects the grid of MP13 and the drain electrode of drain electrode and MN19, and source electrode connects the source electrode of MN16; The drain electrode of MN16 and MN17 all is connected supply voltage VDD, and the source electrode of MN19 connects earth potential VSS.

Principle of work of the present invention is:

NMOS pipe MN1～MN12 and PMOS pipe MP1～MP9 and power tube MP, resistance R M, capacitor C M form LDO core circuit of the present invention, and MP10 and MN13 form the output current sample circuit, and MP11～MP13 and MN13～MN19 forms LDO undershoot slew rate enhancing circuit.OTA amplifier in quick response low pressure difference linear voltage regulator proposed by the invention adopts the cross coupled amplifier structure, this structure is when steady state (SS), power consumption is lower, and when output voltage generation saltus step, this OTA amplifier can be exported larger electric current, different from OTA in traditional LDO, this electric current no longer is subject to the restriction of tail current source, therefore can carry out charging and discharging fast to the grid of power tube, thereby improve the Slew Rate of LDO, the upper punch of output voltage and undershoot spike while reducing the load saltus step.In order more specifically this circuit to be described, in the time of below will with regard to output load, upper jumping and lower jumping occurring respectively, the process of the adjustment output voltage of LDO is set forth.

When output current jumps to heavy duty from underloading, because the grid voltage of power tube MP can not reduce in time, output voltage will produce the undershoot spike, and the electric current that now flows through MP2 can reduce, and the electric current decrease is

$\mathrm{\Δ}{I}_{\mathrm{MP}2}={\left(\frac{\mathrm{\Δ}{V}_{\mathrm{OUT}}}{V_{\mathrm{OVMP}2}}\right)}^{^2}{I}_{\mathrm{MP}2}$

Wherein, Δ V _oUTfor output voltage variable quantity, V _oVMP2for the overdrive voltage of MP2, I _mP2for flowing through the electric current of MP2.ErMN4Zhi road electric current is fixed, due to grid voltage step-down Δ V _oUT, the grid of MP4 reduces Δ V _oUTso the electric current that flows through MP3 increases, the electric current increase is

$\mathrm{\Δ}{I}_{\mathrm{MP}3}={\left(\frac{\mathrm{\Δ}{V}_{\mathrm{OUT}}}{V_{\mathrm{OVMP}3}}\right)}^{^2}{I}_{\mathrm{MP}3}$

Wherein, V _oVMP2for the overdrive voltage of MP2, I _mP2for flowing through the electric current of MP2.Due to I _mP2=I _mP3, and V _oVMP2=V _oVMP3so Δ I _mP2=Δ I _mP3, supposing the electric current M of MP6 mirror image MN5 doubly, doubly, the discharge current of power tube grid is 2M Δ I to the electric current M of MN12 mirror image MN9 _mP2, different from OTA in traditional LDO, this electric current is not limited to the size of current that bias current sources provides, and can greatly accelerate the velocity of discharge of power tube grid, and rapid adjustment outputs to stationary value, thereby reduces the undershoot spike of output voltage.

Equally, when output current jumps to underloading from heavy duty, because the grid voltage of power tube MP can not increase in time, output voltage will produce the upper punch spike, and the electric current that now flows through the MP2 pipe can increase, and the electric current that flows through the MP3 pipe can reduce, and current change quantity is

$\mathrm{\Δ}{I}_{\mathrm{MP}3}={\mathrm{\ΔI}}_{\mathrm{MP}2}={\left(\frac{\mathrm{\Δ}{V}_{\mathrm{OUT}}}{V_{\mathrm{OVMP}3}}\right)}^{^2}{I}_{\mathrm{MP}3}$

Now the charging current of power tube grid is 2M Δ I _mP2.Equally, this electric current is not limited to the size of current that bias current sources provides, and can greatly accelerate the electric speed of rushing of power tube grid, and rapid adjustment outputs to stationary value, thereby reduces the upper punch spike of output voltage.

The size of the current sampling circuit sampling output current that MP10 and MN13 pipe form, and this sample rate current is mirrored to the drain electrode of MP1 pipe and MP4 pipe, in underloading, on MN6 and MN11, electric current is almost 0, thereby this structure no current when underloading flows through, can not reduce the efficiency of LDO under underloading, during heavy duty, in MN6 and MN11, there is large electric current to flow through, thereby increase the mutual conductance of MN2, MN3, MP2, MP3, because the mutual conductance formula is

$g_m=\sqrt{{2I}_D{\mathrm{uC}}_{\mathrm{ox}}(W/L)}$

Wherein, I _dfor flowing through the drain terminal electric current of metal-oxide-semiconductor, u is the metal-oxide-semiconductor mobility, and Cox is metal-oxide-semiconductor unit area gate oxide electric capacity, and W/L is the metal-oxide-semiconductor breadth length ratio.Therefore the mutual conductance of MN2, MN3, MP2, MP3 increases identical multiple, thereby increases the size of charging and discharging currents, the Slew Rate while further improving heavy duty, and in addition due to the increase of the mutual conductance of MN2, MN3, MP2, MP3, bandwidth

also expand, response speed can accelerate thereupon.When heavy duty jumps to underloading, can reduce the upper punch spike of output voltage so.

When weight carries the jumping underloading, the diode type of attachment that output voltage rising spike will make MP7, MP8, MP9 form can cause MP7, MP8, the upper electric current of MP9 to increase rapidly, thereby output is discharged, and accelerates adjustment of load speed in addition.And this structure is when steady state (SS), and the electric current flow through is very little, can not increase the power consumption of LDO.

From top analysis, can see, when heavy duty jumps to underloading, there is number of mechanisms can accelerate adjustment of load speed, and underloading is while jumping to heavy duty, adjustment of load speed only has the loop of OTA own to be adjusted, and, because the electric current of MP2, MP3 when the transient response is less, the output current of OTA also can be very little, makes Slew Rate less.Adjustment of load speed during for further quickening underloading saltus step heavy duty, increased slew rate enhancing circuit in this LDO, when output voltage generation undershoot spike, the source voltage of MP12 reduces, thereby cause the grid voltage of MP11 pipe to reduce, therefore on MP11, there is large electric current to flow through, by mirror image, the MN14 pipe is discharged to the grid of power tube, thereby accelerated the response speed of underloading to heavily loaded saltus step.

Simulation waveform during load current saltus step that Fig. 2 is LDO proposed by the invention, electric current saltus step between 0.1mA and 100mA, Current rise and decline bound-time are 0.5us, the saltus step situation that upper figure is load current, the size that figure below is output voltage.Can see, upper punch is the 1uS left and right release time, upper punch size 190mV; Undershoot is the 1uS left and right release time, and the undershoot size is 150mV.

Claims (1)

1. a low pressure difference linear voltage regulator, it is characterized in that, comprise a PMOS pipe MP1, the 2nd PMOS pipe MP2, the 3rd PMOS pipe MP3, the 4th PMOS pipe MP4, the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the 7th PMOS pipe MP7, the 8th PMOS pipe MP8, the 9th PMOS pipe MP9, the tenth PMOS pipe MP10, the 11 PMOS pipe MP11, the 12 PMOS pipe MP12, the 13 PMOS pipe MP13, power tube PMOS MP, the one NMOS pipe MN1, the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the 5th NMOS pipe MN5, the 6th NMOS pipe MN6, the 7th NMOS pipe MN7, the 8th NMOS pipe MN8, the 9th NMOS pipe MN9, the tenth NMOS pipe MN10, the 11 NMOS pipe MN11, the 12 NMOS pipe MN12, the 13 NMOS pipe MN13, the 14 NMOS pipe MN14, the 15 NMOS pipe MN15, the 16 NMOS pipe MN16, the 17 NMOS pipe MN17, the 18 NMOS pipe MN18, the 19 NMOS pipe MN19, resistance R M and capacitor C M,

The drain electrode of the drain electrode of the drain electrode of the source electrode of the source electrode of the source electrode of the 5th PMOS pipe MP5, the 6th PMOS pipe MP6, the tenth PMOS pipe MP10, the source electrode of power tube PMOS MP, a NMOS pipe MN1, the drain electrode of the 2nd NMOS pipe MN2, the 3rd NMOS pipe MN3, the drain electrode of the 4th NMOS pipe MN4, the 16 NMOS pipe MN16 is connected power vd D with the drain electrode of the 17 NMOS pipe MN17;

The grid of the grid of the one NMOS pipe MN1, the 2nd NMOS pipe MN2 is connected input reference voltage VREF with the grid of the 17 NMOS pipe MN17;

The source electrode of the one NMOS pipe MN1 connects the source electrode of a PMOS pipe MP1, and the grid of a PMOS pipe MP1 is connected the grid of the 2nd PMOS pipe MP2, the drain electrode of the 6th NMOS pipe MN6 and the drain electrode of the 7th NMOS pipe MN7 with drain electrode;

The source electrode of the 2nd NMOS pipe MN2 connects the source electrode of the 3rd PMOS pipe MP3, and the source electrode of the 3rd NMOS pipe MN3 connects the source electrode of the 2nd PMOS pipe MP2, and the drain electrode of the 2nd PMOS pipe MP2 connects the drain and gate of the 8th NMOS pipe MN8 and the grid of the 5th NMOS pipe MN5;

The grid of the 3rd PMOS pipe MP3 connects grid and drain electrode, the drain electrode of the tenth NMOS pipe MN10 and the drain electrode of the 11 NMOS pipe MN11 of the 4th PMOS pipe MP4, and the source electrode of the 4th PMOS pipe MP4 connects the source electrode of the 4th NMOS pipe MN4;

The drain electrode of the 3rd PMOS pipe MP3 connects the drain and gate of the 9th NMOS pipe MN9, the grid of the 12 NMOS pipe MN12, the drain electrode that the grid of the drain electrode of drain electrode connection the 6th PMOS pipe MP6 of the 12 NMOS pipe MN12, the end of capacitor C M, power tube PMOS MP, the grid that the tenth PMOS manages MP10 and the 14 NMOS manage MN14, the grid of grid connection the 5th PMOS pipe MP5 of the 6th PMOS pipe MP6 is managed the drain electrode of MN5 with draining with the 5th NMOS;

The grid of the 6th NMOS pipe MN6 connect the grid of the 11 NMOS pipe MN11, the grid of the 13 NMOS pipe MN13 and the drain electrode that drain electrode, the tenth PMOS manage MP10;

The grid of the grid of the grid of the 7th NMOS pipe MN7, the tenth NMOS pipe MN10, the 18 NMOS pipe MN18 is connected input offset voltage VB with the grid of the 19 NMOS pipe MN19;

The end of the other end of capacitor C M and resistance R M is connected, and the tie point of the source electrode of the drain electrode of the grid connection power tube PMOS MP of the grid of the 3rd NMOS pipe MN3, the 4th NMOS pipe MN4, the other end of resistance R M and the 7th PMOS pipe MP7 is made output terminal VOUT;

The grid of the 7th PMOS pipe MP7 is connected with the source electrode of the 8th PMOS pipe MP8 with drain electrode, and the grid of the 8th PMOS pipe MP8 is connected with the source electrode of the 9th PMOS pipe MP9 with drain electrode;

The grid of the 14 NMOS pipe MN14 connects the grid of the 15 NMOS pipe MN15 and the drain electrode that drain electrode, the 11 PMOS manage MP11, and the grid of the 11 PMOS pipe MP11 connects the drain electrode of the 12 PMOS pipe MP12 and the drain electrode of the 18 NMOS pipe MN18;

The grid of the 12 PMOS pipe MP12 connects the grid of the 13 PMOS pipe MP13 and the drain electrode that drain electrode, the 19 NMOS manage MN19, and the source electrode of the 12 PMOS pipe MP12 connects the source electrode of the 16 NMOS pipe MN16;

The source electrode of the 11 PMOS pipe MP11 connects the source electrode of the 13 PMOS pipe MP13 and the source electrode of the 17 NMOS pipe MN17;

Grid and the drain electrode of the 9th PMOS pipe MP9, the source electrode of the 5th NMOS pipe MN5, the source electrode of the 6th NMOS pipe MN6, the source electrode of the 7th NMOS pipe MN7, the source electrode of the 8th NMOS pipe MN8, the source electrode of the 9th NMOS pipe MN9, the source electrode of the tenth NMOS pipe MN10, the source electrode of the 11 NMOS pipe MN11, the source electrode of the 12 NMOS pipe MN12, the source electrode of the 13 NMOS pipe MN13, the source electrode of the 14 NMOS pipe MN14, the source electrode of the 15 NMOS pipe MN15, the source electrode of the 18 NMOS pipe MN18, the source grounding current potential VSS of the 19 NMOS pipe MN19.

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