CN106125818A - A kind of power-supply circuit and control method thereof - Google Patents
A kind of power-supply circuit and control method thereof Download PDFInfo
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- CN106125818A CN106125818A CN201610716077.8A CN201610716077A CN106125818A CN 106125818 A CN106125818 A CN 106125818A CN 201610716077 A CN201610716077 A CN 201610716077A CN 106125818 A CN106125818 A CN 106125818A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/26—Current mirrors
- G05F3/262—Current mirrors using field-effect transistors only
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Abstract
The embodiment of the present invention provides the control method of a kind of power-supply circuit, power-supply circuit includes the first mu balanced circuit and the second mu balanced circuit, the load current of the first mu balanced circuit is more than the load current of the second mu balanced circuit, described method includes: when load is in normal mode of operation, the first mu balanced circuit provide supply voltage for load；When load is in low power mode of operation, the second mu balanced circuit provide supply voltage for load.Power supply is provided by different mu balanced circuits, it is ensured that loaded work piece is under preferably power consumption mode, and then reduces power consumption, and meanwhile, sub-module is designed and the considering of power consumption, and can improve design efficiency under different power consumption pattern.
Description
Technical field
The present invention relates to IC design field, particularly relate to a kind of power-supply circuit and control method thereof.
Background technology
In IC design field, along with manufacturing process striding forward to deep submicron process, low-power consumption has become as and sets
Key in meter, reduction power consumption becomes one of critical consideration in design.
In existing IC design, mainly chip designs when, by the optimization of power consumption, set from entirety
Reduce the power consumption of chip on meter, need in the design to take more time, and the power consumption that can reduce also has limitation,
It is difficult to reduce chip overall power to a greater degree.
Summary of the invention
The invention provides a kind of power-supply circuit and control method thereof, by different voltage stabilizing electricity under different power consumption pattern
Road provides power supply, reduces power consumption, improves design efficiency.
The invention provides the control method of a kind of power-supply circuit, power-supply circuit include the first mu balanced circuit and
Second mu balanced circuit, the load current of the first mu balanced circuit is more than the load current of the second mu balanced circuit, and described method includes:
When load is in normal mode of operation, the first mu balanced circuit provide supply voltage for load；
When load is in low power mode of operation, the second mu balanced circuit provide supply voltage for load.
Alternatively, power-supply circuit also includes the switch module being connected with the outfan of the second mu balanced circuit, is used for
Controlling the output of the output voltage of the second mu balanced circuit, wherein, the second mu balanced circuit is constantly in duty, then, also include:
After the instruction receiving load entrance low power mode of operation, the dynamic power consumption that first will load is closed, then by the first voltage stabilizing
Circuit is closed, and finally controls switch module in the conduction state, so that the second mu balanced circuit provides electricity to load
Source voltage；Receiving after load is in the instruction of normal mode of operation, first the dynamic power consumption of load is being opened, then by first
Mu balanced circuit is in running order, finally control switch module is in open-circuit condition, so that the first mu balanced circuit is to load
Supply voltage is provided.
Additionally, present invention also offers a kind of power-supply circuit, including:
First mu balanced circuit, for providing supply voltage when load is in normal mode of operation for load；
Second mu balanced circuit, for providing supply voltage when load is in low power mode of operation for load, first is steady
The load current of volt circuit is more than the load current of the second mu balanced circuit.
Alternatively, described first mu balanced circuit includes the first branch road, the second branch road, constant-current source and the first electric capacity；Wherein,
First branch road includes the power transistor being sequentially connected in series, reference voltage transistor, enables transistor and first
Pull-down transistor, power transistor one end of the first branch road connects supply voltage, first pull-down transistor one end ground connection, with reference to electricity
The grid end of piezoelectric crystal connects reference voltage, and the grid end enabling transistor connects enable signal；
Second branch road includes driving transistor and the second pull-down transistor being sequentially connected in series, and the driving of the second branch road is brilliant
Body pipe one end connects supply voltage, second pull-down transistor one end ground connection；
Constant-current source is respectively and drives transistor and the first pull-down transistor, the second pull-down transistor to provide bias current, drives
The current output terminal of dynamic transistor is connected to the grid end of power transistor；
Power transistor is voltage output end with the common port of reference voltage transistor, to export the first voltage.
Alternatively, constant-current source includes:
For the first transistor of the type of attachment of mirror image diode, the first transistor connects input current, and respectively the
Three transistors and the 4th transistor provide the bias current of mirror image；
The 7th transistor being connected with third transistor, is provided bias current by third transistor to the 7th transistor；
The 8th transistor being connected with the 4th transistor, is provided bias current by the 4th transistor to the 8th transistor；
For the 5th transistor of the type of attachment of mirror image diode, the 5th transistor connects the 9th transistor, the 9th crystal
7th transistor of the type of attachment of Guan Youwei mirror image diode provides bias current, by the 5th transistor to driving transistor to carry
Bias current for mirror image；
8th transistor is the type of attachment of mirror image diode, provides for the first pull-down transistor and the second pull-down transistor
The bias current of mirror image.
Alternatively, constant-current source also includes:
The transistor seconds of the bias current of mirror image is provided by the first transistor；
Tenth transistor of concatenation and the 6th transistor, by transistor seconds to the tenth transistor concatenated and the 6th crystal
Pipe provides bias current；
With the 11st transistor of the 7th transistor series connection, by third transistor to concatenation the 7th transistor and the 11st
Transistor provides bias current, the 7th transistor of concatenation and the type of attachment that the 11st transistor is mirror image diode；
With the tenth two-transistor of the 8th transistor series connection, by the 4th transistor to concatenation the 8th transistor and the 12nd
Transistor provides bias current, the 8th transistor of concatenation and the type of attachment that the tenth two-transistor is mirror image diode；
With the 13rd transistor of the 9th transistor series connection, the 5th transistor connect the 13rd transistor that is sequentially connected in series and
9th transistor；
The 14th transistor concatenated with the second pull-down transistor, by driving the transistor the second pull-down transistor to concatenation
Bias current is provided with the 14th transistor；
Tenth transistor of concatenation and the grid end of the 6th transistor are connected respectively to the current output terminal of transistor seconds, point
Do not provide bias voltage to the grid end of the 11st transistor, the tenth two-transistor, the 13rd transistor and the 14th transistor.
Alternatively, it is also associated with concatenating between common port and the voltage output end driving transistor AND gate the 14th transistor
The first resistance and the second electric capacity.
Alternatively, the 3rd electric capacity connected between the grid end of voltage output end and the 9th transistor.
Alternatively, the second mu balanced circuit includes:
Differential amplifier circuit, the grid termination reference voltage of its first input transistors, the grid termination of the second input transistors
Feedback voltage, the load of the first input transistors and the second input transistors is current mirror load, and the first input transistors one
The type of attachment that load is mirror image diode of end；
Feedback branch, including the second power transistor, for providing anti-to the second input transistors of differential amplifier circuit
Feedthrough voltage；
Output branch road, including the 3rd power transistor, for output the second voltage；
Wherein, the common port that the second input transistors of differential amplifier circuit loads with it connect respectively the 4th electric capacity, second
Power transistor, the grid end of the 3rd power transistor.
Alternatively, switch module and the control unit being connected with the outfan of the second mu balanced circuit, the second voltage stabilizing are also included
Circuit is constantly in duty；
Switch module, for controlling the output of the output voltage of the second mu balanced circuit；
Control unit, is used for after the instruction receiving load entrance low power mode of operation, the dynamic merit that first will load
Consumption is closed, and is then closed by the first mu balanced circuit, finally controls switch module in the conduction state, so that second
Mu balanced circuit provides supply voltage to load；Receiving after load is in the instruction of normal mode of operation, first dynamic by load
State power consumption is opened, and then by running order for the first mu balanced circuit, finally control switch module is in open-circuit condition, so that
Obtain the first mu balanced circuit and provide supply voltage to load.
The power-supply circuit of embodiment of the present invention offer and control method thereof, when load is in normal mode of operation,
First mu balanced circuit bigger by load current provides supply voltage, when load is in low-power consumption mode, by less load electricity
Second mu balanced circuit of stream provides supply voltage, so, is provided power supply by different mu balanced circuits, really under different power consumption pattern
Protecting loaded work piece under preferably power consumption mode, and then reduce power consumption, meanwhile, sub-module is designed and the considering of power consumption, can
To improve design efficiency.
Accompanying drawing explanation
For the technical scheme being illustrated more clearly that in the embodiment of the present application, in embodiment being described below required for make
Accompanying drawing be briefly described, it should be apparent that, the accompanying drawing in describing below is only some embodiments of the application, for
From the point of view of those of ordinary skill in the art, on the premise of not paying creative work, it is also possible to obtain it according to these accompanying drawings
His accompanying drawing.
Fig. 1 is the structural representation of the power-supply circuit according to the embodiment of the present invention；
Fig. 2 is the electrical block diagram according to the first mu balanced circuit in the power-supply circuit of the embodiment of the present invention；
First voltage regulator circuit when Fig. 3 is under condition of different temperatures, different process corner condition, different supply voltages
The output voltage waveforms schematic diagram of voltage output end；
When Fig. 4 is under condition of different temperatures, different process corner condition, different supply voltages, load current change time
The output voltage waveforms schematic diagram of the voltage output end of the first voltage regulator circuit；
Fig. 5 is the electrical block diagram according to the second mu balanced circuit in the power-supply circuit of the embodiment of the present invention；
Second voltage regulator circuit when Fig. 6 is under condition of different temperatures, different process corner condition, different supply voltages
The output voltage waveforms schematic diagram of voltage output end；
Fig. 7 is the electrical block diagram of the switch module according to the embodiment of the present invention.
Detailed description of the invention
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Describe, it is clear that described embodiment is only some embodiments of the present application rather than whole embodiments wholely.Based on
Embodiment in the application, it is every other that those of ordinary skill in the art are obtained under not making creative work premise
Embodiment, broadly falls into the scope of the application protection.
In the present invention, it is provided that the control method of a kind of power-supply circuit, power-supply circuit includes the first voltage stabilizing
Circuit and the second mu balanced circuit, the load current of the first mu balanced circuit is more than the load current of the second mu balanced circuit, described method
Including: when load is in normal mode of operation, the first mu balanced circuit provide supply voltage for load；It is in low merit in load
During work consuming operation mode, the second mu balanced circuit provide supply voltage for load.
In the method, load be typically the chip being integrated with circuit module, be such as integrated with CPU module, encrypting module,
The modules such as peripheral module, memory management module, internal memory operation module, power-supply circuit is mainly this these module and provides electricity
Source, in normal mode of operation, circuit module is all in normal operating conditions, and the power supply of chip enables to each circuit module and is in
The duty of dynamic power consumption, the load current of needs is bigger；And when low power mode of operation, circuit module is in static merit
The resting state of consumption, the power supply of chip primarily serves the effect keeping each logic state in chip, and the load current of needs is little.
Based on this, in embodiments of the present invention, when load is in normal mode of operation, by load current bigger first
Mu balanced circuit provides supply voltage, when load is in low-power consumption mode, the second mu balanced circuit of less load current provides
Supply voltage, so, is provided power supply by different mu balanced circuits under different power consumption pattern, it is ensured that loaded work piece is in preferably merit
Under consumption pattern, and then reducing power consumption, meanwhile, sub-module is designed and the considering of power consumption, and can improve design efficiency.
In the particular embodiment, the second mu balanced circuit can be constantly in duty, i.e. output supply voltage, passes through
Switch module realizes the switching of two kinds of mode of operations, and switch module can be such as transistor device, this switch module and
The outfan of two mu balanced circuits connects, and for controlling the output of the output voltage of the second mu balanced circuit, switch module is the most permissible
For transistor switch, the voltage output end of defeated second mu balanced circuit is connected to source and drain one end of transistor switch, so, specifically
Control method in, including: receive load enter low power mode of operation instruction after, first will load dynamic power consumption close
Close, then the first mu balanced circuit is closed, finally control switch module in the conduction state, so that the second voltage stabilizing
Circuit provides supply voltage to load；Receiving after load is in the instruction of normal mode of operation, first will the dynamic merit of load
Consumption is opened, and then by running order for the first mu balanced circuit, finally control switch module is in open-circuit condition, so that the
One mu balanced circuit provides supply voltage to load.In concrete application, the dynamic of load can be controlled by clock signal
The open and close of power consumption, and then realize controlling switch module and the work shape of the first voltage regulator circuit by control signal
State, so, it is achieved the switching of two-way supply voltage, circuit structure is simple and is easily achieved.
Above the control method of the power-supply circuit of the present invention is described in detail, additionally, the present invention also carries
Supply the power-supply circuit in said method, with reference to shown in Fig. 1, including: the first mu balanced circuit, for being in normally in load
Supply voltage is provided for load during mode of operation；
Second mu balanced circuit, for providing supply voltage when load is in low power mode of operation for load, first is steady
The load current of volt circuit is more than the load current of the second mu balanced circuit.
In the particular embodiment, different structure can be selected according to different loads in the demand of different working modes
First mu balanced circuit and the second mu balanced circuit provide power supply.
In an embodiment of the present invention, in normal mode of operation, modules is all in normal operating conditions, the electricity of chip
Source enables to each circuit module and is in the duty of dynamic power consumption, and the load current of needs is relatively big, and stablizes power supply
The performance of property and transient response speed has high requirement；And when low power mode of operation, a lot of circuit modules are in static merit
The resting state of consumption, the power supply of chip primarily serves the effect keeping each logic state in chip, and the load current of needs is little,
Low to the stability of power supply and the performance requirement of transient response speed.
Big based on above load current, power supply stability and transient response speed are required that height considers, currently preferred
In embodiment, with reference to shown in Fig. 2, be the first voltage regulator circuit, including first branch road the 100, second branch road 110, constant-current source 120 with
And the first electric capacity C2；Wherein,
First branch road 100 includes the power transistor Mp being sequentially connected in series, reference voltage transistor Mp7, enables crystal
Pipe Mn12 and the first pull-down transistor Mn11, power transistor Mp one end of the first branch road 100 connect supply voltage Avdd, first
The grid end of pull-down transistor Mn11 one end ground connection Agnd, reference voltage transistor Mp7 connects reference voltage Vref, enables transistor
The grid end of Mn12 connects enable signal pdb；
Second branch road 110 includes driving transistor Mp6 and the second pull-down transistor Mn10 being sequentially connected in series, second
The driving transistor Mp6 one end on road 110 connects supply voltage Avdd, second pull-down transistor one end ground connection Agnd；
Constant-current source 120 provides partially for driving transistor Mp6 and the first pull-down transistor Mn11, the second pull-down transistor Mn10
Put electric current, drive the current output terminal of transistor Mp6 to be connected to the grid end of power transistor Mp；
The common port of power transistor Mp and reference voltage transistor Mp7 is voltage output end E.
In the present invention, the voltage of voltage output end is relevant to the gate source voltage of reference voltage transistor, and passes through constant current
Source controls to keep constant through the electric current of reference voltage transistor, thus realizes the steady of the gate source voltage of reference voltage transistor
Fixed.Additionally, at outfan, use reference voltage and source class follower to determine output voltage values, reduce output impedance
Purpose, it is not necessary to increase extra circuit, reduces the complexity of whole circuit design.
In the concrete application of this embodiment, as in figure 2 it is shown, power transistor Mp, reference voltage transistor Mp7 are
PMOS transistor, reference voltage transistor Mp7, enable transistor Mn12, the first pull-down transistor Mn11 and second time crystal pulling
Pipe Mn10 is nmos pass transistor.
For the first branch road, the source of power transistor Mp connects supply voltage Avdd, drain terminal connects reference voltage crystal
The source of pipe Mp7, the source of reference voltage transistor Mp7 is voltage output end E, the voltage Vout1 of output voltage stabilizer circuit, ginseng
The source examining voltage transistor Mp7 is connected to enable the drain terminal of transistor M12, and the source enabling transistor Mn12 is connected to first
The drain terminal of pull-down transistor Mn11, the source ground connection of the first pull-down transistor Mn11.For the second branch road, drive transistor Mp6
Source connect the drain terminal that supply voltage Avdd, drain terminal connect the second pull-down transistor Mn10, the second pull-down transistor Mn10's
Source ground connection.
Wherein, the grid end of reference voltage transistor Mp7 connects reference voltage Vref, and the grid end enabling transistor Mn12 connects
Enable signal pdb, drive the drain terminal of transistor Mp6 to drive the grid end of power transistor Mp, drive transistor Mp6 to be carried by constant-current source
For bias current, the first pull-down transistor Mn11 and the second pull-down transistor Mn10 is also provided bias current, constant current by constant-current source
The current value of the bias current that source provides is substantially fixing.Enabling signal pdb can be the signal from control module, is needing
When wanting voltage regulator circuit to export so that enabling signal pdb effective, typically its value can be Avdd so that enable transistor Mn12
In the conduction state, reference voltage Vref is held essentially constant, it is common that produced by band-gap reference module.
So, when enabling signal pdb and being effective, owing to driving transistor Mp6, the first pull-down transistor Mn11 and second time
The turn on current value of pull transistor Mn10 is fixed, and the first pull-down transistor Mn11, the electric conduction of the second pull-down transistor Mn10
Flow valuve is equal with the turn on current value of driving transistor Mp6, reference voltage transistor Mp7, therefore flows through reference voltage transistor
The current value of Mp7 is also substantially stationary constant, thus ensure that the gate source voltage Vgs of reference voltage transistor Mp7 keeps solid
Fixed constant, and the output voltage Vout1 of voltage output end E is equal to reference voltage Vref and Vgs sum, it is ensured that voltage output end
The stability of output voltage Vout1.
First electric capacity C2 serves compensating action to the phase margin of loop, improves the stability of loop, also can carry simultaneously
The transient response speed of high circuit.
In the present embodiment, can use suitable constant-current source be respectively drive transistor and the first pull-down transistor, the
Two pull-down transistors provide bias current.In more excellent embodiment, constant-current source provides for multistage circuit mirror current, reference
Shown in Fig. 2, constant-current source includes:
Input current Ibp is connected for the first transistor Mp1 of the type of attachment of mirror image diode, the first transistor Mp1, and
Third transistor Mp3 and the bias current of the 4th transistor Mp4 offer mirror image are provided；
The 7th transistor Mn4 being connected with third transistor Mp3, is provided to the 7th transistor Mn4 by third transistor Mp3
Bias current；
The 8th transistor Mn6 being connected with the 4th transistor Mp4, is provided partially to the 8th transistor by the 4th transistor Mp4
Put electric current Mn6；
The 9th transistor Mn8 is connected for the 5th transistor Mp5 of the type of attachment of mirror image diode, the 5th transistor Mp5,
9th transistor Mn8 is provided bias current, by the 5th transistor by the 7th transistor Mn4 of the type of attachment for mirror image diode
Mp5 is to the bias current driving transistor Mp6 to provide mirror image；
8th transistor Mn6 is the type of attachment of mirror image diode, is the first pull-down transistor Mn10 and second time crystal pulling
Body pipe Mn11 provides the bias current of mirror image.
In an embodiment of the present invention, as in figure 2 it is shown, more preferably, constant-current source also includes:
The transistor seconds Mp2 of the bias current of mirror image is provided by the first transistor Mp1；
The tenth transistor Mn1 and the 6th transistor Mn2 of concatenation, by transistor seconds Mp2 to the tenth transistor of concatenation
Mn1 and the 6th transistor Mn2 provides bias current；
The 11st transistor Mn3 concatenated with the 7th transistor Mn4, by third transistor Mp3 to the 7th crystal of concatenation
Pipe Mn4 and the 11st transistor Mn3 provides bias current, and the 7th transistor Mn4 of concatenation and the 11st transistor Mn3 is mirror image
The type of attachment of diode；
The tenth two-transistor Mn5 concatenated with the 8th transistor Mn6, by the 4th transistor Mp4 to the 8th crystal of concatenation
Pipe Mn6 and the tenth two-transistor Mn5 provides bias current, and the 8th transistor Mn6 of concatenation and the tenth two-transistor Mn5 is mirror image
The type of attachment of diode；
The 13rd transistor Mn7 concatenated with the 9th transistor Mn8, the 5th transistor Mp5 connect the tenth be sequentially connected in series
Three transistor Mn7 and the 9th transistor Mn8；
The 14th transistor Mn9 concatenated with the second pull-down transistor Mn10, by driving transistor Mp6 to the second of concatenation
Pull-down transistor Mn10 and the 14th transistor Mn9 provides bias current；
The tenth transistor Mn1 and the 6th transistor Mn2 of concatenation are respectively to the 11st transistor Mn3, the tenth two-transistor
Mn5, the grid end of the 13rd transistor Mn7 and the 14th transistor Mn9 provide bias voltage.
In this preferred embodiment, the first transistor Mp1, transistor seconds Mp2, third transistor Mp3, the 4th crystal
Pipe Mp4 and the 5th transistor Mp5 is PMOS transistor, the 6th transistor Mn2, the 7th transistor Mn4, the 8th transistor Mn6,
Nine transistor Mn8, the tenth transistor Mn1, the 11st transistor Mn3, the tenth two-transistor Mn5, the 13rd transistor Mn7 and
14 transistor Mn9 are nmos pass transistor.
The first transistor Mp1 is the type of attachment of mirror image diode, when the first transistor Mp1 is PMOS transistor, and will
The grid end of the first transistor Mp1 is connected to drain terminal, and drain terminal connects input current, and source connects supply voltage, first crystal
The grid end of pipe Mp1 is connected respectively to transistor seconds Mp2, third transistor Mp3, the grid end of the 4th transistor Mp4, the second crystal
Pipe Mp2, third transistor Mp3, the 4th transistor Mp4 source connect supply voltage, so, the first transistor Mp1 respectively with
Transistor seconds Mp2, third transistor Mp3, the 4th transistor Mp4 are that the circuit of mirror current source connects, by the first transistor
Mp1 provides the bias current of mirror image respectively to transistor seconds Mp2, third transistor Mp3, the 4th transistor Mp4, thus second
Transistor Mp2, third transistor Mp3, the 4th transistor Mp4 export of substantially equal electric current respectively.And transistor seconds Mp2
Drain terminal connects the tenth transistor Mn1 and the 6th transistor Mn2 of concatenation, in the present embodiment, and the tenth transistor Mn1 of concatenation and the
Six transistor Mn2 are nmos pass transistor pair, and the source of the tenth transistor Mn1 connects the drain terminal of the 6th transistor Mn2, the 6th crystal
The source ground connection of pipe Mn2, so, connects the tenth transistor Mn1 and the 6th transistor Mn2 of concatenation at transistor seconds Mp2
In branch road, the electric current of transistor seconds Mp2 output provides biased electrical to the tenth transistor Mn1 and the 6th transistor Mn2 of concatenation
Stream；The tenth transistor Mn1 and the branch road of the 6th transistor Mn2, third transistor Mp3 of concatenation is connected with transistor seconds Mp2
Connecting the 11st transistor Mn3 and the 7th transistor Mn4 of concatenation, the 4th transistor Mp4 connects the tenth two-transistor of concatenation
Mn5 and the 8th transistor Mn6.
5th transistor Mp5 is also the type of attachment of mirror image diode, when the 5th transistor Mp5 is PMOS transistor, i.e.
The grid end of the 5th transistor Mp5 being connected to drain terminal, and drain terminal connects input current, source connects supply voltage, and the 5th is brilliant
The grid end of body pipe Mp5 is connected to drive the grid end of transistor Mp6, is connected with the circuit driving transistor to form mirror current source,
For driving transistor Mp6 to provide the bias current of mirror image, connect the tenth transistor Mn1 and the of concatenation with transistor seconds Mp2
The branch road of six transistor Mn2, the drain terminal of the 5th transistor Mp5 connects the 13rd transistor Mn7 and the 9th transistor of concatenation
Mn8.The electric current driving transistor Mp6 output is the most identical with the bias current of the 5th transistor place branch road.With the second crystal
Pipe Mp2 connects the tenth transistor Mn1 and the branch road of the 6th transistor Mn2 of concatenation, drives the drain terminal of transistor Mp6 to connect concatenation
The 14th transistor Mn9 and the first pull-down transistor Mn10.
Additionally, the grid end of the tenth transistor Mn1 and the 6th transistor Mn2 of concatenation is connected respectively to transistor seconds Mp2
Current output terminal, brilliant to the 11st transistor Mn3, the tenth two-transistor Mn5, the 13rd transistor Mn7 and the 14th respectively
The grid end of body pipe Mn9 provides bias voltage, and in the present embodiment, the current output terminal of transistor seconds Mp2 is drain terminal；The of concatenation
11 transistor Mn3 and the type of attachment that the 7th transistor Mn4 is mirror image diode, and be the 9th crystalline substance by the 7th transistor Mn4
Body pipe Mn8 provides the bias current of mirror image, in the present embodiment concrete connects, will the grid end of the 7th transistor Mn4 connect
To the current output terminal of third transistor Mp3, namely the drain terminal of the 11st transistor Mn3, so, it is that the 9th transistor Mn8 carries
Essentially identical for the bias current of mirror image and the electric current of the 4th transistor Mp4 output；Similarly, the tenth two-transistor of concatenation
Mn5 and the 8th transistor Mn6 is also the type of attachment of mirror image diode, and is the first pull-down transistor by the 8th transistor Mn6
Mn11 and the second pull-down transistor Mn10 provide the bias current of mirror image, so, are the first pull-down transistor Mn11 and second time
The bias current of pull transistor Mn10 offer mirror image is essentially identical with the electric current that third transistor Mp3 exports, and drives transistor
The bias current of Mp6 and the bias current of the 5th transistor Mp5 are image current, and input current Ibp be metastable partially
Put electric current so that the current value driving transistor Mp6, the first pull-down transistor Mn11 and the second pull-down transistor Mn10 conducting is solid
Fixed, and the first pull-down transistor Mn11 and the second pull-down transistor Mn10 leads with driving transistor Mp6, reference transistor Mp7
Energising flow valuve is of substantially equal, then, also it is substantially changeless through reference transistor Mp7 current value, thus ensure that ginseng
The gate source voltage Vgs examining transistor Mp7 keeps stable, and then ensure the output voltage Vout1 of whole first voltage regulator circuit
Stability.
In this preferred embodiment, to contribute to improving image current further accurate for transistors of these concatenations above-mentioned
Property, and then ensure to the first pull-down transistor Mn11, the second pull-down transistor Mn10 and drive transistor Mp6 to provide essentially identical
Bias current.
Additionally, be also connected with between transistor Mp6 and the common port of the 14th transistor Mn9 and voltage output end E driving
There are a first resistance R and the second electric capacity C1 of concatenation, and further, at voltage output end E and the grid end of the 9th transistor Mn8
Between connect the 3rd electric capacity C3.Second electric capacity C1 serves compensating action to the phase margin of loop, improves stablizing of loop
Property, also can improve the transient response speed of circuit simultaneously.
3rd electric capacity C3 is primarily to improve the transient response speed of the first voltage regulator circuit, its operation principle further
For, when output loading increases, power transistor Mp grid terminal voltage can not be suddenlyd change so that output voltage Vout1 reduces, due to the
The AC coupled effect of three electric capacity C3 so that the grid terminal voltage of the 9th transistor Mn8 reduces, and then drive leading of transistor Mp6
Galvanization decreases, simultaneously as output voltage Vout1 reduces, and reference voltage Vref keeps constant, reference transistor
The conducting electric current of Mp7 can decrease, and the first pull-down transistor Mn11 and the second pull-down transistor Mn10 electric current keep constant,
Therefore, the gate source voltage of reference transistor Mp7 can reduce due to the imbalance of electric current, and the reduction to output voltage Vout1 rises
To certain compensating action.Same reason, when output loading reduces, can play alleviation to the rising of output voltage Vout1
Effect, thus improves output voltage due to the speed of whole transient response during load change.
With reference to shown in Fig. 3, the emulation ripple of the output voltage of the first mu balanced circuit voltage output end when changing for different parameters
Shape schematic diagram, the parameter of change includes different temperatures, different process angle and different electrical power voltage, and wherein, temperature is respectively-40
DEG C, 25 DEG C, 85 DEG C, supply voltage is respectively the simulation waveform schematic diagram of the output voltage in the case of 1.8V, 3.3V and 5V, from figure
Show that, it will be seen that output voltage control is between 1.49V to 1.64V, output voltage, in the range of 1.5V ± 10%, meets
The requirement of the excursion of output voltage in design objective.
With reference to shown in Fig. 4, the simulation waveform schematic diagram of the output voltage changed with load current when changing for different parameters,
The parameter of change includes different temperatures, different process angle and different electrical power voltage, wherein, temperature be respectively-40 DEG C, 25 DEG C, 85
DEG C, supply voltage is respectively 1.8V, 3.3V and 5V, and load current changes in the range of 50uA to 15mA, rising and falling time
For 10ns, load capacitance is 100pF.From emulation schematic diagram it will be seen that under the worst case of load changing, output voltage
Stationary value can also be reached, it is possible to meet the requirement of design objective and engineer applied within the time of 2us.
Little based on above load current, power supply stability and transient response speed are required low consideration, with reference to shown in Fig. 5,
For the second voltage regulator circuit of the preferred embodiment of the present invention, including:
Differential amplifier circuit 200, the grid termination reference voltage of its first input transistors MN25, the second input transistors
The grid termination feedback voltage Vfb of MN26, the first input transistors MN25 and load MP21, MP22 of the second input transistors MN26
For current mirror load, and the type of attachment that load MP21 is mirror image diode of first input transistors MN25 one end；
Feedback branch 210, including the second power transistor MNZ1, for the second input transistors of differential amplifier circuit
MN26 provides feedback voltage Vfb；
Output branch road 220, including the 3rd power transistor MNZ2, for output the second voltage Vout_sty；
Wherein, the outfan of the second input transistors NM26 of differential amplifier circuit 200 connect respectively the 4th electric capacity MN27,
Two power transistor MNZ1, the grid end of the 3rd power transistor MNZ2.
In concrete application, as it is shown in figure 5, the tail current of differential amplifier circuit 200 is passed through mirror image by input current Ibn
Electric current provides, concrete, and the nmos pass transistor that the afterbody connection at differential amplifier circuit 200 concatenates is to MN23, MN24, separately
One concatenates and is formed another NMOS tube that mirror image diode connects to MN21, MN22, connects input current Ibn, to transistor
MN23, MN24 provide the bias current of mirror image, and the bias current of this mirror image is the tail current of differential amplifier circuit 200.Difference is put
The Differential Input of big circuit 200, to for the first input transistors MN25 and the second input transistors MN26, is all nmos pass transistor；
PMOS transistor MP21, the drain terminal of MP22 connect supply voltage AVDD, source and connect the first input transistors MN25 and the respectively
Two input transistors MN26, and form current mirror connection, as the amplifier current mirror load of Differential Input pair, the first input crystal
The load of pipe MN25 one end is PMOS transistor MP21, for the source of the type of attachment of mirror image diode, i.e. PMOS transistor MP21
End is connected with grid end and its grid end is connected to the grid end of PMOS transistor MP22, so, by this branch road of the first input transistors
Bias current is provided to this branch road of transistor seconds.
Feedback branch 210 provides grid terminal voltage, in concrete application, this feedback branch bag for the second input transistors MN26
Include the 3rd resistance R21, the second power transistor MNZ1, the 4th resistance R22 and being sequentially connected with from supply voltage AVDD one end
Five resistance R23, the 5th resistance R23 other end ground connection AVSS, the 4th resistance R22, the 5th resistance R23 constitute this feedback branch 210
Bleeder circuit, by regulation the 4th resistance R22, the proportionate relationship of the 5th resistance R23 so that feedback voltage Vfb is final
Equal with Vref voltage.
Output branch road 220 is for output the second voltage Vout_sty, it is provided that the output supply voltage of the second mu balanced circuit, tool
In the application of body, this output branch road 220 includes the 6th resistance R24 and the 3rd power crystal being sequentially connected with from supply voltage one end
The outfan that source is the second mu balanced circuit of pipe MNZ2, the 3rd power transistor MNZ2, in the application that this is concrete, the 3rd merit
Rate transistor MNZ2 and the second power transistor MNZ1 is that native nmos pass transistor is managed as driving, and its threshold voltage is relatively
Little, close to 0.
The outfan of the second input transistors NM26 of differential amplifier circuit 200, namely load MP22 and second input
The common port of transistor MN26, connects the 4th electric capacity MN27, the second power transistor MNZ1, the 3rd power transistor MNZ2 respectively
Grid end, the 4th electric capacity NM27 is nmos pass transistor, plays the effect of charging, is the second power transistor MNZ1, the 3rd power
Transistor MNZ2 provides grid terminal voltage.
In order to be more fully understood that the technical scheme of this second mu balanced circuit, in conjunction with this specific embodiment, to its work
Principle is described in detail.In a concrete application, input current Ibn and reference voltage Vref are all carried by base modules
Confession, after supply voltage AVDD powers on, Ibn and reference voltage Vref the most normally work, when firm power-up state, differential amplification electricity
The first input transistors MN25 on road 200 is conducting, and feedback voltage Vfb is 0, and the tail current of differential amplifier circuit 200 is complete
Portion is all from the first input transistors MN25 circulation, and due to the effect of current mirror load so that connect the second input transistors with
The capacitance voltage VG of the common port of its load is continuously increased, thus rely on the second power transistor MNZ1 of feedback branch 210
Source electrode Following effect, the feedback voltage Vfb in feedback branch 210 is continuously increased, and passes through feedback circuit so that feedback voltage Vfb
The most identical with reference voltage Vref, so that whole loop stability is got off, at identical feedback voltage Vfb and reference voltage
During Vref so that the source voltage terminal Vout2 of the second power transistor MNZ1 is substantially equal to voltage Vout_sty, export branch road 220
Export stable voltage Vout_sty, i.e. export the second stable voltage.For the second mu balanced circuit, in low power mode of operation
Time supply voltage, the purpose of this supply voltage mainly play keep logic state effect, the design circuit of this embodiment makes
The 3rd power transistor that must export the second voltage is in outside feedback circuit, the problem not havinging stability, it is not necessary to extra
Stabiloity compensation design and the consideration of transient response performance, the complexity of design is low and circuit power consumption is low.
With reference to shown in Fig. 6, the emulation ripple of the output voltage of the second mu balanced circuit voltage output end when changing for different parameters
Shape schematic diagram, the parameter of change includes different temperatures, different process angle and different electrical power voltage, and wherein, temperature is respectively-40
DEG C, 25 DEG C, 85 DEG C, supply voltage is respectively the simulation waveform schematic diagram of the output voltage in the case of 1.8V, 3.3V and 5V, from figure
Show that, it will be seen that output voltage control is between 1.37V to 1.6V, output voltage, in the range of 1.5V ± 10%, meets
The requirement of the excursion of output voltage in design objective.
For above power-supply circuit, switch module and control unit can be passed through, realize first further steady
Volt circuit and the switching of the second mu balanced circuit out-put supply, concrete, also include: what the outfan of the second mu balanced circuit connected opens
Closing module and control unit, the second mu balanced circuit is constantly in duty；Switch module, for controlling the second mu balanced circuit
The output of output voltage；Control unit, for after the instruction receiving load entrance low power mode of operation, first by load
Dynamic power consumption is closed, and is then closed by the first mu balanced circuit, finally controls switch module in the conduction state, so that
Obtain the second mu balanced circuit and provide supply voltage to load；Receiving after load is in the instruction of normal mode of operation, first will be negative
The dynamic power consumption carried is opened, and then by running order for the first mu balanced circuit, finally control switch module is in open circuit shape
State, so that the first mu balanced circuit provides supply voltage to load.
In a concrete application, with reference to shown in Fig. 7, this switch module is transistor device, the grid of transistor device
End connection control signal PD, source and drain one end of transistor device connects the voltage output end Vout_sty of the second voltage regulator circuit,
The other end is the voltage output end Vout of whole power-supply circuit, so, when low-power consumption mode, enables control signal PD,
So that transistor device conducting, so, transistor device works, and voltage output end Vout exports the defeated of the second voltage regulator circuit
Go out voltage Vout_sty；When normal mode of operation, control signal PD is invalid so that transistor device is closed, voltage output end
Vout connects the output voltage Vout1 of the first voltage regulator circuit, thus exports the output voltage of the first voltage regulator circuit.
Power-supply circuit and control method thereof to the embodiment of the present invention are described above, are particularly suitable for
Application in RFID chip, reduces chip power-consumption, improves design efficiency.
It should be noted that in this article, the relational terms of such as first and second or the like is used merely to a reality
Body or operation separate with another entity or operating space, and deposit between not necessarily requiring or imply these entities or operating
Relation or order in any this reality.And, term " includes ", " comprising " or its any other variant are intended to
Comprising of nonexcludability, so that include that the process of a series of key element, method, article or equipment not only include that those are wanted
Element, but also include other key elements being not expressly set out, or also include for this process, method, article or equipment
Intrinsic key element.In the case of there is no more restriction, statement " including ... " key element limited, it is not excluded that
Including process, method, article or the equipment of described key element there is also other identical element.
Claims (10)
1. the control method of power-supply circuit, power-supply circuit includes the first mu balanced circuit and the second mu balanced circuit, first
The load current of mu balanced circuit is more than the load current of the second mu balanced circuit, it is characterised in that described method includes:
When load is in normal mode of operation, the first mu balanced circuit provide supply voltage for load；
When load is in low power mode of operation, the second mu balanced circuit provide supply voltage for load.
Control method the most according to claim 1, it is characterised in that also include in power-supply circuit and the second voltage stabilizing electricity
The switch module that the outfan on road connects, for controlling the output of the output voltage of the second mu balanced circuit, wherein, the second voltage stabilizing electricity
Road is constantly in duty, then, also include: after the instruction receiving load entrance low power mode of operation, first will load
Dynamic power consumption close, then the first mu balanced circuit is closed, finally control switch module in the conduction state, with
The second mu balanced circuit is made to provide supply voltage to load；Receiving after load is in the instruction of normal mode of operation, first will
The dynamic power consumption of load is opened, and then by running order for the first mu balanced circuit, finally control switch module is in open circuit
State, so that the first mu balanced circuit provides supply voltage to load.
3. a power-supply circuit, it is characterised in that including:
First mu balanced circuit, for providing supply voltage when load is in normal mode of operation for load；
Second mu balanced circuit, for providing supply voltage, the first voltage stabilizing electricity when load is in low power mode of operation for load
The load current on road is more than the load current of the second mu balanced circuit.
Power-supply circuit the most according to claim 3, it is characterised in that described first mu balanced circuit includes first
Road, the second branch road, constant-current source and the first electric capacity；Wherein,
First branch road includes that the power transistor, reference voltage transistor, enable transistor and first that are sequentially connected in series are drop-down
Transistor, power transistor one end of the first branch road connects supply voltage, first pull-down transistor one end ground connection, and reference voltage is brilliant
The grid end of body pipe connects reference voltage, and the grid end enabling transistor connects enable signal；
Second branch road includes driving transistor and the second pull-down transistor being sequentially connected in series, the driving transistor of the second branch road
One end connects supply voltage, second pull-down transistor one end ground connection；
Constant-current source is respectively and drives transistor and the first pull-down transistor, the second pull-down transistor to provide bias current, drives crystalline substance
The current output terminal of body pipe is connected to the grid end of power transistor；
Power transistor is voltage output end with the common port of reference voltage transistor, to export the first voltage.
Power-supply circuit the most according to claim 4, it is characterised in that constant-current source includes:
For the first transistor of the type of attachment of mirror image diode, the first transistor connects input current, and respectively the is trimorphism
Body pipe and the 4th transistor provide the bias current of mirror image；
The 7th transistor being connected with third transistor, is provided bias current by third transistor to the 7th transistor；
The 8th transistor being connected with the 4th transistor, is provided bias current by the 4th transistor to the 8th transistor；
For the 5th transistor of the type of attachment of mirror image diode, the 5th transistor connects the 9th transistor, the 9th transistor by
The 7th transistor for the type of attachment of mirror image diode provides bias current, by the 5th transistor to driving transistor to provide mirror
The bias current of picture；
8th transistor is the type of attachment of mirror image diode, provides mirror image for the first pull-down transistor and the second pull-down transistor
Bias current.
Power-supply circuit the most according to claim 5, it is characterised in that constant-current source also includes:
The transistor seconds of the bias current of mirror image is provided by the first transistor；
Tenth transistor of concatenation and the 6th transistor, carried to the tenth transistor and the 6th transistor of concatenation by transistor seconds
For bias current；
With the 11st transistor of the 7th transistor series connection, by third transistor to concatenation the 7th transistor and the 11st crystal
Pipe provides bias current, the 7th transistor of concatenation and the type of attachment that the 11st transistor is mirror image diode；
With the tenth two-transistor of the 8th transistor series connection, by the 4th transistor to concatenation the 8th transistor and the 12nd crystal
Pipe provides bias current, the 8th transistor of concatenation and the type of attachment that the tenth two-transistor is mirror image diode；
With the 13rd transistor of the 9th transistor series connection, the 5th transistor connects the 13rd transistor and the 9th being sequentially connected in series
Transistor；
The 14th transistor concatenated with the second pull-down transistor, by driving the transistor the second pull-down transistor and the to concatenation
14 transistors provide bias current；
Tenth transistor of concatenation and the grid end of the 6th transistor are connected respectively to the current output terminal of transistor seconds, respectively to
The grid end of the 11st transistor, the tenth two-transistor, the 13rd transistor and the 14th transistor provides bias voltage.
Power-supply circuit the most according to claim 4, it is characterised in that driving transistor AND gate the 14th transistor
The first resistance and the second electric capacity concatenated it is also associated with between common port with voltage output end.
Power-supply circuit the most according to claim 4, it is characterised in that at voltage output end and the grid of the 9th transistor
The 3rd electric capacity connected between end.
Power-supply circuit the most according to claim 1, it is characterised in that the second mu balanced circuit includes:
Differential amplifier circuit, the grid termination reference voltage of its first input transistors, the grid termination feedback of the second input transistors
Voltage, the load of the first input transistors and the second input transistors is current mirror load, and first input transistors one end
Load is the type of attachment of mirror image diode；
Feedback branch, including the second power transistor, for providing feedback electricity to the second input transistors of differential amplifier circuit
Pressure；
Output branch road, including the 3rd power transistor, for output the second voltage；
Wherein, the common port that the second input transistors of differential amplifier circuit loads with it connects the 4th electric capacity, the second power respectively
Transistor, the grid end of the 3rd power transistor.
10. according to the power-supply circuit according to any one of claim 1-9, it is characterised in that also include and the second voltage stabilizing
The switch module of the outfan connection of circuit and control unit, the second mu balanced circuit is constantly in duty；
Switch module, for controlling the output of the output voltage of the second mu balanced circuit；
Control unit, for after the instruction receiving load entrance low power mode of operation, the dynamic power consumption that first will load closes
Close, then the first mu balanced circuit is closed, finally control switch module in the conduction state, so that the second voltage stabilizing
Circuit provides supply voltage to load；Receiving after load is in the instruction of normal mode of operation, first will the dynamic merit of load
Consumption is opened, and then by running order for the first mu balanced circuit, finally control switch module is in open-circuit condition, so that the
One mu balanced circuit provides supply voltage to load.
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| CN106125818B (en) | 2017-11-14 |
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Effective date of registration: 20180115 Address after: 430075 Hubei Wuhan city East Lake Development Zone Hi-tech Avenue 666 Wuhan national biological industry base project B, C, D District R & D building 408 room building Patentee after: WUHAN TAILI MEIXIN MEDICAL SCIENCE & TECHNOLOGY CO., LTD. Address before: 215123 Jiangsu Suzhou city Suzhou Industrial Park, Jinji Lake Road 99 Suzhou Nancheng North District 23 building 214 room Patentee before: Terry maxim (Suzhou) Medical Technology Co Ltd |