CN102270006B - Voltage regulator circuit - Google Patents
Voltage regulator circuit Download PDFInfo
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- CN102270006B CN102270006B CN201110176488.XA CN201110176488A CN102270006B CN 102270006 B CN102270006 B CN 102270006B CN 201110176488 A CN201110176488 A CN 201110176488A CN 102270006 B CN102270006 B CN 102270006B
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Abstract
The present invention discloses a kind of voltage regulator circuit, comprise the first reference voltage generating circuit of generation first reference voltage, the first charge pump, the second reference voltage generating circuit producing the second reference voltage, the first switch, control circuit, the first electric capacity and the second electric capacity, first switch is connected to the first reference voltage generating circuit and the first charge pump respectively, output reference voltage; The input end of control circuit is connected with the first charge pump and the second reference voltage generating circuit, the first charge pump is controlled to produce a charge pump enable signal, the present invention is by realizing a reference voltage capable of fast starting, avoiding prior art uses reference voltage source generation reference voltage can sacrifice the problem of stand-by power consumption, reduces the power consumption of circuit.
Description
Technical field
The present invention relates to a kind of voltage regulator circuit, particularly relate to a kind of voltage regulator circuit for flash read operation.
Background technology
Voltage stabilizer is a kind of feed circuit or equipment that automatically can adjust output voltage, its effect is stabilized in its range of set value by comparatively large and the requirement of inadequacy electric equipment for fluctuation supply voltage, and various circuit or electric equipment can be worked under rated operational voltage.
At present, integrated circuit is all provide stable voltage by voltage stabilizer.For voltage stabilizer, reference voltage is that voltage stabilizer produces the requisite key element of output voltage, and the generation of reference voltage needs a bandgap reference source usually.Fig. 1 is the electrical block diagram of existing voltage stabilizer, and as shown in Figure 1, existing voltage stabilizer comprises bandgap reference source 10, operational amplifier 20 and bleeder circuit 30.Wherein bleeder circuit 30 comprises PMOS M1 and to drain resistance R3 and R4 be connected with PMOS M1, one end of resistance R3 is connected with the drain electrode of PMOS M1, the other end is connected with resistance R4, the other end ground connection of R4, the source electrode of PMOS M1 meets DC input voitage Vddq, and the output end vo ut of this voltage stabilizer is connected with the drain electrode of PMOS M1; Bandgap reference source 10 produces a reference voltage Vref, and this reference voltage Vreg is input to the normal phase input end V+ of operational amplifier 20, and the output end vo of operational amplifier 20 is connected with the grid of PMOS M1, and its inverting input V-is connected between resistance R3 and R4.According to the characteristic of operational amplifier, Vref=Vout*R4/ (R3+R4).
But because the start-up time in bandgap reference source 10 is very long, can not close when standby, therefore, even if under standy operation mode, bandgap reference source 10 also can produce standby energy consumption, and this energy consumption consumes standby power supply to a great extent.For the integrated circuit for low energy consumption application model, thisly under standy operation mode, produce the raising that additional energy causes circuit integrity energy consumption to a great extent due to voltage stabilizer, thus low energy consumption is applied be restricted.
In sum, the voltage regulator circuit of known prior art exists due to the problem of sacrificing stand-by power consumption and then cause circuit integrity energy consumption to improve, and therefore, is necessary the technological means proposing to improve in fact, solves this problem.
Summary of the invention
Exist due to the problem of sacrificing stand-by power consumption and then cause circuit integrity energy consumption to improve for overcoming above-mentioned prior art voltage regulator circuit, fundamental purpose of the present invention is to provide a kind of voltage regulator circuit, it can produce the reference voltage started fast, thus can not sacrifice stand-by power consumption, chip occupying area is little simultaneously.
For reaching above-mentioned and other object, a kind of voltage regulator circuit of the present invention, at least comprises:
First reference voltage generating circuit, for generation of one first reference voltage;
First charge pump, under the control of charge pump enable signal, produces a High voltage output;
First switch, is connected to this first reference voltage generating circuit and this first charge pump respectively, under controlling at this first reference voltage, the output of this first charge pump is produced reference voltage by this first switch and exports;
Control circuit, has two input ends, and this two input end is all connected to this first electric charge delivery side of pump, to produce this charge pump enable signal to control this first charge pump under the input signal effect of this two input end;
Second reference voltage generating circuit, be connected to outside read operation commencing signal, and be connected with this first switch and this control circuit, under the control at this outside read operation commencing signal, produce the second reference voltage export this reference voltage by this first switch and as one of this control circuit input signal; And
First electric capacity and the second electric capacity, between the output terminal that this first electric capacity is connected on this first charge pump and ground, the second electric capacity is connected between this first switch and ground.
Further, this first switch is the first nmos pass transistor, and this first nmos pass transistor grid is connected with this first reference voltage generating circuit, and drain electrode is connected to the output terminal of this first charge pump, and source electrode exports this reference voltage.
Further, this control circuit comprises the first control signal and produces circuit, the second control signal generation circuit and rest-set flip-flop, this first control signal produces circuit lotus root and is connected to this first electric charge delivery side of pump, to produce the first control signal under the control of the output of this first charge pump; This second control signal produces circuit and connects with this first charge pump and this second reference voltage generating circuit, to produce the second control signal under the output and the control of this second reference voltage of this first charge pump; Two input ends of this rest-set flip-flop are connected to this first control signal generation circuit respectively and this second control signal produces circuit, and its output terminal exports this charge pump enable signal.
Further, this first control signal produces circuit and comprises the second nmos pass transistor, first PMOS transistor, 3rd nmos pass transistor, 4th nmos pass transistor, second PMOS transistor and the first phase inverter, this the second nmos pass transistor grid leak connects and is connected to this first electric charge delivery side of pump, source electrode is connected to this first PMOS transistor source electrode, this the first PMOS transistor grid connects supply voltage, drain electrode is connected to the drain electrode of the 3rd nmos pass transistor and the input end of this first phase inverter, this first inverter output exports this first control signal, 3rd nmos pass transistor source ground, grid is connected to the 4th nmos pass transistor grid, the drain electrode of this second PMOS transistor is connected to after 4th nmos pass transistor grid leak interconnection, this the second PMOS transistor source electrode connects this supply voltage, grounded-grid.
Further, this second control signal produces circuit and comprises the 3rd PMOS transistor, 5th nmos pass transistor, 6th nmos pass transistor, second phase inverter and the 3rd phase inverter, this first charge pump and this second reference voltage generating circuit is connect after 5th nmos pass transistor grid leak interconnection, source electrode is connected to the 3rd PMOS transistor source electrode, 3rd PMOS transistor grid connects this supply voltage, drain electrode is connected to the input end of the 6th nmos transistor drain and this second phase inverter, 6th nmos pass transistor grid is connected to the 4th nmos pass transistor and the 3rd nmos pass transistor grid, source ground, this second inverter output connects the 3rd inverter input, 3rd inverter output exports this second control signal.
Further, this the first/the second reference voltage generating circuit comprises the second charge pump, mu balanced circuit and clock signal generator, wherein, this mu balanced circuit comprises the 7th nmos pass transistor, 8th nmos pass transistor, 9th nmos pass transistor and a comparer, this the second electric charge delivery side of pump is connected to after 7th nmos pass transistor grid leak interconnection, its source electrode is connected to the 8th nmos transistor drain, 8th nmos pass transistor grid leak interconnection, source electrode is connected to the 9th nmos transistor drain, 8th nmos pass transistor source electrode is also connected to the positive input terminal of this comparer simultaneously, to provide a sampled voltage to this comparer, 9th nmos pass transistor grid leak interconnection, source ground, negative input termination 1 the 3rd reference voltage generating circuit of this comparer, to receive the 3rd reference voltage, its output terminal is connected to this clock signal generator, this clock signal generator is connected to this second charge pump to control this second charge pump.
Further, 3rd reference voltage generating circuit comprises the 4th PMOS transistor further, 5th PMOS transistor, 6th PMOS transistor, tenth nmos pass transistor, 11 nmos pass transistor and the tenth bi-NMOS transistor and the 13 nmos pass transistor, be connected with the 5th PMOS transistor grid after 4th PMOS transistor grid leak interconnection, tenth nmos pass transistor grid source is connected and is connected to the 4th PMOS transistor drain electrode, 11 nmos pass transistor grid source is connected and is connected to the tenth nmos transistor drain, also be connected to the 6th PMOS transistor grid simultaneously, 11 nmos transistor drain is connected to the tenth bi-NMOS transistor drain electrode, 5th PMOS transistor drain electrode is connected to the source electrode of the 8th PMOS transistor, and export the negative input end of the 3rd reference voltage to this comparer, 6th PMOS transistor drain electrode is connected to the 13 this drain electrode of nmos pass transistor, tenth bi-NMOS transistor and the 13 nmos pass transistor source ground, simultaneously, its grid is all connected to an enable signal.
Further, this first nmos pass transistor, the 5th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor, the 9th nmos pass transistor, the tenth nmos pass transistor and this 11 nmos pass transistor are Low threshold high-voltage tube.
Compared with prior art, a kind of voltage regulator circuit of the present invention, by realizing a reference voltage capable of fast starting, avoids use reference voltage source to produce problem that reference voltage can sacrifice stand-by power consumption, reduces power consumption.
Accompanying drawing explanation
Fig. 1 is the electrical block diagram of existing voltage stabilizer;
Fig. 2 is the detailed circuit diagram of a kind of voltage regulator circuit preferred embodiment of the present invention;
Fig. 3 is the circuit structure diagram of the first/the second reference voltage generating circuit in present pre-ferred embodiments.
Fig. 4 is the circuit structure diagram of the 3rd reference voltage generating circuit in present pre-ferred embodiments.
Embodiment
Below by way of specific instantiation and accompanying drawings embodiments of the present invention, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.The present invention is also implemented by other different instantiation or is applied, and the every details in this instructions also can based on different viewpoints and application, carries out various modification and change not deviating under spirit of the present invention.
Fig. 2 is the detailed circuit diagram of a kind of voltage regulator circuit preferred embodiment of the present invention.In present pre-ferred embodiments, this voltage regulator circuit is mainly used to carry out read operation to flash memory, therefore without the need to accurate especially.According to Fig. 2, a kind of voltage regulator circuit of the present invention comprises the first reference voltage generating circuit 201, first switch 202, first charge pump 203, control circuit 204, second reference voltage generating circuit 205, second switch 206, first electric capacity C1 and the second electric capacity C2.
First reference voltage generating circuit 201 exports the first reference voltage V R
1to the first switch 202, to control unlatching first switch 202, the first charge pump 203 is exported high pressure HV and is exported by the first switch 202; First charge pump 203 for exporting a high pressure HV under the control of charge pump enable signal PUMPENb, and high pressure HV produces the reference voltage VREF of read/write flash memory after the first switch 202; Two input ends of control circuit 204 are connected to the output terminal of the first charge pump 203, to produce the charge pump enable signal PUMPEN that controls the first charge pump 203 work under the effect of two input signals of its two input end; Second reference voltage generating circuit 205 is connected to outside read operation commencing signal ACT, and be connected to one of the first switch 202 and control circuit 204 input end by second switch 206, with under outside read operation commencing signal ACT effect, second reference voltage generating circuit 205 produces one second reference voltage V R2 and exports the reference voltage VREF producing read/write flash memory through the first switch 202, and controls control circuit 204; First electric capacity C1 mono-end is connected to the output terminal of the first charge pump 203, other end ground connection, second electric capacity C2 one end is connected to the first switch 202 and connects contrary one end with the first charge pump 203, other end ground connection, and the capacitance of the second electric capacity C2 is much larger than the capacitance of the first electric capacity C1, representative value is 50pF if the first electric capacity is C1, and the second electric capacity C2 is 150pF.
More particularly, first switch 202 is a metal-oxide-semiconductor switch, it is specially one first nmos pass transistor N1, this first nmos pass transistor N1 is Low threshold high-voltage tube, its grid is connected with the first reference voltage generating circuit 201, drain electrode is connected to the first charge pump 203 and second switch 206, and source electrode exports the reference voltage VREF of read/write flash memory, namely when the first reference voltage generating circuit 201 produces the first reference voltage V R
1time, a NMOS is through transistor N1 conducting, and the high pressure HV that the first charge pump 203 produces exports through the first nmos pass transistor N1, control circuit 204 comprises the first control signal and produces circuit 207, second control signal produces circuit 208 and rest-set flip-flop 209, wherein the first control signal produces the output terminal that circuit 201 lotus root is connected to the first charge pump 203, to produce the first control signal SET under the control exported at the first charge pump 203, second control signal produces the output terminal that circuit 208 lotus root is connected to the first charge pump 203, and be connected to the second reference voltage generating circuit 205 by second switch 206 lotus root, , to produce the second control signal RST under the control of the first charge pump 203 and the second reference voltage generating circuit 205, first control signal SET and the second control signal RST is then two input signals (R/S holds input signal) of rest-set flip-flop 209, these two input signals are after rest-set flip-flop 209, then produce the charge pump enable signal PUMPEN that control first charge pump 203 works, control the work of the first charge pump 203.
In present pre-ferred embodiments, first control signal produces circuit 207 and comprises the second nmos pass transistor N2, first PMOS transistor P1, 3rd nmos pass transistor N3, 4th nmos pass transistor N4, second PMOS transistor P2, first phase inverter D1 and the second phase inverter D2, wherein, second nmos pass transistor N2 grid leak connects and is connected to the output terminal of the first charge pump 203, source electrode is connected to the first PMOS transistor P1 source electrode, first PMOS transistor P1 grid connects power source voltage Vcc, drain electrode is connected to the drain electrode of the 3rd nmos pass transistor N3 and the input end of the first phase inverter D1, the output terminal of phase inverter D1 exports the first control signal SET, 3rd nmos pass transistor N3 source ground, grid is connected to the 4th nmos pass transistor N4 grid, the drain electrode of the second PMOS transistor P2 is connected to after 4th nmos pass transistor grid leak interconnection, second PMOS transistor source electrode connects power source voltage Vcc, grounded-grid, second control signal produces circuit 208 and comprises the 3rd PMOS transistor P3, 5th nmos pass transistor N5, 6th nmos pass transistor N6, second phase inverter D2 and the 3rd phase inverter D3, 5th nmos pass transistor is Low threshold high-voltage tube, the first charge pump 203 and second switch 206 is connect after the interconnection of its grid leak, source electrode is connected to the 3rd PMOS transistor P3 source electrode, 3rd PMOS transistor P3 grid connects supply voltage, drain electrode is connected to the input end of the 6th nmos pass transistor N6 drain electrode and the second phase inverter D2, 6th nmos pass transistor N6 grid is connected to the grid of the 4th nmos pass transistor N4 and the 3rd nmos pass transistor N3, source ground, second phase inverter D2 exports termination the 3rd phase inverter D3 input end, D3 output terminal exports the second control signal RST.
Coordinate Fig. 2 that the principle of work of the present invention is described continuation below: during beginning, the output HV of the first charge pump 203 is low, reference voltage VREF=" 0 ", now then the first control signal SET=" 1 ", second control signal RST=" 0 ", after rest-set flip-flop 209, charge pump enable signal PUMPENb=" 0 ", first charge pump 203 is worked, first reference voltage generating circuit 201 is started working, the work of the first reference voltage generating circuit 201 and the first charge pump 203 makes the first reference voltage V R1 and HV rise to predetermined high pressure, first reference voltage V R1 makes the first switch 202 open, then reference voltage VREF also rises to predetermined high pressure, and due to HV be high pressure, reference voltage VREF is also high pressure, then the first control signal SET=" 0 ", second control signal RST=" 1 ", like this after rest-set flip-flop 209, charge pump enable signal PUMPENb=" 1 ", this makes the first charge pump 203 not work, thus make the first control signal SET=" 1 ", and when outside read operation commencing signal ACT following closely arrives, it is " 1 " that the second reference voltage V R2 that second reference voltage generating circuit 205 produces then makes the second control signal RST still, thus charge pump enable signal PUMPENb keeps, simultaneously, second reference voltage V R2 exports the reference voltage VREF of read/write flash memory through the first switch 202.
Fig. 3 is the circuit structure diagram of the first/the second reference voltage generating circuit in present pre-ferred embodiments.According to Fig. 3, the first/the second reference voltage generating circuit comprises: the second charge pump 301, mu balanced circuit 302 and clock generator 303, mu balanced circuit 302 comprises the 7th nmos pass transistor N7 further, 8th nmos pass transistor N8, 9th nmos pass transistor N9 and comparer 304, the output terminal of the second charge pump 301 is connected to after 7th nmos pass transistor N7 grid leak interconnection, its source electrode is connected to the 8th nmos pass transistor N8 and drains, 8th nmos pass transistor N8 grid leak interconnection, source electrode is connected to the 9th nmos pass transistor N9 and drains, this source electrode is also connected to the positive input terminal of comparer 304 simultaneously, to provide sampled voltage VRD to comparer 304, 9th nmos pass transistor N9 grid leak interconnection, source ground, negative input termination 1 the 3rd reference voltage generating circuit of comparer 304, to receive the 3rd reference voltage V F, the output terminal of comparer 304 is connected to clock signal generator 303, clock signal generator 303 is connected to the second charge pump 301 and works to control the second charge pump 301, output reference voltage (VR1/VR2).It should be noted that, in present pre-ferred embodiments, seven/eight/nine nmos pass transistor N7/N8/N9 are preferably Low threshold high-voltage tube.
Fig. 4 is the circuit diagram of the 3rd reference voltage generating circuit in Fig. 3.According to Fig. 4, 3rd reference voltage generating circuit comprises further: the 4th PMOS transistor P4, 5th PMOS transistor P5, 6th PMOS transistor P6, tenth nmos pass transistor N10, 11 nmos pass transistor N11 and the tenth bi-NMOS transistor N12 and the 13 nmos pass transistor N13, wherein, tenth/11 nmos pass transistor N10/N11 is Low threshold high-voltage tube, four/five PMOS transistor P4/P5 source electrodes are all connected to power source voltage Vcc, be connected with the 5th PMOS transistor P5 grid after the interconnection of P4 grid leak, tenth nmos pass transistor N10 grid source is connected and is connected to the 4th PMOS transistor P4 drain electrode, 11 nmos pass transistor N11 grid source is connected and is connected to the tenth nmos pass transistor N10 and drains, also be connected to the 6th PMOS transistor P6 grid simultaneously, 11 nmos pass transistor N11 drain electrode is connected to the tenth bi-NMOS transistor N12 and drains, 5th PMOS transistor P5 drain electrode is connected to the source electrode of the 8th PMOS transistor P8, and export the negative input end of the 3rd reference voltage V F to comparer 304, 6th PMOS transistor drain electrode is connected to the 13 nmos pass transistor N13 and drains, 12/13 nmos pass transistor N12/N13 source ground, simultaneously, its grid is all connected to an enable signal EN.
Please with reference to Fig. 3 and Fig. 4, visible, reference voltage V R obtains by following calculating formula:
VR＝Vth0+Vdd+(1/x-1)Vt；
Wherein, Vth0 is the threshold voltage of the 7th nmos pass transistor N7, Vdd is that the 8th nmos pass transistor N8 drains and the 9th nmos pass transistor N9 drain terminal voltage, (1/x-1) Vt is the 3rd reference voltage V F, Vt is the threshold voltage of PMOS transistor, and wherein the representative value of x is 0.48, can obtain:
VR＝Vth0+Vdd+1.08*Vt。
Visible, a kind of voltage regulator circuit of the present invention passes through invention one reference voltage capable of fast starting, avoid the problem using reference voltage source generation reference voltage can sacrifice stand-by power consumption, reduce power consumption, because voltage regulator circuit of the present invention is mainly used to carry out read operation to flash memory, without the need to accurate especially, the reference voltage of generation meets actual requirement, and area is also very little.
Above-described embodiment is illustrative principle of the present invention and effect thereof only, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can carry out modifying to above-described embodiment and change.Therefore, the scope of the present invention, should listed by claims.
Claims (8)
1. a voltage regulator circuit, at least comprises:
First reference voltage generating circuit, for generation of one first reference voltage;
First charge pump, under the control of charge pump enable signal, produces a High voltage output;
First switch, is connected to this first reference voltage generating circuit and this first charge pump respectively, under controlling at this first reference voltage, the output of this first charge pump is produced reference voltage by this first switch and exports;
Control circuit, has two input ends, and this two input end is all connected to this first electric charge delivery side of pump, to produce this charge pump enable signal to control this first charge pump under the input signal effect of this two input end;
Second reference voltage generating circuit, be connected to outside read operation commencing signal, and be connected with this first switch and this control circuit, under the control at this outside read operation commencing signal, produce the second reference voltage export this reference voltage by this first switch and as one of this control circuit input signal; And
First electric capacity and the second electric capacity, between the output terminal that this first electric capacity is connected on this first charge pump and ground, the second electric capacity is connected between this first switch and ground.
2. voltage regulator circuit as claimed in claim 1, it is characterized in that: this first switch is the first nmos pass transistor, this the first nmos pass transistor grid is connected with this first reference voltage generating circuit, and drain electrode is connected to the output terminal of this first charge pump, and source electrode exports this reference voltage.
3. voltage regulator circuit as claimed in claim 2, it is characterized in that: this control circuit comprises the first control signal and produces circuit, the second control signal generation circuit and rest-set flip-flop, this first control signal produces circuit lotus root and is connected to this first electric charge delivery side of pump, to produce the first control signal under the control of the output of this first charge pump; This second control signal produces circuit and connects with this first charge pump and this second reference voltage generating circuit, to produce the second control signal under the output and the control of this second reference voltage of this first charge pump; Two input ends of this rest-set flip-flop are connected to this first control signal generation circuit respectively and this second control signal produces circuit, and its output terminal exports this charge pump enable signal.
4. voltage regulator circuit as claimed in claim 3, it is characterized in that: this first control signal produces circuit and comprises the second nmos pass transistor, first PMOS transistor, 3rd nmos pass transistor, 4th nmos pass transistor, second PMOS transistor and the first phase inverter, this the second nmos pass transistor grid leak connects and is connected to this first electric charge delivery side of pump, source electrode is connected to this first PMOS transistor source electrode, this the first PMOS transistor grid connects supply voltage, drain electrode is connected to the drain electrode of the 3rd nmos pass transistor and the input end of this first phase inverter, this first inverter output exports this first control signal, 3rd nmos pass transistor source ground, grid is connected to the 4th nmos pass transistor grid, the drain electrode of this second PMOS transistor is connected to after 4th nmos pass transistor grid leak interconnection, this the second PMOS transistor source electrode connects this supply voltage, grounded-grid.
5. voltage regulator circuit as claimed in claim 4, it is characterized in that: this second control signal produces circuit and comprises the 3rd PMOS transistor, 5th nmos pass transistor, 6th nmos pass transistor, second phase inverter and the 3rd phase inverter, this first charge pump and this second reference voltage generating circuit is connect after 5th nmos pass transistor grid leak interconnection, source electrode is connected to the 3rd PMOS transistor source electrode, 3rd PMOS transistor grid connects this supply voltage, drain electrode is connected to the input end of the 6th nmos transistor drain and this second phase inverter, 6th nmos pass transistor grid is connected to the 4th nmos pass transistor and the 3rd nmos pass transistor grid, source ground, this second inverter output connects the 3rd inverter input, 3rd inverter output exports this second control signal.
6. the voltage regulator circuit as described in claim 1 or 5, it is characterized in that: this first/the second reference voltage generating circuit comprises the second charge pump, mu balanced circuit and clock signal generator, wherein, this mu balanced circuit comprises the 7th nmos pass transistor, 8th nmos pass transistor, 9th nmos pass transistor and a comparer, this the second electric charge delivery side of pump is connected to after 7th nmos pass transistor grid leak interconnection, its source electrode is connected to the 8th nmos transistor drain, 8th nmos pass transistor grid leak interconnection, source electrode is connected to the 9th nmos transistor drain, 8th nmos pass transistor source electrode is also connected to the positive input terminal of this comparer simultaneously, to provide a sampled voltage to this comparer, 9th nmos pass transistor grid leak interconnection, source ground, negative input termination 1 the 3rd reference voltage generating circuit of this comparer, to receive the 3rd reference voltage, its output terminal is connected to this clock signal generator, this clock signal generator is connected to this second charge pump to control this second charge pump.
7. voltage regulator circuit as claimed in claim 6, it is characterized in that: the 3rd reference voltage generating circuit comprises the 4th PMOS transistor further, 5th PMOS transistor, 6th PMOS transistor, tenth nmos pass transistor, 11 nmos pass transistor and the tenth bi-NMOS transistor and the 13 nmos pass transistor, be connected with the 5th PMOS transistor grid after 4th PMOS transistor grid leak interconnection, tenth nmos pass transistor grid source is connected and is connected to the 4th PMOS transistor drain electrode, 11 nmos pass transistor grid source is connected and is connected to the tenth nmos transistor drain, also be connected to the 6th PMOS transistor grid simultaneously, 11 nmos transistor drain is connected to the tenth bi-NMOS transistor drain electrode, 5th PMOS transistor drain electrode is connected to the source electrode of the 6th PMOS transistor, and export the negative input end of the 3rd reference voltage to this comparer, 6th PMOS transistor drain electrode is connected to the 13 nmos transistor drain, tenth bi-NMOS transistor and the 13 nmos pass transistor source ground, simultaneously, its grid is all connected to an enable signal.
8. voltage regulator circuit as claimed in claim 7, is characterized in that: this first nmos pass transistor, the 5th nmos pass transistor, the 7th nmos pass transistor, the 8th nmos pass transistor, the 9th nmos pass transistor, the tenth nmos pass transistor and the 11 nmos pass transistor are Low threshold high-voltage tube.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102647082B (en) * | 2012-04-24 | 2017-02-08 | 上海华虹宏力半导体制造有限公司 | Negative voltage generation circuit |
| CN104464803B (en) * | 2013-09-18 | 2018-07-20 | 北京兆易创新科技股份有限公司 | A kind of generation device of read voltage, flash-memory storage system |
| CN104714584B (en) * | 2013-12-13 | 2016-04-06 | 芯视达系统公司 | There is voltage regulator and the control method thereof of multi output scope |
| US10401438B2 (en) * | 2016-03-08 | 2019-09-03 | Ablic Inc. | Magnetic sensor and magnetic sensor device |
| JP6797035B2 (en) * | 2016-03-08 | 2020-12-09 | エイブリック株式会社 | Magnetic sensor and magnetic sensor device |
| CN105843316B (en) * | 2016-05-31 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | Charge pump reference voltage adjusts circuit |
| CN109003634B (en) * | 2017-06-06 | 2021-09-24 | 合肥格易集成电路有限公司 | Chip starting method and FLASH chip |
| CN108320762B (en) * | 2018-04-12 | 2019-02-22 | 武汉新芯集成电路制造有限公司 | Charge pump drive circuit |
| CN114167929B (en) * | 2020-09-11 | 2023-03-24 | 兆易创新科技集团股份有限公司 | Voltage generating circuit and electronic device |
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| US6188212B1 (en) * | 2000-04-28 | 2001-02-13 | Burr-Brown Corporation | Low dropout voltage regulator circuit including gate offset servo circuit powered by charge pump |
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