CN106094957B - A kind of voltage regulator circuit and RFID chip - Google Patents
A kind of voltage regulator circuit and RFID chip Download PDFInfo
- Publication number
- CN106094957B CN106094957B CN201610715418.XA CN201610715418A CN106094957B CN 106094957 B CN106094957 B CN 106094957B CN 201610715418 A CN201610715418 A CN 201610715418A CN 106094957 B CN106094957 B CN 106094957B
- Authority
- CN
- China
- Prior art keywords
- transistor
- voltage
- pull
- current
- bias current
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The embodiment of the present invention provides a kind of voltage regulator circuit and RFID chip, in voltage regulator circuit, tie point includes the power transistor being sequentially connected in series, reference voltage transistor, enabled transistor and the first pull-down transistor, second branch road includes driving transistor and the second pull-down transistor being sequentially connected in series, and by constant-current source it is driving transistor and the first pull-down transistor, second pull-down transistor provides bias current, the current output terminal of driving transistor is connected to the grid end of power transistor, so, the voltage of voltage output end is related to the gate source voltage of reference voltage transistor, and keep constant by the electric current of reference voltage transistor by constant-current source control, so as to realize the stabilization of the gate source voltage of reference voltage transistor.In addition, in output end, output voltage values are determined using reference voltage and source class follower, reaches the purpose for reducing output impedance, without increasing extra circuit, reduces the complexity of whole circuit design.
Description
Technical field
The present invention relates to electronic circuit design field, more particularly to a kind of voltage regulator circuit and RFID chip.
Background technology
Passive RFID (Radio Frequency Identification, radio frequency identification) label chip, by RF energy
Electric energy is converted to, without built-in power, there is small volume, in light weight, the low one-level service life of cost is long, extensive use
In the various fields such as bank card, supply chain management, gate inhibition, public transit system.
In passive RFID tag chip, in order to save chip area and reduce chip power-consumption, digital control circuit is main
It is made up of low-voltage device, in order to ensure the power supply of digital control circuit part, it usually needs the power supply of increase low pressure output is steady
Volt circuit (Ldo), it is powered for digital control circuit part.
Traditional power supply stabilization circuit mainly has the outer electric capacity resistive degeneration structure of piece and without electric capacity resistive degeneration outside piece
Network structure, it is connected, it is necessary to carry out contact with electric capacity outside piece in the outer electric capacity resistive degeneration structure of piece, is not suitable for RFID chip
Non-contact application in, and for without in electric capacity resistive degeneration structure outside piece, it usually needs increase extra circuit module, come
The performances such as voltage stabilization are realized, increase the complexity of circuit design.
The content of the invention
The invention provides a kind of voltage regulator circuit and RFID chip, by controlling the electric current by reference voltage transistor
To realize regulated output voltage, circuit structure is simple and is easily achieved.
The invention provides a kind of voltage regulator circuit, including tie point, the second branch road, constant-current source and the first electric capacity；
Wherein,
Tie point includes the power transistor, reference voltage transistor, enabled transistor and first being sequentially connected in series
Pull-down transistor, power transistor one end connection supply voltage of tie point, first pull-down transistor one end ground connection, with reference to electricity
The grid end connection reference voltage of piezoelectric crystal, enable the grid end connection enable signal of transistor；
Second branch road includes driving transistor and the second pull-down transistor being sequentially connected in series, and the driving of the second branch road is brilliant
Body pipe one end connection supply voltage, second pull-down transistor one end ground connection；
Constant-current source is respectively that driving transistor and the first pull-down transistor, the second pull-down transistor provide bias current, is driven
The current output terminal of dynamic transistor is connected to the grid end of power transistor；
The common port of power transistor and reference voltage transistor is voltage output end.
Alternatively, constant-current source includes：
For the first transistor of the type of attachment of mirror image diode, the first transistor connection input current, and respectively the
Three transistors and the 4th transistor provide the bias current of mirror image；
The 7th transistor being connected with third transistor, bias current is provided from third transistor to the 7th transistor；
The 8th transistor being connected with the 4th transistor, bias current is provided from the 4th transistor to the 8th transistor；
For the 5th transistor of the type of attachment of mirror image diode, the 5th transistor connects the 9th transistor, the 9th crystal
7th transistor of the type of attachment of Guan Youwei mirror image diodes provides bias current, is carried from the 5th transistor to driving transistor
For the bias current of mirror image；
8th transistor is the type of attachment of mirror image diode, is provided for the first pull-down transistor and the second pull-down transistor
The bias current of mirror image.
Alternatively, constant-current source also includes：
The second transistor of the bias current of mirror image is provided by the first transistor；
The tenth transistor and the 6th transistor of concatenation, from second transistor to the tenth transistor of concatenation and the 6th crystal
Pipe provides bias current；
With the 11st transistor of the 7th transistor series connection, from third transistor to the 7th transistor of concatenation and the 11st
Transistor provides bias current, the 7th transistor of concatenation and the type of attachment that the 11st transistor is mirror image diode；
With the tenth two-transistor of the 8th transistor series connection, from the 4th transistor to the 8th transistor of concatenation and the 12nd
Transistor provides bias current, the 8th transistor of concatenation and the type of attachment that the tenth two-transistor is mirror image diode；
With the 13rd transistor of the 9th transistor series connection, the 5th transistor the 13rd transistor that is sequentially connected in series of connection and
9th transistor；
The 14th transistor concatenated with the second pull-down transistor, from driving transistor to the second pull-down transistor of concatenation
Bias current is provided with the 14th transistor；
Tenth transistor of concatenation and the grid end of the 6th transistor are connected respectively to the current output terminal of second transistor, point
Bias voltage is not provided to the grid end of the 11st transistor, the tenth two-transistor, the 13rd transistor and the 14th transistor.
Alternatively, it is also associated with concatenating between common port and voltage output end of the driving transistor with the 14th transistor
First resistor and the second electric capacity.
Alternatively, the 3rd electric capacity connected between the grid end of voltage output end and the 9th transistor.
In addition, present invention also offers a kind of RFID chip, using any of the above-described voltage regulator circuit.The embodiment of the present invention
The voltage regulator circuit and RFID chip of offer, in voltage regulator circuit, tie point includes the power crystal being sequentially connected in series
Pipe, reference voltage transistor, enabled transistor and the first pull-down transistor, the driving that the second branch road includes being sequentially connected in series are brilliant
Body pipe and the second pull-down transistor, and be that driving transistor and the first pull-down transistor, the second pull-down transistor carry by constant-current source
For bias current, the current output terminal of driving transistor is connected to the grid end of power transistor, so, the voltage of voltage output end
It is related to the gate source voltage of reference voltage transistor, and kept not by the electric current of reference voltage transistor by constant-current source control
Become, so as to realize the stabilization of the gate source voltage of reference voltage transistor.In addition, in output end, using reference voltage and source class with
Output voltage values are determined with device, reaches the purpose for reducing output impedance, without increasing extra circuit, reduces whole circuit
The complexity of design.
Brief description of the drawings
In order to illustrate more clearly of the technical scheme in the embodiment of the present application, make required in being described below to embodiment
Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present application, for
For those of ordinary skill in the art, without having to pay creative labor, it can also be obtained according to these accompanying drawings
His accompanying drawing.
Fig. 1 is the electrical block diagram according to the voltage regulator circuit of the embodiment of the present invention；
The output of voltage output end when Fig. 2 is under condition of different temperatures, different process corner condition, different supply voltages
Voltage waveform view；
Fig. 3 be under condition of different temperatures, different process corner condition, different supply voltages when, load current change when
The output voltage waveforms schematic diagram of voltage output end.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present application, the technical scheme in the embodiment of the present application is carried out clear, complete
Site preparation describes, it is clear that described embodiment is only some embodiments of the present application, rather than whole embodiments.It is based on
Embodiment in the application, those of ordinary skill in the art are obtained every other under the premise of creative work is not made
Embodiment, belong to the scope of the application protection.
The embodiment of the present invention proposes a kind of voltage regulator circuit, with reference to shown in figure 1, including tie point 100, the second branch road
110th, the electric capacity C2 of constant-current source 120 and first；Wherein,
Tie point 100 includes the power transistor Mp, reference voltage transistor Mp7, enabled crystal being sequentially connected in series
Pipe Mn12 and the first pull-down transistor Mn11, power transistor Mp one end connection supply voltage Avdd of tie point 100, first
Pull-down transistor Mn11 one end is grounded Agnd, reference voltage transistor Mp7 grid end connection reference voltage Vref, enables transistor
Mn12 grid end connection enable signal pdb；
Second branch road 110 includes the driving transistor Mp6 that is sequentially connected in series and the second pull-down transistor Mn10, second
Driving transistor Mp6 one end connection supply voltage Avdd, second pull-down transistor one end ground connection Agnd on road 110；
Constant-current source 120 provides partially for driving transistor Mp6 and the first pull-down transistor Mn11, the second pull-down transistor Mn10
Electric current is put, driving transistor Mp6 current output terminal is connected to power transistor Mp grid end；
Power transistor Mp and reference voltage transistor Mp7 common port is voltage output end E.
In the present invention, the voltage of voltage output end is related to the gate source voltage of reference voltage transistor, and passes through constant current
Source control keeps constant by the electric current of reference voltage transistor, so as to realize the steady of the gate source voltage of reference voltage transistor
It is fixed.In addition, in output end, output voltage values are determined using reference voltage and source class follower, reaching reduces output impedance
Purpose, without increasing extra circuit, reduce the complexity of whole circuit design.
Technical scheme for a better understanding of the present invention and technique effect, carried out below with reference to specific embodiment detailed
Thin explanation.
In this embodiment, as shown in figure 1, power transistor Mp, reference voltage transistor Mp7 are PMOS transistor,
Reference voltage transistor Mp7, enabled transistor Mn12, the first pull-down transistor Mn11 and the second pull-down transistor Mn10 are
Nmos pass transistor.
For tie point, power transistor Mp source connection supply voltage Avdd, drain terminal connection reference voltage crystal
Pipe Mp7 source, reference voltage transistor Mp7 source are voltage output end E, the voltage of output voltage stabilizer circuit, with reference to electricity
Piezoelectric crystal Mp7 source is connected to enabled transistor M12 drain terminal, and enabled transistor Mn12 source is connected to the first drop-down
Transistor Mn11 drain terminal, the first pull-down transistor Mn11 source ground connection.For the second branch road, driving transistor Mp6 source
End connection supply voltage Avdd, drain terminal connect the second pull-down transistor Mn10 drain terminal, the second pull-down transistor Mn10 source
Ground connection.
Wherein, reference voltage transistor Mp7 grid end connection reference voltage Vref, enables transistor Mn12 grid end connection
Enable signal pdb, driving transistor Mp6 drain terminal driving power transistor Mp grid end, driving transistor Mp6 are carried by constant-current source
For bias current, the first pull-down transistor M11 and the second pull-down transistor M10 also provide bias current, constant-current source by constant-current source
The current value of the bias current of offer is substantially fixed.Enable signal pdb can be the signal from control module, need
When voltage regulator circuit exports so that enable signal pdb is effective, and its general value can be Avdd so that at enabled transistor Mn12
In conducting state, reference voltage Vref is held essentially constant, and is typically produced by band-gap reference module.
So, when enable signal pdb is effective, due under driving transistor Mp6, the first pull-down transistor Mn11 and second
Pull transistor Mn10 turn on current value is fixed, and the first pull-down transistor Mn11, the second pull-down transistor Mn10 electric conduction
Flow valuve is equal with driving transistor Mp6, reference voltage transistor Mp7 turn on current value, therefore flows through reference voltage transistor
Mp7 current value is also substantially stationary constant, so as to ensure that reference voltage transistor Mp7 gate source voltage Vgs keeps solid
It is fixed constant, and voltage output end E output voltage Vout is equal to reference voltage Vref and Vgs sums, ensure that voltage output end
Output voltage Vout stability.
First electric capacity C2 serves compensating action to the phase margin of loop, improves the stability of loop, while can also carry
The transient response speed of high circuit.
In the present invention, can be respectively driving transistor and the first pull-down transistor, second using suitable constant-current source
Pull-down transistor provides bias current.In this embodiment, constant-current source provides for the circuit mirror current of multistage, with reference to the institute of figure 1
Show, constant-current source includes：
For the first transistor Mp1 of the type of attachment of mirror image diode, the first transistor Mp1 connection input current Ibp, and
Respectively third transistor Mp3 and the 4th transistor Mp4 provides the bias current of mirror image；
The 7th transistor Mn4 being connected with third transistor Mp3, is provided from third transistor Mp3 to the 7th transistor Mn4
Bias current；
The 8th transistor Mn6 being connected with the 4th transistor Mp4, provided from the 4th transistor Mp4 to the 8th transistor inclined
Put electric current Mn6；
For the 5th transistor Mp5 of the type of attachment of mirror image diode, the transistor Mn8 of the 5th transistor Mp5 connections the 9th,
9th transistor Mn8 provides bias current by the 7th transistor Mn4 of the type of attachment for mirror image diode, by the 5th transistor
Mp5 provides the bias current of mirror image to driving transistor Mp6；
8th transistor Mn6 is the type of attachment of mirror image diode, is the first pull-down transistor Mn10 and second time crystal pulling
Body pipe Mn11 provides the bias current of mirror image.
In embodiment, as shown in figure 1, more preferably, constant-current source also includes：
Second transistor Mp2, the bias current of mirror image is provided from the first transistor Mp1 to second transistor Mp2；
The tenth transistor Mn1 and the 6th transistor Mn2 of concatenation, from second transistor Mp2 to the tenth transistor of concatenation
Mn1 and the 6th transistor Mn2 provides bias current；
The 11st transistor Mn3 concatenated with the 7th transistor Mn4, from third transistor Mp3 to the 7th crystal of concatenation
Pipe Mn4 and the 11st transistor Mn3 provides bias current, and the 7th transistor Mn4 of concatenation and the 11st transistor Mn3 are mirror image
The type of attachment of diode；
The tenth two-transistor Mn5 concatenated with the 8th transistor Mn6, from the 4th transistor Mp4 to the 8th crystal of concatenation
Pipe Mn6 and the tenth two-transistor Mn5 provides bias current, and the 8th transistor Mn6 of concatenation and the tenth two-transistor Mn5 are mirror image
The type of attachment of diode；
The 13rd transistor Mn7 concatenated with the 9th transistor Mn8, the 5th transistor Mp5 connections be sequentially connected in series the tenth
Three transistor Mn7 and the 9th transistor Mn8；
The 14th transistor Mn9 concatenated with the second pull-down transistor Mn10, from driving transistor Mp6 to the second of concatenation
Pull-down transistor Mn10 and the 14th transistor Mn9 provides bias current；
The tenth transistor Mn1 and the 6th transistor Mn2 of concatenation are respectively to the 11st transistor Mn3, the tenth two-transistor
Mn5, the 13rd transistor Mn7 and the 14th transistor Mn9 grid end provide bias voltage.
In this preferred embodiment, the first transistor Mp1, second transistor Mp2, third transistor Mp3, the 4th crystal
Pipe Mp4 and the 5th transistor Mp5 is PMOS transistor, the 6th transistor Mn2, the 7th transistor Mn4, the 8th transistor Mn6,
Nine transistor Mn8, the tenth transistor Mn1, the 11st transistor Mn3, the tenth two-transistor Mn5, the 13rd transistor Mn7 and
14 transistor Mn9 are nmos pass transistor.
The first transistor Mp1 is the type of attachment of mirror image diode, will when the first transistor Mp1 is PMOS transistor
The first transistor Mp1 grid end is connected to drain terminal, and drain terminal connection input current, source connection supply voltage, first crystal
Pipe Mp1 grid end is connected respectively to second transistor Mp2, third transistor Mp3, the 4th transistor Mp4 grid end, the second crystal
Pipe Mp2, third transistor Mp3, the 4th transistor Mp4 source connection supply voltage, so, the first transistor Mp1 respectively with
Second transistor Mp2, third transistor Mp3, the circuit that the 4th transistor Mp4 is mirror current source connect, by the first transistor
Mp1 provides the bias current of mirror image to second transistor Mp2, third transistor Mp3, the 4th transistor Mp4 respectively, so as to second
Transistor Mp2, third transistor Mp3, the 4th transistor Mp4 export of substantially equal electric current respectively.And second transistor Mp2
The tenth transistor Mn1 and the 6th transistor Mn2 of drain terminal connection concatenation, in the present embodiment, the tenth transistor Mn1 of concatenation and the
Six transistor Mn2 are nmos pass transistor pair, and the tenth transistor Mn1 source connects the 6th transistor Mn2 drain terminal, the 6th crystal
Pipe Mn2 source ground connection, so, in the tenth transistor Mn1 and the 6th transistor Mn2 that second transistor Mp2 connections concatenate
In branch road, the electric current of second transistor Mp2 outputs provides biased electrical to the tenth transistor Mn1 of concatenation and the 6th transistor Mn2
Stream；With the tenth transistor Mn1 and the 6th transistor Mn2 of second transistor Mp2 connections concatenation branch road, third transistor Mp3
Connect the 11st transistor Mn3 and the 7th transistor Mn4 of concatenation, the tenth two-transistor of the 4th transistor Mp4 connections concatenation
Mn5 and the 8th transistor Mn6.
5th transistor Mp5 is also the type of attachment of mirror image diode, when the 5th transistor Mp5 is PMOS transistor, i.e.,
5th transistor Mp5 grid end is connected to drain terminal, and drain terminal connection input current, source connection supply voltage, the 5th is brilliant
Body pipe Mp5 grid end is connected to driving transistor Mp6 grid end, and the circuit that mirror current source is formed with driving transistor is connected,
The bias current of mirror image is provided for driving transistor Mp6, with the tenth transistor Mn1 and the of second transistor Mp2 connections concatenation
Six transistor Mn2 branch road, the 13rd transistor Mn7 and the 9th transistor of the 5th transistor Mp5 drain terminal connection concatenation
Mn8.The electric current of driving transistor Mp6 outputs is substantially identical with the bias current of branch road where the 5th transistor.With the second crystal
The tenth transistor Mn1 and the 6th transistor Mn2 of pipe Mp2 connections concatenation branch road, driving transistor Mp6 drain terminal connection concatenation
The 14th transistor Mn9 and the first pull-down transistor Mn10.
In addition, the tenth transistor Mn1 and the 6th transistor Mn2 of concatenation grid end are connected respectively to second transistor Mp2
Current output terminal, it is brilliant to the 11st transistor Mn3, the tenth two-transistor Mn5, the 13rd transistor Mn7 and the 14th respectively
Body pipe Mn9 grid end provides bias voltage, and in the present embodiment, second transistor Mp2 current output terminal is drain terminal；The of concatenation
11 transistor Mn3 and the 7th transistor Mn4 are the type of attachment of mirror image diode, and are the 9th brilliant by the 7th transistor Mn4
Body pipe Mn8 provides the bias current of mirror image, in the specific connection of the present embodiment, i.e., connects the 7th transistor Mn4 grid end
To third transistor Mp3 current output terminal, namely the 11st transistor Mn3 drain terminal, so, carried for the 9th transistor Mn8
It is essentially identical for the bias current and electric current that the 4th transistor Mp4 is exported of mirror image；Similarly, the tenth two-transistor of concatenation
Mn5 and the 8th transistor Mn6 is also the type of attachment of mirror image diode, and is the first pull-down transistor by the 8th transistor Mn6
Mn11 and the second pull-down transistor Mn10 provides the bias current of mirror image, is under the first pull-down transistor Mn11 and second so
The bias current of pull transistor Mn10 offer mirror images and the electric current that third transistor Mp3 is exported are essentially identical, and driving transistor
Mp6 bias current and the 5th transistor Mp5 bias current are image current, and input current Ibp is metastable inclined
Put electric current so that driving transistor Mp6, the first pull-down transistor Mn11 and the current value of the second pull-down transistor Mn10 conductings are consolidated
It is fixed, and the first pull-down transistor Mn11 and the second pull-down transistor Mn10 and driving transistor Mp6, reference transistor Mp7 are led
Energization flow valuve is of substantially equal, then, it is also substantially changeless by reference transistor Mp7 current values, so as to ensure that ginseng
The gate source voltage Vgs for examining transistor Mp7 keeps stabilization that is stable, and then ensureing the output voltage Vout of whole voltage regulator circuit
Property.
In this preferred embodiment, transistors of these above-mentioned concatenations help further to improve image current accurate
Property, and then ensure essentially identical to the first pull-down transistor Mn11, the second pull-down transistor Mn10 and driving transistor Mp6 offer
Bias current.
In addition, it is also connected between driving transistor Mp6 and the 14th transistor Mn9 common port and voltage output end E
There are the first resistor R and the second electric capacity C1 of concatenation, and further, in voltage output end E and the 9th transistor Mn8 grid end
Between the 3rd electric capacity C3 that connects.Second electric capacity C1 serves compensating action to the phase margin of loop, improves the stabilization of loop
Property, while can also improve the transient response speed of circuit.
Primarily to further improving the transient response speed of voltage regulator circuit, its operation principle is 3rd electric capacity C3,
When output loading increases, power transistor Mp grid ends voltage can not be mutated so that output voltage Vout is reduced, due to the 3rd electricity
Hold C3 AC coupled effect so that the 9th transistor Mn8 grid end voltage reduces, and then driving transistor Mp6 electric conduction
Stream decreases, simultaneously as output voltage Vout is reduced, and reference voltage Vref keeps constant, and reference transistor Mp7's leads
Galvanization can decrease, and the first pull-down transistor M11 and the second pull-down transistor M10 electric currents keep constant, therefore, reference
Transistor Mp7 gate source voltage can be reduced due to the imbalance of electric current, and certain benefit is played in the reduction to output voltage Vout
The effect of repaying.Same reason, when output loading reduces, mitigation can be played to output voltage Vout rising, thus come
Improve speed of the output voltage due to whole transient response when load changes.
With reference to shown in figure 2, the simulation waveform schematic diagram of the output voltage of voltage output end when changing for different parameters, change
Parameter include different temperatures, different process angle and different electrical power voltage, wherein, temperature be respectively -40 DEG C, 25 DEG C, 85 DEG C, electricity
Source voltage is respectively the simulation waveform schematic diagram of the output voltage in the case of 1.8V, 3.3V and 5V, from diagram it can be seen that, it is defeated
Go out voltage control between 1.49V to 1.64V, output voltage meets in design objective and exported in the range of 1.5V ± 10%
The requirement of the excursion of voltage.
With reference to shown in figure 3, the simulation waveform schematic diagram of the output voltage changed when changing for different parameters with load current,
The parameter of change includes different temperatures, different process angle and different electrical power voltage, wherein, temperature be respectively -40 DEG C, 25 DEG C, 85
DEG C, supply voltage is respectively 1.8V, 3.3V and 5V, and load current changes in the range of 50uA to 15mA, rising and falling time
For 10ns, load capacitance 100pF.It can see from emulation schematic diagram, under the worst case of load changing, output voltage
Stationary value can also be reached within 2us time, the requirement of design objective and engineer applied can be met.
The voltage regulator circuit of the embodiment of the present invention is described above, the voltage regulator circuit is particularly suitable in RFID
Application in chip, stable supply voltage is provided for digital control circuit part.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply and deposited between these entities or operation
In any this actual relation or order.Moreover, term " comprising ", "comprising" or its any other variant are intended to
Nonexcludability includes, so that process, method, article or equipment including a series of elements not only will including those
Element, but also the other element including being not expressly set out, or it is this process, method, article or equipment also to include
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Other identical element also be present in process, method, article or equipment including the key element.
Claims (6)
1. a kind of voltage regulator circuit, it is characterised in that including tie point, the second branch road, constant-current source and the first electric capacity；Its
In,
Tie point includes power transistor, reference voltage transistor, enabled transistor and the first drop-down being sequentially connected in series
Transistor, power transistor one end connection supply voltage of tie point, first pull-down transistor one end ground connection, reference voltage are brilliant
The grid end connection reference voltage of body pipe, enable the grid end connection enable signal of transistor；
Second branch road includes driving transistor and the second pull-down transistor being sequentially connected in series, the driving transistor of the second branch road
One end connection supply voltage, second pull-down transistor one end ground connection；
Constant-current source is respectively that driving transistor and the first pull-down transistor, the second pull-down transistor provide bias current, and driving is brilliant
The current output terminal of body pipe is connected to the grid end of power transistor；
The common port of power transistor and reference voltage transistor is voltage output end.
2. voltage regulator circuit according to claim 1, it is characterised in that constant-current source includes：
For the first transistor of the type of attachment of mirror image diode, the first transistor connection input current, and the respectively the 3rd crystalline substance
Body pipe and the 4th transistor provide the bias current of mirror image；
The 7th transistor being connected with third transistor, bias current is provided from third transistor to the 7th transistor；
The 8th transistor being connected with the 4th transistor, bias current is provided from the 4th transistor to the 8th transistor；
For the 5th transistor of the type of attachment of mirror image diode, the 5th transistor connects the 9th transistor, the 9th transistor by
The 7th transistor for the type of attachment of mirror image diode provides bias current, and mirror is provided from the 5th transistor to driving transistor
The bias current of picture；
8th transistor is the type of attachment of mirror image diode, and mirror image is provided for the first pull-down transistor and the second pull-down transistor
Bias current.
3. voltage regulator circuit according to claim 2, constant-current source also include：
The second transistor of the bias current of mirror image is provided by the first transistor；
The tenth transistor and the 6th transistor of concatenation, are carried from second transistor to the tenth transistor of concatenation and the 6th transistor
For bias current；
With the 11st transistor of the 7th transistor series connection, from third transistor to the 7th transistor of concatenation and the 11st crystal
Pipe provides bias current, the 7th transistor of concatenation and the type of attachment that the 11st transistor is mirror image diode；
With the tenth two-transistor of the 8th transistor series connection, from the 4th transistor to the 8th transistor of concatenation and the 12nd crystal
Pipe provides bias current, the 8th transistor of concatenation and the type of attachment that the tenth two-transistor is mirror image diode；
The 13rd transistor and the 9th being sequentially connected in series with the 13rd transistor of the 9th transistor series connection, the connection of the 5th transistor
Transistor；
The 14th transistor concatenated with the second pull-down transistor, from driving transistor to the second pull-down transistor of concatenation and
14 transistors provide bias current；
Tenth transistor of concatenation and the grid end of the 6th transistor are connected respectively to the current output terminal of second transistor, respectively to
11st transistor, the tenth two-transistor, the grid end of the 13rd transistor and the 14th transistor provide bias voltage.
4. voltage regulator circuit according to claim 3, it is characterised in that in driving transistor and the public affairs of the 14th transistor
End and the first resistor for being also associated with concatenating between voltage output end and the second electric capacity altogether.
5. the voltage regulator circuit according to claim 3 or 4, it is characterised in that in voltage output end and the 9th transistor
The 3rd electric capacity connected between grid end.
6. a kind of RFID chip, it is characterised in that including the voltage regulator circuit as any one of claim 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610715418.XA CN106094957B (en) | 2016-08-24 | 2016-08-24 | A kind of voltage regulator circuit and RFID chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610715418.XA CN106094957B (en) | 2016-08-24 | 2016-08-24 | A kind of voltage regulator circuit and RFID chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106094957A CN106094957A (en) | 2016-11-09 |
| CN106094957B true CN106094957B (en) | 2018-04-10 |
Family
ID=57224892
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610715418.XA Active CN106094957B (en) | 2016-08-24 | 2016-08-24 | A kind of voltage regulator circuit and RFID chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106094957B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111221369B (en) * | 2018-11-23 | 2022-01-07 | 比亚迪半导体股份有限公司 | Low dropout linear regulator |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070164810A1 (en) * | 2006-01-16 | 2007-07-19 | Yin-Chang Chen | Regulator circuit |
| CN101552560A (en) * | 2009-01-13 | 2009-10-07 | 成都芯源系统有限公司 | Switch voltage-stabilizing circuit and control method thereof |
| CN101556481A (en) * | 2009-05-05 | 2009-10-14 | 中国科学院上海微系统与信息技术研究所 | Precisely matched image current source circuit |
| CN202067171U (en) * | 2011-04-25 | 2011-12-07 | 上海集成电路研发中心有限公司 | Low dropout linear regulator |
| CN102455728A (en) * | 2010-10-25 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Current control circuit |
-
2016
- 2016-08-24 CN CN201610715418.XA patent/CN106094957B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070164810A1 (en) * | 2006-01-16 | 2007-07-19 | Yin-Chang Chen | Regulator circuit |
| CN101552560A (en) * | 2009-01-13 | 2009-10-07 | 成都芯源系统有限公司 | Switch voltage-stabilizing circuit and control method thereof |
| CN101556481A (en) * | 2009-05-05 | 2009-10-14 | 中国科学院上海微系统与信息技术研究所 | Precisely matched image current source circuit |
| CN102455728A (en) * | 2010-10-25 | 2012-05-16 | 三星半导体(中国)研究开发有限公司 | Current control circuit |
| CN202067171U (en) * | 2011-04-25 | 2011-12-07 | 上海集成电路研发中心有限公司 | Low dropout linear regulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106094957A (en) | 2016-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN108803761B (en) | LDO circuit that contains high-order temperature compensation | |
| CN205945737U (en) | NFC chip with power management module | |
| CN105242734B (en) | A kind of high power LD O circuit without external electric capacity | |
| CN102707754A (en) | Low dropout regulator | |
| CN103095226B (en) | Integrated circuit | |
| CN109710017B (en) | Low-dropout linear voltage regulator system | |
| CN105867506A (en) | LDO (low dropout regulator) with internal reference voltage | |
| CN111638744B (en) | Current frequency conversion circuit | |
| CN100479027C (en) | Display device | |
| CN114200994B (en) | Low dropout linear regulator and laser ranging circuit | |
| CN107272818A (en) | A kind of high voltage band-gap reference circuit structure | |
| CN106125818B (en) | A kind of power-supply circuit and its control method | |
| CN104460807A (en) | Low-dropout linear regulator with self-adaptive reference buffer | |
| CN103472880B (en) | Low dropout regulator | |
| CN108594924A (en) | A kind of band-gap reference voltage circuit of super low-power consumption whole CMOS subthreshold work | |
| CN106094957B (en) | A kind of voltage regulator circuit and RFID chip | |
| CN106647911A (en) | Multifunctional LDO circuit applicable to low-power-consumption RFID reader | |
| CN106055011A (en) | Self-startup power supply circuit | |
| CN110192163A (en) | Voltage regulator | |
| CN116865730A (en) | High-voltage wide-input-range voltage comparator with negative feedback | |
| CN110389614A (en) | Efficient low-pressure difference voltage-stablizer | |
| CN110502056A (en) | A kind of threshold voltage reference circuit | |
| CN203643886U (en) | Band-gap reference source circuit and band-gap reference source | |
| CN106209029B (en) | Ring oscillator | |
| US6417655B2 (en) | Common mode bias voltage generator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |