CN110618742A - PDB board and working method thereof - Google Patents

Abstract

The application discloses a PDB board and its working method. The PDB board includes N 48V‑12V modules connected in parallel and a delay control module. Any 48V‑12V module is connected to the delay control module through a PMBUS interface. The input end of a 48V‑12V module is connected to the PSU, and the output end is connected to the motherboard. The delay control module is used to set the delay time in the designated register of the 48V-12V module, and start N parallel-connected 48V-12V modules in sequence according to the delay time. The working method of the PDB board includes: obtaining the 48V voltage from the PSU; using the delay control module to configure the delay time in the designated register of any one of the 48V-12V modules in turn; starting N parallel connected 48V- 12V module, obtain 12V voltage; send 12V voltage to the main board. Through the present application, time-sharing start can be realized, the phenomenon of current overshoot can be effectively avoided, and the stability of the output voltage of the PDB board can be improved.

Description

A kind of PDB board and working method thereof

technical field

The present application relates to the technical field of power conversion, in particular to a PDB (Power Distribution Board, power distribution board) board and a working method thereof.

Background technique

The 48V power supply architecture is more and more widely used in the fields of communication, automotive power supply, data center and AI server. When the 48V power supply architecture is applied in these fields, it is usually necessary to convert the 48V power supply to a 12V power supply. Taking the AI (Artificial Intelligence, artificial intelligence) server field as an example, 8GPU (Graphics Processing Unit, graphics processing unit) or even 16GPU is usually used to build a large-scale artificial intelligence deep learning platform, and the power consumption of GPU accounts for the total power consumption of the server. The ratio reaches 70%. In order to meet the power supply requirements, server platforms equipped with these GPUs usually adopt a 48V power supply architecture. Specifically, the PSU (Power Supply Unit, power supply unit) outputs 48V DC (Direct Current, DC power supply) to the server, and the 48V power supply can be directly supplied to the GPU, but components other than the GPU, such as CPU, memory, hard disk, etc. If the voltage is lower than 48V, the PDB board is used to step down the 48V power supply to obtain a 12V power supply, and then the 12V power supply is connected to the CPU, memory, hard disk and other components.

The current PDB board usually uses multi-level 48V-12V modules in parallel in order to output higher power. The input voltage of the multi-level 48V-12V module is 48V, and the 12V voltage is obtained after being processed by the PDB board.

However, when the current PDB boards are connected in parallel with multi-level modules, due to the individual differences between 48V-12V modules, the working states of the 48V-12V modules will not be completely synchronized during the soft start stage, and the slower 48V-12V modules will start. The module will have a backflow current, and the 48V-12V module that starts faster will output a larger current. Therefore, the output current of different 48V-12V modules is uneven, the output voltage stability is poor, and a large output current may even cause current overshoot.

Contents of the invention

The present application provides a PDB board and its working method, so as to solve the problem in the prior art that the output voltage stability of the PDB board is poor, and the current overshoot is easily caused during the startup process.

In order to solve the above technical problems, the embodiment of the present application discloses the following technical solutions:

A kind of PDB board, described PDB board comprises: N 48V-12V modules connected in parallel and a delay control module, pass PMBUS (Power Management Bus, power supply between any described 48V-12V module and delay control module) Management bus) interface communication connection, the input end of any one of the 48V-12V modules is connected to the PSU, and the output end of any one of the 48V-12V modules is connected to the main board, wherein N is a natural number and N≥2;

The 48V-12V module is used to convert the 48V voltage from the PSU into a 12V voltage and transmit it to the main board;

The delay control module is used to set the delay time in the designated register of the 48V-12V module, and start N parallel-connected 48V-12V modules sequentially according to the delay time, wherein the sequentially started The difference between the delay times of the two preceding and following 48V-12V modules is equal, and the difference is greater than the power-on time of one 48V-12V module.

Optionally, the delay control module includes:

A first unlocking unit, configured to send a first write protection unlock command to a designated register of the 48V-12V module;

The setting unit is used to set the delay time in the designated register of the 48V-12V module, wherein the delay time of the Nth 48V-12V module is: T _N =T ₁ +(N-1)*Δt, N is the total number of 48V-12V modules in the PDB board, T ₁ is the delay time of the first 48V-12V module, T _N is the delay time of the Nth 48V-12V module, Δt is the two 48V- 12V module delay time difference;

A writing unit, configured to write the delay time into a designated register of the 48V-12V module;

The second unlocking unit is used to send the second write protection unlocking command to the flash (non-volatile memory) of the 48V-12V module;

A saving unit, configured to save the delay time.

Optionally, the 48V-12V module supports the standard PMBUS protocol.

Optionally, the delay time difference is 140ms.

Optionally, the delay control module is a BMC (Baseboard Management Controller, baseboard management controller).

A working method of a PDB board, the PDB board comprising: N parallel-connected 48V-12V modules and a delay control module, any of the 48V-12V modules and the delay control module are connected through a PMBUS interface communication , the input end of any one of the 48V-12V modules is connected to the PSU, the output end of any one of the 48V-12V modules is connected to the main board, wherein N is a natural number and N≥2, and the working methods include:

Get 48V from the PSU;

Use the delay control module to configure the delay time in the designated register of any one of the 48V-12V modules in turn, wherein the difference between the delay times of the two adjacent 48V-12V modules is equal, and the difference > The power-on time of a 48V-12V module;

According to the delay time, N 48V-12V modules connected in parallel are sequentially started to obtain 12V voltage;

Send the 12V voltage to the motherboard.

Optionally, using the delay control module, the method of configuring the delay time in the designated registers of any of the 48V-12V modules in turn includes:

Use the delay control module to configure the delay time for the designated register of the first 48V-12V module;

Use the delay control module to sequentially configure the corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module.

Optionally, the method of using the delay control module to configure the delay time for the designated register of the first 48V-12V module includes:

The delay control module sends the first write protection unlock command to the designated register of the first 48V-12V module;

The delay control module writes the delay time of the first 48-12V module into the designated register of the first 48V-12V module;

The delay control module sends the second write protection unlock command to the flash of the first 48V-12V module;

Save the delay time of the first 48V-12V module.

Optionally, using the delay control module to sequentially configure the corresponding turn-on time for the designated registers of the 48V-12V modules after the first 48V-12V module, including:

The delay control module sends the first write protection unlock command to the designated register of any 48V-12V module after the first 48V-12V module;

According to the formula T _N =T ₁ +(N-1)*Δt, calculate the delay time of the 48V-12V modules after the first 48V-12V module in turn, where N is the total number of 48V-12V modules in the PDB board , T ₁ is the delay time of the first 48V-12V module, T _N is the delay time of the Nth 48V-12V module, Δt is the difference between the delay time of the two 48V-12V modules before and after;

According to the calculated delay time of any 48V-12V module after the first 48V-12V module, the delay control module sends the specified register of any 48V-12V module after the first 48V-12V module Write the corresponding opening time in ;

The delay control module sends the second write protection unlock command to the flash of any 48V-12V module after the first 48V-12V module;

Save the delay time of any 48V-12V module after the first 48V-12V module.

Optionally, the delay control module is a BMC.

The technical solutions provided by the embodiments of the present application may include the following beneficial effects:

The application provides a PDB board, which includes: N 48V-12V modules connected in parallel and a delay control module, wherein any 48V-12V module is connected to the delay control module through a PMBUS interface communication, The input end of any 48V-12V module is connected to the PSU, and the output end of any 48V-12V module is connected to the motherboard. The 48V-12V module is used to convert the 48V voltage from the PSU to 12V voltage and transmit it to the main board; the delay control module is used to set the delay time in the designated register of the 48V-12V module, and start in sequence according to the delay time N 48V-12V modules connected in parallel. By setting a delay control module, the PDB board uses the delay time to stagger the turn-on time of two adjacent 48V-12V modules, so as to realize the time-sharing start of two adjacent 48V-12V modules, thereby avoiding the occurrence of backflow current The resulting current overshoot phenomenon is conducive to improving the stability of the power supply of the PDB board. Among them, the difference between the delay times of the two 48V-12V modules before and after starting in sequence is equal, and the difference is greater than the power-on time of one 48V-12V module. This method of setting the difference can ensure that the next 48V-12V module When powering on, the previous 48V-12V module has been powered on.

In this embodiment, the delay control module adopts BMC. Since the 48V-12V module in this embodiment supports the standard PMBUS protocol, the BMC can not only configure the delay time for the specified register inside the 48V-12V module, but also configure the delay time for the 48V-12V module Monitoring of the power supply voltage, power consumption, temperature and alarm information, etc., is conducive to obtaining the operating status information of the 48V-12V module in time, thereby further improving the stability of the 48V-12V module operation.

The present application also provides a working method of a PDB board, which is applicable to the above-mentioned PDB board. The working method includes: first obtain the 48V voltage from the PSU through multi-stage parallel 48V-12V modules, and then use the delay control module to configure the delay time of the current 48V-12V module in the designated register of any 48V-12V module in turn , and then start multiple parallel-connected 48V-12V modules sequentially according to the configured delay time, finally obtain 12V voltage, and finally send the obtained 12V voltage to the main board. In this embodiment, the delay control module is used to configure the delay time of each 48V-12V module in turn, so that the startup time of N 48V-12V modules is staggered in turn, that is, when starting multiple 48V-12V modules, the first The 48V-12V module will start first and output a stable voltage, then the second 48V-12V module will start and output a stable voltage until the Nth 48V-12V module starts and outputs a stable voltage. This method of setting the delay time for the specified register inside the 48V-12V module can avoid the current backflow problem caused by the voltage difference between two adjacent 48V-12V modules during the voltage frequency modulation process, thereby avoiding the current overshoot phenomenon. It is beneficial to improve the stability of the output voltage of the PDB board.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description serve to explain the principles of the application.

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, In other words, other drawings can also be obtained from these drawings on the premise of not paying creative work.

Fig. 1 is the structural representation of a kind of PDB board provided by the embodiment of the present application;

Fig. 2 is a schematic diagram of the working principle of the delay control module in the embodiment of the present application;

FIG. 3 is a schematic flowchart of a working method of a PDB board provided by an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described The embodiments are only some of the embodiments of the present application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the scope of protection of this application.

In order to better understand the present application, the implementation manner of the present application will be explained in detail below in conjunction with the accompanying drawings.

Embodiment one

Referring to FIG. 1 , FIG. 1 is a schematic structural diagram of a PDB board provided by an embodiment of the present application. As can be seen from Figure 1, the PDB board in this embodiment mainly includes: multiple parallel-connected 48V-12V modules and a delay control module, where multiple parallel-connected 48V-12V modules can be recorded as N 48V-12V modules , N is a natural number and N≥2, that is, one PDB board includes at least two 48V-12V modules. Among them, any 48V-12V module among the N 48V-12V modules is connected to the delay control module through the PMBUS interface, and the input terminal of any 48V-12V module is connected to the PSU to obtain the 48V voltage from the PSU. The output end of any 48V-12V module is connected to the main board, which is used to supply power to the CPU, memory and hard disk on the main board with the converted 12V voltage.

In this embodiment, the 48V-12V module is used to convert the 48V voltage from the PSU into a 12V voltage, and transmit the converted 12V voltage to the main board. The delay control module is used to set the delay time in the designated register of the 48V-12V module, and sequentially start N 48V-12V modules connected in parallel according to the set delay time. Wherein, the difference between the delay times of the two 48V-12V modules started sequentially is equal, and the difference is greater than the power-on time of one 48V-12V module.

The working process of a 48V-12V module includes: power-on process and constant voltage output process. The power-on process is the voltage conversion process, which corresponds to the power-on time, which is the time for a 48V-12V module to rise from 0V to 12V. The power-on time is also the turn-on time of a 48V-12V module. In this embodiment, the start time of the turn-on time is the connection time of the 48V-12V module, and the end time of the turn-on time is when the 48V-12V module starts to output constant voltage. time. The difference of the delay time is the interval time between two adjacent 48V-12V modules before and after starting in sequence. In this embodiment, the delay times of multiple 48V-12V modules form an arithmetic sequence, and the difference is greater than one 48V-12V module. The power-on time of the 12V module ensures that after the previous 48V-12V module is powered on, the next 48V-12V module is powered on, so that the power-on time of the two 48V-12V modules is staggered. Therefore, the setting of the delay control module in this embodiment can effectively avoid the current backflow problem caused by the voltage difference between two adjacent 48V-12V modules during the voltage frequency modulation process, thereby improving the stability of the output voltage.

Taking the PDB board including two 48V-12V modules as an example, the working principle of the delay control module in this embodiment can be referred to in FIG. 2 . In Fig. 2, the abscissa is time, the unit is millisecond ms, and the ordinate is voltage amplitude, the unit is volt. The two 48V-12V modules are respectively: module 1 and module 2, where the delay time of module 1 is 60ms, and the delay time of module 2 is 200ms. It can be seen from Figure 2 that after setting the delay time of module 1 to 60ms through the delay control module, module 1 will enter the power-on process after 60 ms after the server is turned on, that is, it will enter the power-on process after 60 ms after the PSU is turned on, and the power-on is complete Perform constant voltage output; module 2 will enter the power-on process 200ms after module 1 starts the server, and will perform constant voltage output after power-on.

Further, in this embodiment, the difference of the delay time configured by the delay control module is 140 ms, and the difference is set according to the power-on time of the module, and the difference is greater than the power-on time. Usually, the power-on time of the 48V-12V module is 100ms. In this embodiment, the difference is 140ms, which can ensure that the two 48V-12V modules are powered on in an orderly manner, and a buffer (buffer time) of 40ms can also be reserved, which is conducive to further improvement. The safety and stability of 48V-12V module power-on.

The delay control module in this embodiment mainly includes five parts: a first unlocking unit, a setting unit, a writing unit, a second unlocking unit and a saving unit.

Wherein, the first unlocking unit is used to send the first write protection unlocking command to the designated register of the 48V-12V module. After the designated register of the 48V-12V module receives the first write protection unlocking command, the setting unit and the writing unit can write to the designated register in the 48V-12V module.

The setting unit is used to set the delay time in the designated register of the 48V-12V module. Among them, the delay time of the first 48V-12V module is set to T ₁ , and the delay time of the Nth 48V-12V module is: T _N =T ₁ +(N-1)*Δt, N is the PDB board The total number of 48V-12V modules, T _N is the delay time of the Nth 48V-12V module, Δt is the difference between the delay time of the two 48V-12V modules before and after. Take three 48V-12V modules connected in parallel in the PDB board as an example, the delay time of the first 48V-12V module is set to 60ms, and the difference of the delay time is preset to 140ms, according to T _N = T ₁ + (N-1)*Δt, the delay time of the second 48V-12V module is 200ms, and the delay time of the third 48V-12V module is 340ms.

The writing unit is used to write the delay time set by the setting unit into the designated register of the 48V-12V module. The second unlocking unit is used to send the second write protection unlocking command to the flash of the 48V-12V module. There are two storage areas inside the 48V-12V module: one is RAM and the other is flash. RAM is a volatile memory, and flash is a non-volatile memory. By sending the second write protection unlock command through the second unlocking unit, the parameters written by the writing unit can be stored in the flash from the RAM to realize permanent storage.

The storage unit is used for storing the delay time, so as to sequentially start N 48-12V modules connected in parallel according to the delay time.

Further, the delay control module in this embodiment is realized by a BMC, and the BMC is respectively connected to any 48V-12V module through the PMBUS interface. BMC can not only configure the delay time for the specified register inside the 48V-12V module, but also monitor the power supply voltage, power consumption, temperature and alarm information of the 48V-12V module, which is conducive to timely acquisition of the operating status of the 48V-12V module information, thereby further improving the stability of the 48V-12V module operation.

It should be noted that the 48V-12V module in this embodiment supports the standard PMBUS protocol. The PMBUS protocol is a protocol for power management. Since the 48V-12V module supports the standard PMBUS protocol in this embodiment, the 48V-12V module can easily read the power supply voltage and power consumption of the 48V-12V module through the PMBUS protocol. , temperature and alarm information, etc.

Embodiment two

Referring to FIG. 3 on the basis of the embodiments shown in FIG. 1 and FIG. 2 , FIG. 3 is a schematic flowchart of a working method of a PDB board provided by an embodiment of the present application. As can be seen from Figure 3, the working method of the PDB board in the present embodiment comprises the following steps:

S1: Get 48V from PSU.

That is: Multiple 48V-12V modules connected in parallel all get 48V from the PSU.

S2: Use the delay control module to sequentially configure the delay time in the designated register of any 48V-12V module.

Wherein, the difference between the delay times of two adjacent 48V-12V modules is equal, and the difference is greater than the power-on time of one 48V-12V module. In this embodiment, the delay times of multiple 48V-12V modules connected in parallel are in an arithmetic sequence relationship.

Specifically, according to the different configuration methods for the delay time of the first 48V-12V module and the remaining N-1 48V-12V modules, step S2 further includes the following process:

S21: Use the delay control module to configure the delay time for the designated register of the first 48V-12V module.

Specifically, step S21 includes:

S211: The delay control module sends a first write protection unlock command to a designated register of the first 48V-12V module.

After the designated register of the first 48V-12V module obtains the first write protection unlock command, step S212 can be executed: the delay control module writes the first 48-12V to the designated register of the first 48V-12V module The delay time of the module. The delay time of the first 48V-12V module in this embodiment can be set according to the requirements of the server system and power-on sequence without calculation, and then directly write the preset delay time into the first 48V In the designated register of -12V module. Since the entire server system includes multiple boards, and there is a certain power-on sequence relationship between different boards, this embodiment can effectively improve the power-on timing of the entire server board by controlling the delay time of the first module. Accuracy, thereby improving the stability of the server system.

S213: The delay control module sends a second write protection unlock command to the flash of the first 48V-12V module.

After the Flash obtains the second write protection unlock command, it can save the preset delay time of the first 48V-12V module.

After all configuration commands sent by the delay control module to the first 48V-12V module are executed, step S214 is executed: saving the delay time of the first 48V-12V module.

After saving the delay time of the first 48V-12V module, it is convenient to start N 48V-12V modules sequentially according to the delay time of different 48V-12V modules, so as to ensure that all 48V-12V modules connected in parallel The starting time of the PDB board is staggered to avoid the phenomenon of current overshoot, which is conducive to improving the stability of the output voltage of the PDB board.

S22: Using the delay control module, sequentially configure the corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module.

Specifically, step S22 includes:

S221: The delay control module sends a first write protection unlock command to a designated register of any 48V-12V module after the first 48V-12V module.

S222: According to the formula T _N =T ₁ +(N-1)*Δt, calculate the delay time of the 48V-12V module after the first 48V-12V module sequentially, wherein, N is the time delay of the 48V-12V module in the PDB board The total quantity, T ₁ is the delay time of the first 48V-12V module, T _N is the delay time of the Nth 48V-12V module, Δt is the difference between the delay time of the two 48V-12V modules before and after.

S223: According to the calculated delay time of any 48V-12V module after the first 48V-12V module, the delay control module sends the specified register of any 48V-12V module after the first 48V-12V module Write the corresponding opening time in.

S224: The delay control module sends a second write protection unlock command to the flash of any 48V-12V module after the first 48V-12V module.

S225: Save the delay time of any 48V-12V module after the first 48V-12V module.

In this embodiment, the delay control module configures the delay time of the N-1 48V-12V modules after the first 48V-12V module, which is configured in sequence according to the modules, that is, the above steps S221-S225 are used to complete the configuration After the second 48V-12V module, use the above steps S221-S225 to configure the 48V-12V module until all the N 48V-12V modules are configured.

The principles of steps S221-S225 above are basically the same as steps S211-214, except that step S223 is added, and the delay time of the 48V-12V module currently being configured needs to be calculated first, and then the subsequent delay time writing step is performed.

Continuing to refer to Figure 3, we can see that after using the delay control module to sequentially configure the delay time in the designated register of any 48V-12V module, perform step S3: according to the delay time, sequentially start N 48V-12V modules connected in parallel to obtain 12V voltage.

Since the delay times of multiple parallel-connected 48V-12V modules are different, time-sharing startup can be realized when step S3 is executed, thereby effectively avoiding current backflow.

After the 12V voltage is obtained, step S4 is performed: sending the 12V voltage to the main board.

For parts not described in detail in this embodiment, reference may be made to Embodiment 1 shown in FIGS. 1-2 , and the two embodiments may refer to each other, so details are not repeated here.

The above descriptions are only specific implementation manners of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A kind of PDB board, it is characterized in that, described PDB board comprises: 48V-12V module and a time-delay control module of N parallel connection, pass PMBUS between any described 48V-12V module and time-delay control module Interface communication connection, the input end of any one of the 48V-12V modules is connected to the PSU, and the output end of any one of the 48V-12V modules is connected to the main board, wherein N is a natural number and N≥2; The 48V-12V module is used to convert the 48V voltage from the PSU into a 12V voltage and transmit it to the main board; The delay control module is used to set the delay time in the designated register of the 48V-12V module, and start N parallel-connected 48V-12V modules sequentially according to the delay time, wherein the sequentially started The difference between the delay times of the two preceding and following 48V-12V modules is equal, and the difference is greater than the power-on time of one 48V-12V module. 2. A kind of PDB board according to claim 1, is characterized in that, described delay control module comprises: A first unlocking unit, configured to send a first write protection unlock command to a designated register of the 48V-12V module; The setting unit is used to set the delay time in the designated register of the 48V-12V module, wherein the delay time of the Nth 48V-12V module is: T _N =T ₁ +(N-1)*Δt, N is the total number of 48V-12V modules in the PDB board, T ₁ is the delay time of the first 48V-12V module, T _N is the delay time of the Nth 48V-12V module, Δt is the two 48V- 12V module delay time difference; A writing unit, configured to write the delay time into a designated register of the 48V-12V module; The second unlocking unit is used to send a second write protection unlock command to the flash of the 48V-12V module; The saving unit is used for saving the delay time. 3. A kind of PDB board according to claim 1, is characterized in that, described 48V-12V module supports standard PDBUS agreement. 4. A kind of PDB board according to claim 1, is characterized in that, the difference of described delay time is 140ms. 5. A PDB board according to any one of claims 1-4, wherein the delay control module is a BMC. 6. A working method of a PDB board, characterized in that, the PDB board includes: N 48V-12V modules connected in parallel and a delay control module, any one of the 48V-12V modules and the delay control module The communication between them is connected through the PMBUS interface, the input end of any one of the 48V-12V modules is connected to the PSU, and the output end of any one of the 48V-12V modules is connected to the main board, wherein N is a natural number and N≥2, the working method include: Get 48V from the PSU; Use the delay control module to configure the delay time in the designated register of any one of the 48V-12V modules in turn, wherein the difference between the delay times of the two adjacent 48V-12V modules is equal, and the difference > The power-on time of a 48V-12V module; According to the delay time, N 48V-12V modules connected in parallel are sequentially started to obtain 12V voltage; Send the 12V voltage to the motherboard. 7. the working method of a kind of PDB board according to claim 6, it is characterized in that, utilize delay control module, in the appointed register of any described 48V-12V module successively, configure the method for delay time, comprising: Use the delay control module to configure the delay time for the designated register of the first 48V-12V module; Use the delay control module to sequentially configure the corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module. 8. the working method of a kind of PDB board according to claim 7, is characterized in that, described utilization delay control module, the method for the designated register configuration delay time of first 48V-12V module, comprises: The delay control module sends the first write protection unlock command to the designated register of the first 48V-12V module; The delay control module writes the delay time of the first 48-12V module into the designated register of the first 48V-12V module; The delay control module sends the second write protection unlock command to the flash of the first 48V-12V module; Save the delay time of the first 48V-12V module. 9. The working method of a kind of PDB board according to claim 7, is characterized in that, utilizes time-delay control module, sequentially to the specified register configuration corresponding turn-on time of the 48V-12V module after the first 48V-12V module methods, including: The delay control module sends the first write protection unlock command to the designated register of any 48V-12V module after the first 48V-12V module; According to the formula T _N =T ₁ +(N-1)*Δt, calculate the delay time of the 48V-12V modules after the first 48V-12V module in turn, where N is the total number of 48V-12V modules in the PDB board , T ₁ is the delay time of the first 48V-12V module, T _N is the delay time of the Nth 48V-12V module, Δt is the difference between the delay time of the two 48V-12V modules before and after; According to the calculated delay time of any 48V-12V module after the first 48V-12V module, the delay control module sends the specified register of any 48V-12V module after the first 48V-12V module Write the corresponding opening time in ; The delay control module sends the second write protection unlock command to the flash of any 48V-12V module after the first 48V-12V module; Save the delay time of any 48V-12V module after the first 48V-12V module. 10. The working method of a PDB board according to any one of claims 6-9, wherein the delay control module is a BMC.