CN110618742A - PDB board and working method thereof - Google Patents

PDB board and working method thereof Download PDF

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Publication number
CN110618742A
CN110618742A CN201910767423.9A CN201910767423A CN110618742A CN 110618742 A CN110618742 A CN 110618742A CN 201910767423 A CN201910767423 A CN 201910767423A CN 110618742 A CN110618742 A CN 110618742A
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module
delay time
modules
delay
control module
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CN110618742B (en
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孔祥涛
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Suzhou Wave Intelligent Technology Co Ltd
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Suzhou Wave Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Power Sources (AREA)

Abstract

The application discloses a PDB board and a working method thereof, wherein the PDB board comprises N48V-12V modules and a delay control module which are connected in parallel, any 48V-12V module is connected with the delay control module through a PMBUS interface, the input end of any 48V-12V module is connected with a PSU, and the output end of the any 48V-12V module is connected with a main board. The delay control module is used for setting delay time in a designated register of the 48V-12V module and sequentially starting the N48V-12V modules connected in parallel according to the delay time. The working method of the PDB board comprises the following steps: acquiring a 48V voltage from a PSU; configuring delay time in a designated register of any one 48V-12V module in sequence by using a delay control module; sequentially starting N48V-12V modules connected in parallel according to the delay time to obtain 12V voltage; the 12V voltage is sent to the motherboard. Through the application, time-sharing starting can be realized, the phenomenon of current overshoot is effectively avoided, and the stability of the output voltage of the PDB board is favorably improved.

Description

PDB board and working method thereof
Technical Field
The present disclosure relates to Power conversion technologies, and in particular, to a Power Distribution Board (PDB) Board and a method for operating the PDB Board.
Background
The 48V power supply architecture is applied more and more widely in the fields of communication, automobile power supply, data center and AI server. When the 48V power supply architecture is applied to these fields, the 48V power supply is generally required to be converted into a 12V power supply. Taking the field of AI (artificial intelligence) servers as an example, 8 GPUs (Graphics Processing units, Graphics processors) or even 16 GPUs are generally used for constructing a large-scale artificial intelligence deep learning platform, the power consumption of the GPUs accounts for 70% of the total power consumption of the servers, and in order to meet the power supply requirements, the server platforms carrying the GPUs generally adopt a 48V power supply architecture. Specifically, the PSU (Power Supply Unit) outputs 48V DC (Direct Current) to the server, the 48V Power Supply can directly Supply to the GPU, but the voltage used by components other than the GPU, such as the CPU, the memory, and the hard disk, is lower than 48V, which is to use the PDB board to step down the 48V Power Supply to obtain 12V Power Supply, and then to access the 12V Power Supply to the components such as the CPU, the memory, and the hard disk.
In order to output higher power, the current PDB board usually adopts multistage 48V-12V modules connected in parallel, the input end voltage of the multistage 48V-12V module is 48V, and 12V voltage is obtained after being processed by the PDB board.
However, when the current PDB board performs parallel connection of multiple modules, due to individual differences between the 48V-12V modules, respective working states of the 48V-12V modules are not completely synchronized in a soft start stage, a backward current occurs in the 48V-12V module which is started slowly, and a large current is output in the 48V-12V module which is started quickly. Therefore, the output currents of different modules of 48V-12V are not uniform, the stability of the output voltage is poor, and the larger output current even causes the current overshoot phenomenon.
Disclosure of Invention
The application provides a PDB board and a working method thereof, which aim to solve the problems that in the prior art, the stability of the output voltage of the PDB board is poor, and current overshoot is easily caused in the starting process.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
a PDB panel, comprising: the system comprises N48V-12V modules and a delay control module which are connected in parallel, wherein any 48V-12V module is in communication connection with the delay control module through a PMBUS (Power Management Bus) interface, the input end of any 48V-12V module is connected with a PSU (Power Management Bus), the output end of any 48V-12V module is connected with a mainboard, and N is a natural number and is more than or equal to 2;
the 48V-12V module is used for converting the 48V voltage from the PSU into 12V voltage and transmitting the 12V voltage to the mainboard;
the delay control module is used for setting delay time in a designated register of the 48V-12V module and sequentially starting the N48V-12V modules connected in parallel according to the delay time, wherein the delay time difference of the sequentially started front and rear 48V-12V modules is equal, and the difference is more than the power-on time of one 48V-12V module.
Optionally, the delay control module includes:
the first unlocking unit is used for sending a first write protection unlocking command to a designated register of the 48V-12V module;
a setting unit, configured to set a delay time in a designated register of the 48V-12V module, where the delay time of the nth 48V-12V module is: t isN＝T1+ (N-1) Δ T, N is the total number of 48V-12V modules in PDB plate, T1Delay time, T, for the first 48V-12V moduleNThe delay time of the Nth 48V-12V module is delta t, and the delta t is the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module;
the writing unit is used for writing the delay time into a designated register of the 48V-12V module;
a second unlocking unit for sending a second write-protect unlocking command to a flash (nonvolatile memory) of the 48V-12V module;
and the storage unit is used for storing the delay time.
Optionally, the 48V-12V module supports standard PMBUS protocols.
Optionally, the difference of the delay times is 140 ms.
Optionally, the delay control module is a BMC (Baseboard Management Controller).
A method of operating a PDB board, the PDB board comprising: the working method comprises the following steps that N48V-12V modules and a delay control module are connected in parallel, any 48V-12V module is in communication connection with the delay control module through a PMBUS interface, the input end of any 48V-12V module is connected with a PSU, the output end of any 48V-12V module is connected with a main board, N is a natural number and is more than or equal to 2, and the working method comprises the following steps:
acquiring a 48V voltage from a PSU;
configuring delay time in a designated register of any 48V-12V module in sequence by using a delay control module, wherein the delay time difference of two adjacent front and rear 48V-12V modules is equal, and the difference is more than the power-on time of one 48V-12V module;
sequentially starting N48V-12V modules connected in parallel according to the delay time to obtain 12V voltage;
and sending the 12V voltage to a mainboard.
Optionally, the method for sequentially configuring the delay time in the designated register of any one of the 48V-12V modules by using the delay control module includes:
configuring delay time for a designated register of a first 48V-12V module by using a delay control module;
and utilizing the delay control module to sequentially configure corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module.
Optionally, the method for configuring a delay time for a specified register of a first 48V-12V module by using a delay control module includes:
the delay control module sends a first write protection unlocking command to a designated register of a first 48V-12V module;
the delay control module writes the delay time of the first 48-12V module into a designated register of the first 48V-12V module;
the delay control module sends a second write protection unlocking command to the flash of the first 48V-12V module;
and saving the delay time of the first 48V-12V module.
Optionally, the method for sequentially configuring, by using a delay control module, corresponding on-times for designated registers of 48V-12V modules subsequent to a first 48V-12V module includes:
the delay control module sends a first write protection unlocking command to a designated register of any 48V-12V module behind the first 48V-12V module;
according to the formula TN＝T1Plus (N-1) Δ T, sequentially calculating the delay time of the 48V-12V modules after the first 48V-12V module, wherein N is the total number of the 48V-12V modules in the PDB board, and T is the total number of the 48V-12V modules in the PDB board1Delay time, T, for the first 48V-12V moduleNThe delay time of the Nth 48V-12V module is delta t, and the delta t is the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module;
according to the calculated delay time of any 48V-12V module behind the first 48V-12V module, the delay control module writes corresponding opening time into a designated register of any 48V-12V module behind the first 48V-12V module;
the delay control module sends a second write protection unlocking command to the flash of any 48V-12V module behind the first 48V-12V module;
the delay time of any 48V-12V module after the first 48V-12V module is saved.
Optionally, the delay control module is a BMC.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the present application provides a PDB board, comprising: the system comprises N48V-12V modules and a delay control module which are connected in parallel, wherein any 48V-12V module is in communication connection with the delay control module through a PMBUS interface, the input end of any 48V-12V module is connected with a PSU, and the output end of any 48V-12V module is connected with a mainboard. The 48V-12V module is used for converting the 48V voltage from the PSU into 12V voltage and transmitting the 12V voltage to the mainboard; the delay control module is used for setting delay time in a designated register of the 48V-12V module and sequentially starting the N48V-12V modules connected in parallel according to the delay time. The PDB board is provided with the delay control module, the switching-on time of two adjacent 48V-12V modules in the front and back is staggered by utilizing the delay time, and the time-sharing starting of the two adjacent 48V-12V modules is realized, so that the current overshoot phenomenon caused by the backward flow current is avoided, and the stability of the power supply of the PDB board is improved. The difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module which are started in sequence are equal, and the difference value is larger than the power-on time of one 48V-12V module, and the difference value setting method can ensure that the previous 48V-12V module is completely powered on when the rear 48V-12V module is powered on.
In this embodiment, the delay control module adopts a BMC, and since the 48V-12V module in this embodiment supports a standard PMBUS protocol, the BMC may not only configure delay time for a designated register inside the 48V-12V module, but also monitor power supply voltage, power consumption, temperature, alarm information, and the like of the 48V-12V module, which is beneficial to timely obtaining the operating state information of the 48V-12V module, thereby further improving the operating stability of the 48V-12V module.
The application also provides a working method of the PDB board, and the working method is suitable for the PDB board. The working method comprises the following steps: the method comprises the steps of firstly obtaining 48V voltage from a PSU through a plurality of stages of 48V-12V modules connected in parallel, then utilizing a delay control module to sequentially configure the delay time of the current 48V-12V module in a designated register of any 48V-12V module, then sequentially starting a plurality of 48V-12V modules connected in parallel according to the configured delay time, finally obtaining 12V voltage, and finally sending the obtained 12V voltage to a main board. In this embodiment, the delay control module is used to sequentially configure the delay time for each 48V-12V module, so that the start times of the N48V-12V modules are sequentially staggered, that is, when a plurality of 48V-12V modules are started, a first 48V-12V module is started first and outputs a stable voltage, and then a second 48V-12V module is started and outputs a stable voltage until the nth 48V-12V module is started and outputs a stable voltage. The method for setting the delay time for the designated register in the 48V-12V module can avoid the problem of current backflow caused by the pressure difference in the voltage frequency modulation process of two adjacent 48V-12V modules, further avoid the phenomenon of current overshoot and is beneficial to improving the stability of the output voltage of the PDB board.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a PDB board according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram illustrating the operation of a delay control module according to an embodiment of the present disclosure;
fig. 3 is a schematic flowchart of a working method of a PDB board according to an embodiment of the present disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the accompanying drawings.
Example one
Referring to fig. 1, fig. 1 is a schematic structural diagram of a PDB board according to an embodiment of the present disclosure. As can be seen from fig. 1, the PDB board in this embodiment mainly includes: the system comprises a plurality of 48V-12V modules connected in parallel and a delay control module, wherein the plurality of 48V-12V modules connected in parallel can be marked as N48V-12V modules, N is a natural number and is more than or equal to 2, namely: at least 2 48V-12V modules are included in one PDB board. The delay control module is connected with any one 48V-12V module of the N48V-12V modules through a PMBUS interface in a communication mode, the input end of any one 48V-12V module is connected with the PSU and used for obtaining 48V voltage from the PSU, and the output end of any one 48V-12V module is connected with the mainboard and used for supplying power to the CPU, the memory, the hard disk and the like on the mainboard through the converted 12V voltage.
In this embodiment, the 48V-12V module is configured to convert the 48V voltage from the PSU into a 12V voltage, and transmit the 12V voltage to the motherboard. The delay control module is used for setting delay time in a designated register of the 48V-12V module and sequentially starting the N48V-12V modules connected in parallel according to the set delay time. The delay time difference of the front and the back 48V-12V modules which are started in sequence is equal, and the difference is more than the power-on time of one 48V-12V module.
The working process of the 48V-12V module comprises the following steps: the power-on process, namely the voltage conversion process, corresponds to the power-on time, namely the time for the 48V-12V module to rise from 0V to 12V. The power-on time is also the opening time of a 48V-12V module, in this embodiment, the starting time of the opening time is the access time of the 48V-12V module, and the ending time of the opening time is the time when the 48V-12V module starts to perform constant voltage output. The difference of the delay times is the interval time of sequentially starting the front and the back adjacent 48V-12V modules, in this embodiment, the delay times of the 48V-12V modules form an equal difference array, and the difference is greater than the power-on time of one 48V-12V module, so that after the power-on of the front 48V-12V module is completed, the power-on of the back 48V-12V module is performed, and the start times of the front and the back 48V-12V modules are staggered. Therefore, the arrangement of the delay control module in the embodiment can effectively avoid the problem of current backflow caused by the voltage difference in the voltage frequency modulation process of two adjacent 48V-12V modules, and further improve the stability of the output voltage.
Taking the PDB board including two 48V-12V modules as an example, the working principle of the delay control module in this embodiment can be seen in fig. 2. In fig. 2, the abscissa is time in milliseconds ms and the ordinate is the voltage amplitude in volts. The two 48V-12V modules are respectively: module 1 and module 2, wherein the delay time of module 1 is 60ms, and the delay time of module 2 is 200 ms. As can be seen from fig. 2, after the delay time of the module 1 is set to 60ms by the delay control module, the module 1 enters the power-on process after 60ms after the server is started, that is, the module enters the power-on process after 60ms after the PSU is started, and the power-on process performs constant-voltage output after the power-on process is finished; and the module 2 enters a power-on process 200ms after the module 1 is started, and constant-voltage output is performed after power-on is finished.
Further, in this embodiment, the difference of the delay times configured by the delay control module is 140ms, the difference is set according to the power-on time of the module, and the difference is greater than the power-on time. Generally, the power-on time of the 48V-12V module is 100ms, and the difference value is 140ms in this embodiment, which can ensure that the front and rear 48V-12V modules are powered on in order, and can reserve a buffer (buffer time) of 40ms, which is beneficial to further improving the safety and stability of power-on of the 48V-12V module.
The delay control module in this embodiment mainly includes: the device comprises a first unlocking unit, a setting unit, a writing unit, a second unlocking unit and a storage unit.
The first unlocking unit is used for sending a first write protection unlocking command to a designated register of the 48V-12V module. After the designated register of the 48V-12V module receives the first write protection unlocking command, the setting unit and the writing unit can write the designated register in the 48V-12V module.
The setting unit is used for setting the delay time in a designated register of the 48V-12V module. Wherein the delay time of the first 48V-12V module is set as T1The delay time of the Nth module from 48V to 12V is as follows: t isN＝T1+ (N-1) Δ T, N is the total number of 48V-12V modules in PDB plate, TNThe delay time of the Nth 48V-12V module is delta t, and the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module is delta t. Taking the PDB board comprising three 48V-12V modules connected in parallel as an example, the delay time of the first 48V-12V module is set to be 60ms, the difference of the delay times is preset to be 140ms, and the delay time is determined according to TN＝T1Plus (N-1) Δ t, the delay time of the second 48V-12V module is 200ms, and the delay time of the third 48V-12V module is 340 ms.
The writing unit is used for writing the delay time set by the setting unit into a designated register of the 48V-12V module. The second unlocking unit is used for sending a second write protection unlocking command to a flash of the 48V-12V module, and the 48V-12V module is internally provided with two parts of storage areas: one is RAM and the other is flash. The RAM is a volatile memory, and the flash is a nonvolatile memory. And a second write protection unlocking command is sent by the second unlocking unit, so that the parameters written by the writing unit can be stored into the flash from the RAM, and permanent storage is realized.
The holding unit is used for holding the delay time so as to start the N48-12V modules connected in parallel according to the delay time.
Further, the delay control module in this embodiment is implemented by using a BMC, and the BMC is connected to any one of the 48V-12V modules through a PMBUS interface. The BMC can not only configure delay time for a designated register in the 48V-12V module, but also monitor power supply voltage, power consumption, temperature, alarm information and the like of the 48V-12V module, and is beneficial to timely acquiring running state information of the 48V-12V module, so that running stability of the 48V-12V module is further improved.
It should be noted that the 48V-12V module supports the standard PMBUS protocol in this embodiment. The PMBUS protocol is a protocol for power management, and as the 48V-12V module in the embodiment supports the standard PMBUS protocol, the 48V-12V module can conveniently read the power supply voltage, power consumption, temperature, alarm information and the like of the 48V-12V module through the PMBUS protocol.
Example two
Referring to fig. 3 based on the embodiments shown in fig. 1 and fig. 2, fig. 3 is a schematic flow chart of a working method of a PDB board according to an embodiment of the present application. As can be seen from fig. 3, the working method of the PDB board in this embodiment includes the following steps:
s1: the 48V voltage from the PSU is acquired.
Namely: a plurality of parallel connected 48V-12V modules each take the 48V voltage from the PSU.
S2: and utilizing the delay control module to sequentially configure delay time in a designated register of any 48V-12V module.
The delay time difference of the adjacent front and back 48V-12V modules is equal, and the difference is larger than the power-on time of one 48V-12V module. In the embodiment, the delay time of the 48V-12V modules connected in parallel is in an arithmetic progression relationship.
Specifically, according to the difference of the configuration method of the delay time of the first 48V-12V module and the remaining N-1 48V-12V modules, the step S2 further includes the following steps:
s21: and configuring the delay time for the specified register of the first 48V-12V module by using the delay control module.
Specifically, step S21 includes:
s211: the latency control module sends a first write protect unlock command to a designated register of a first 48V-12V module.
After the first write protect unlock command is obtained by the specific register of the first 48V-12V module, step S212 may be executed: the delay control module writes the delay time of the first 48-12V module into a designated register of the first 48V-12V module. In this embodiment, the delay time of the first 48V-12V module may be set according to different requirements of the server system and the power-on timing sequence without calculation, and then the preset delay time is directly written into the designated register of the first 48V-12V module. Because the whole server system comprises a plurality of board cards, and a certain power-on time sequence relationship exists between different board cards, the accuracy of the power-on time sequence of the whole server board card can be effectively improved by controlling the delay time of the first module, so that the stability of the server system is improved.
S213: and the delay control module sends a second write protection unlocking command to the flash of the first 48V-12V module.
After the Flash obtains the second write protection unlocking command, the preset delay time of the first 48V-12V module can be saved.
After the delay control module finishes executing all the configuration commands sent by the first 48V-12V module, step S214 is executed: and saving the delay time of the first 48V-12V module.
After the delay time of the first 48V-12V module is stored, the N48V-12V modules can be sequentially and sequentially started according to the delay time of different 48V-12V modules, so that the starting time of all the 48V-12V modules connected in parallel is staggered, the phenomenon of current overshoot is avoided, and the stability of the output voltage of the PDB board is improved.
S22: and utilizing the delay control module to sequentially configure corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module.
Specifically, step S22 includes:
s221: the delay control module sends a first write-protect unlock command to a designated register of any 48V-12V module following the first 48V-12V module.
S222: according to the formula TN＝T1Plus (N-1) Δ T, sequentially calculating the delay time of the 48V-12V modules after the first 48V-12V module, wherein N is the total number of the 48V-12V modules in the PDB board, and T is the total number of the 48V-12V modules in the PDB board1Delay time, T, for the first 48V-12V moduleNThe delay time of the Nth 48V-12V module is delta t, and the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module is delta t.
S223: and according to the calculated delay time of any 48V-12V module behind the first 48V-12V module, the delay control module writes the corresponding opening time into a designated register of any 48V-12V module behind the first 48V-12V module.
S224: and the delay control module sends a second write protection unlocking command to the flash of any 48V-12V module behind the first 48V-12V module.
S225: the delay time of any 48V-12V module after the first 48V-12V module is saved.
In this embodiment, the method for configuring the delay time of the N-1 48V-12V modules after the first 48V-12V module by the delay control module is sequentially configured according to the modules, that is, after the second 48V-12V module is configured by the steps S221 to S225, the 48V-12V module is configured by the steps S221 to S225 until all the N48V-12V modules are configured.
The principle of the steps S221 to S225 is basically the same as that of the steps S211 to S214, except that the step S223 is added, and the delay time of the currently configured 48V-12V module needs to be calculated first, and then the subsequent step of writing the delay time is performed.
With continued reference to fig. 3, after configuring the delay time in the designated register of any 48V-12V module in turn by using the delay control module, step S3 is executed: and sequentially starting the N48V-12V modules connected in parallel according to the delay time to obtain 12V voltage.
Due to the fact that the delay time of the parallel 48V-12V modules is different, time-sharing starting can be achieved when the step S3 is executed, and therefore current backflow is effectively avoided.
After the 12V voltage is acquired, step S4 is executed: the 12V voltage is sent to the motherboard.
The parts not described in detail in this embodiment may refer to the first embodiment shown in fig. 1 to 2, and the two embodiments may refer to each other, which is not described herein again.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. A PDB panel, comprising: the system comprises N48V-12V modules and a delay control module which are connected in parallel, wherein any 48V-12V module is in communication connection with the delay control module through a PMBUS interface, the input end of any 48V-12V module is connected with a PSU, the output end of any 48V-12V module is connected with a mainboard, N is a natural number and is more than or equal to 2;
the 48V-12V module is used for converting the 48V voltage from the PSU into 12V voltage and transmitting the 12V voltage to the mainboard;
the delay control module is used for setting delay time in a designated register of the 48V-12V module and sequentially starting the N48V-12V modules connected in parallel according to the delay time, wherein the delay time difference of the sequentially started front and rear 48V-12V modules is equal, and the difference is more than the power-on time of one 48V-12V module.
2. The PDB board of claim 1, wherein the delay control module comprises:
the first unlocking unit is used for sending a first write protection unlocking command to a designated register of the 48V-12V module;
a setting unit, configured to set a delay time in a designated register of the 48V-12V module, where the delay time of the nth 48V-12V module is: t isN＝T1+ (N-1) Δ T, N is the total number of 48V-12V modules in PDB plate, T1Delay time, T, for the first 48V-12V moduleNThe delay time of the Nth 48V-12V module is delta t, and the delta t is the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module;
the writing unit is used for writing the delay time into a designated register of the 48V-12V module;
the second unlocking unit is used for sending a second write protection unlocking command to the flash of the 48V-12V module;
and the storage unit is used for storing the delay time.
3. The PDB board of claim 1, wherein said 48V-12V module supports standard PMBUS protocol.
4. The PDB board of claim 1, wherein the difference in delay time is 140 ms.
5. A PDB board according to any of claims 1-4, wherein said delay control module is a BMC.
6. A method of operating a PDB board, the PDB board comprising: the working method comprises the following steps that N48V-12V modules and a delay control module are connected in parallel, any 48V-12V module is in communication connection with the delay control module through a PMBUS interface, the input end of any 48V-12V module is connected with a PSU, the output end of any 48V-12V module is connected with a main board, N is a natural number and is more than or equal to 2, and the working method comprises the following steps:
acquiring a 48V voltage from a PSU;
configuring delay time in a designated register of any 48V-12V module in sequence by using a delay control module, wherein the delay time difference of two adjacent front and rear 48V-12V modules is equal, and the difference is more than the power-on time of one 48V-12V module;
sequentially starting N48V-12V modules connected in parallel according to the delay time to obtain 12V voltage;
and sending the 12V voltage to a mainboard.
7. The working method of the PDB board as claimed in claim 6, wherein the method for configuring the delay time in the designated register of any one of said 48V-12V modules in turn by using the delay control module comprises:
configuring delay time for a designated register of a first 48V-12V module by using a delay control module;
and utilizing the delay control module to sequentially configure corresponding delay time for the designated registers of the 48V-12V modules after the first 48V-12V module.
8. The operating method of the PDB board as claimed in claim 7, wherein said method for configuring the delay time for the designated register of the first 48V-12V module by using the delay control module comprises:
the delay control module sends a first write protection unlocking command to a designated register of a first 48V-12V module;
the delay control module writes the delay time of the first 48-12V module into a designated register of the first 48V-12V module;
the delay control module sends a second write protection unlocking command to the flash of the first 48V-12V module;
and saving the delay time of the first 48V-12V module.
9. The operating method of the PDB board as claimed in claim 7, wherein the method for configuring the corresponding on-time to the designated registers of the 48V-12V modules after the first 48V-12V module in sequence by using the delay control module comprises:
the delay control module sends a first write protection unlocking command to a designated register of any 48V-12V module behind the first 48V-12V module;
according to the formula TN＝T1Plus (N-1) Δ T, sequentially calculating the delay time of the 48V-12V modules after the first 48V-12V module, wherein N is the total number of the 48V-12V modules in the PDB board, and T is the total number of the 48V-12V modules in the PDB board1Delay time, T, for the first 48V-12V moduleNThe delay time of the Nth 48V-12V module is delta t, and the delta t is the difference value of the delay time of the front 48V-12V module and the delay time of the rear 48V-12V module;
according to the calculated delay time of any 48V-12V module behind the first 48V-12V module, the delay control module writes corresponding opening time into a designated register of any 48V-12V module behind the first 48V-12V module;
the delay control module sends a second write protection unlocking command to the flash of any 48V-12V module behind the first 48V-12V module;
the delay time of any 48V-12V module after the first 48V-12V module is saved.
10. The operating method of a PDB board of any of claims 6 to 9, wherein said delay control module is a BMC.
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111740405A (en) * 2020-05-29 2020-10-02 科华恒盛股份有限公司 Starting control method, system and device of electrical equipment
CN115061789A (en) * 2022-06-09 2022-09-16 海光信息技术股份有限公司 Transient current control method and related device

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060242462A1 (en) * 2005-04-22 2006-10-26 Dell Products L.P. Power supply control in a server system
CN101369136A (en) * 2008-09-25 2009-02-18 浪潮电子信息产业股份有限公司 Power supply distribution unit capable of time-sharing power supply
US20120072738A1 (en) * 2010-09-21 2012-03-22 Oracle International Corporation Reducing latency when activating a power supply unit
CN102749856A (en) * 2012-05-30 2012-10-24 曙光信息产业(北京)有限公司 Power-on sequential control circuit and method
CN103064497A (en) * 2011-10-21 2013-04-24 研祥智能科技股份有限公司 Power source delayed power supply device, network main board and network host
CN103728896A (en) * 2012-10-10 2014-04-16 杭州华三通信技术有限公司 Method and device for controlling power-on sequence of multiple channels of power supplies
CN104281244A (en) * 2013-07-04 2015-01-14 鸿富锦精密工业（深圳）有限公司 Time-delay device and time-delay circuits
CN104570774A (en) * 2013-10-15 2015-04-29 深圳迈瑞生物医疗电子股份有限公司 Method and system for powering on and off multiple electrical units
CN104571442A (en) * 2015-01-26 2015-04-29 浪潮电子信息产业股份有限公司 Power platform-based memory board POWER-on time sequence control method
CN106125818A (en) * 2016-08-24 2016-11-16 泰利美信（苏州）医疗科技有限公司 A kind of power-supply circuit and control method thereof
CN107918477A (en) * 2017-11-15 2018-04-17 曙光信息产业(北京)有限公司 Whole machine cabinet power supplying system of server
CN108663969A (en) * 2018-05-15 2018-10-16 郑州云海信息技术有限公司 A kind of SCM Based power panel sequential time delay module and method
CN109885151A (en) * 2019-01-31 2019-06-14 郑州云海信息技术有限公司 A kind of server power supply monitoring method and system

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060242462A1 (en) * 2005-04-22 2006-10-26 Dell Products L.P. Power supply control in a server system
CN101369136A (en) * 2008-09-25 2009-02-18 浪潮电子信息产业股份有限公司 Power supply distribution unit capable of time-sharing power supply
US20120072738A1 (en) * 2010-09-21 2012-03-22 Oracle International Corporation Reducing latency when activating a power supply unit
CN103064497A (en) * 2011-10-21 2013-04-24 研祥智能科技股份有限公司 Power source delayed power supply device, network main board and network host
CN102749856A (en) * 2012-05-30 2012-10-24 曙光信息产业(北京)有限公司 Power-on sequential control circuit and method
CN103728896A (en) * 2012-10-10 2014-04-16 杭州华三通信技术有限公司 Method and device for controlling power-on sequence of multiple channels of power supplies
CN104281244A (en) * 2013-07-04 2015-01-14 鸿富锦精密工业（深圳）有限公司 Time-delay device and time-delay circuits
CN104570774A (en) * 2013-10-15 2015-04-29 深圳迈瑞生物医疗电子股份有限公司 Method and system for powering on and off multiple electrical units
CN104571442A (en) * 2015-01-26 2015-04-29 浪潮电子信息产业股份有限公司 Power platform-based memory board POWER-on time sequence control method
CN106125818A (en) * 2016-08-24 2016-11-16 泰利美信（苏州）医疗科技有限公司 A kind of power-supply circuit and control method thereof
CN107918477A (en) * 2017-11-15 2018-04-17 曙光信息产业(北京)有限公司 Whole machine cabinet power supplying system of server
CN108663969A (en) * 2018-05-15 2018-10-16 郑州云海信息技术有限公司 A kind of SCM Based power panel sequential time delay module and method
CN109885151A (en) * 2019-01-31 2019-06-14 郑州云海信息技术有限公司 A kind of server power supply monitoring method and system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111740405A (en) * 2020-05-29 2020-10-02 科华恒盛股份有限公司 Starting control method, system and device of electrical equipment
CN115061789A (en) * 2022-06-09 2022-09-16 海光信息技术股份有限公司 Transient current control method and related device
CN115061789B (en) * 2022-06-09 2024-02-09 海光信息技术股份有限公司 Transient current control method and related device

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