CN103728896A - Method and device for controlling power-on sequence of multiple channels of power supplies - Google Patents
Method and device for controlling power-on sequence of multiple channels of power supplies Download PDFInfo
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Abstract
The invention discloses a method and device for controlling the power-on sequence of multiple channels of power supplies. When a system is detected to be powered on, a programmable logic chip tacitly approves that enabled pins connected with secondary power supplies of all chips on a PCB are invalid, and then the pins are sequentially enabled according to the preset chip power-on sequence, so that the multiple channels of power supplies sequentially conduct secondary power supply on the chips on the PCB according to the preset power-on sequence. Further, the power-on intervals of the multiple channels of power supplies can be achieved through a programmable logic chip counter. According to the method and device for controlling the power-on sequence of the multiple channels of power supplies, under the situation that special power-on sequence control chips and production links are not added, control over the power-on sequence of the multiple channels of power supplies is achieved, and the power supply intervals and the power-on sequence can be adjusted flexibly at the same time.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of method and device of controlling multiple power supplies electric sequence.
Background technology
Along with the development of large scale integrated circuit technology, chip design and design of circuit system become increasingly complex.A lot of chips not only adopt multiple power supplies power supply, and between each circuit power, electric sequence are had to very high requirement.Such as: certain power supply chip has 3.3V, 2.5V, 1.8V, 1.2V, several power specifications of 0.9V, require to power on from low to high, and a rear power supply powering on will power on previous powering on after reaching 90% again, total deadline that powers on is required to be controlled in 5ms to complete simultaneously.
For meeting above-mentioned power requirement, the special electric sequence control chip of general employing in existing scheme, as the Power Manager I of the ISL8702 of INTERSIL company or Lattice company, Power Manager II family chip.But, although special electric sequence control chip can be realized the upper and lower electric control of Dui Ge road power supply preferably, but because the independent chip of needs is realized the control function of electric sequence, increased cost, the product that this is very large for delivering amount, cost is comparatively responsive, production firm generally can not accept.
In addition, also there is certain deficiency in special electric sequence control chip.Particularly, as shown in Figure 1, ISL8702 electric sequence control chip can only be realized the electric sequence control of 4 tunnels (A, B, C, D) power supply, on this chip, be provided with 4 enable pins, A, B, C, D pin in corresponding diagram respectively, ISL8702 chip is by controlling the enable signal of these 4 pins, realizes the sequential control that the secondary power supply of the chip being attached thereto powers on.Wherein the interval that powers between two-way is controlled by the size of peripheral resistance.When chip requires the power supply of control to exceed 4 tunnel, just need to increase ISL8702 chip.In addition, because ISL8702 chip requires to power on and must carry out according to the order of A-B-C-D, once design, occur that connection error or chip producer change electric sequence requirement, just can only redesign pcb board, so, can increase pcb board development and Design difficulty and the cost of company.Although and the Power Manager family chip of Lattice company can be realized the electric sequence control of multiple power supplies (from 6 Dao12 roads not etc.), and also can change flexibly the electric sequence between multiple power supplies, but it needs to load separately the logic software of Power Manager chip, increase production link one, need to increase equally the cost of production firm.
Summary of the invention
In view of this, the invention provides a kind of method and device of controlling multiple power supplies electric sequence.By the present invention, in the situation that not increasing electric sequence control chip and production link, can realize the control of multiple power supplies electric sequence, can realize the flexible adjustment of supply cell and electric sequence simultaneously.
For realizing the object of the invention, implementation of the present invention is specific as follows:
Control a method for multivoltage electric supply sequence, described method is for carrying out secondary power supply power supply to the each chip on pcb board successively according to predefined procedure, and wherein said method comprises:
When step 1, the system of detecting power on, all enable pins that are connected with the each chip secondary of pcb board power supply of described programmable logic chip acquiescence are invalid;
Step 2, according to the electric sequence of each chip on pcb board, enable successively each pin, make the power supply being connected with pin to each chip, carry out secondary power supply power supply successively according to aforementioned electric sequence.
Further, in described step 2, on pcb board, the electric sequence of each chip needs to determine according to the actual application scenarios of each chip power order on electronic equipment.
Further, when having determined according to the application scenarios of electronic equipment reality on pcb board after the electric sequence of each chip, directly in the logical code of CPLD chip according to pcb board on the electric sequence of each chip set the order that enables of each pin.
Further, if need to the electric sequence of different chips on pcb board be adjusted, according to the chip power order after adjusting, change the logical code of enable pin order in CPLD chip.
Further, described method also comprises: by the counting of CPLD Chip counter, realize the time delay to the each pin enable signal output of CPLD chip, and then realization was adjusted to the supply cell time of each chip power on pcb board.
The present invention provides a kind of device of controlling multiple power supplies electric sequence simultaneously, the electric sequence of the secondary power supply power supply of described application of installation each chip on to electronic equipment pcb board is controlled, wherein said device is specially CPLD chip, and wherein said device comprises:
Whether the detecting unit that powers on, power on for detection of system, and when the system of detecting powers on, described device acquiescence is all invalid with the enable pin that on pcb board, each chip secondary power supply is connected;
Electric sequence control module, for enabling successively each pin according to the electric sequence of each chip on predefined pcb board;
Power supply enables unit, when receiving electric sequence control module, enables after the signal of each pin, enables the chip secondary power supply out-put supply being connected with this pin.
Further, the electric sequence of different chips on described pcb board, specifically realize in the following way:
In the logical code of CPLD chip, according to the electric sequence of different chips on pcb board, set the order that enables each pin;
Described electric sequence control module, according to the order that enables each pin setting in the logical code of CPLD chip, enables each pin successively;
Power supply enables unit and enables after the signal of each pin when receiving electric sequence control module, enables the chip secondary power supply out-put supply being connected with this pin.
Further, the electric sequence of different chips is adjusted on need to be to pcb board, enables the logical code of order by each pin in change CPLD chip.
Further, described electric sequence control module is realized the time delay output to pin enable signal by the counting of counter on CPLD chip, and then realization was adjusted the supply cell time of each chip power on pcb board.
Compared with existing technical scheme, use after the present invention, can be in the situation that not increasing electric sequence control chip and production link, realize the control of multiple power supplies electric sequence, can realize the flexible adjustment of supply cell and electric sequence, simplified design and production process, reduce cost of products simultaneously.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of prior art ISL8702 chip controls electric sequence.
Fig. 2 is the method flow schematic diagram of control multiple power supplies electric sequence of the present invention.
Fig. 3 is CPLD chip composition structural representation.
Fig. 4 is the circuit diagram that the present invention utilizes CPLD chip controls multiple power supplies electric sequence.
Fig. 5 is the device schematic diagram of control multiple power supplies electric sequence of the present invention.
Embodiment
In order to realize the object of the invention, the core concept that the present invention adopts is: utilize idle pin and idle programming in logic resource on the CPLD chip (programmable logic chip) on electronic equipment pcb board to realize the upper electric control to multiple power supplies.Particularly, when the system of detecting powers on, described programmable logic chip acquiescence is invalid with the enable pin that on pcb board, each chip secondary power supply is connected, then according to predetermined chip power order, enable successively described pin, and then Shi Ge road power supply carries out secondary power supply power supply to the each chip on pcb board successively according to predetermined electric sequence.Further, power supply electrifying interval, described each road can be realized by described programmable logic chip counter.By the present invention, can, in the situation that not increasing special electric sequence control chip and production link, realize the electric sequence control of multiple power supplies, can realize the flexible adjustment of supply cell and electric sequence simultaneously.
For making technical solution of the present invention more clear and clear, below in conjunction with the specific embodiment of the invention, described in detail.As shown in Figure 2, be the method flow schematic diagram of control multiple power supplies electric sequence of the present invention.Described method is for carrying out secondary power supply power supply to the each chip on pcb board successively according to predefined procedure.Described method comprises:
When step 1, the system of detecting power on, described programmable logic chip acquiescence is all invalid with the enable pin that on pcb board, each chip secondary power supply is connected.
As shown in Figure 3, be CPLD chip composition structural representation.CPLD chip is general programmable logic device (PLD), mainly general IO pin (peripheral components shown in Fig. 3) and programmable logic cells (the inside blockage shown in Fig. 3), consists of.Wherein IO pin is for aerial lug, can flexible configuration input and output type; Programmable logic cells is minimum available logic ingredient, for carrying out programming in logic.Complete after the necessary logic control function of pcb board, the IO pin of CPLD and programmable logic cells generally all can be available free, and the present invention utilizes the idle pin of CPLD chip and idle programming in logic resource to realize the electric sequence control to multiple power supplies.
As shown in Figure 4, for utilizing the idle pin of CPLD chip and idle programming in logic resource, the present invention realizes the circuit diagram of controlling multiple power supplies electric sequence.In the figure, for convenience of description, the only annexation between exemplary feed circuit and the programmable logic chip pin of enumerating 3 road chips, if there are multiple chip power supply power supplys, annexation and Fig. 4 are similar.Be not able to this scope as limit the present invention program.
In order to realize the object of the invention, the present invention utilizes the signal of the idle IO pin output of CPLD chip to enable to control as the power supply of each chip secondary power supply (DC-DC in Fig. 2) on pcb board.Wherein, the pin that carries out secondary power supply power supply for each chip enable to control require substantially similar: when EN is expressed as low level for " 0 ", forbid the output of chip power supply power supply; When EN is " 1 ", represent high level or " Z " high resistant, the output of chip power supply power supply effectively.Preferably, chip secondary power supply power supply enable signal (Vo1_EN, the Vo2_EN of CPLD chip output of the present invention ... VoN_EN) be set as 2 kinds of states: " 0 " low level and " Z " high resistant.When CPLD chip pin enable signal is " 0 ", chip secondary power supply is not exported, and when CPLD chip pin enable signal is " Z ", owing to there being the existence of pull-up resistor VIN, chip secondary power supply is normally exported.
In this step, when the system of detecting powers on, the all enable pins that are connected with chip secondary power supply of described CPLD chip acquiescence are invalid, be that idle pin output signal on CPLD chip is set as " 0 ", like this, after system powers on, due to enable signal Vo1, the Vo2 of the chip secondary power supply of all CPLD chip pin output ... VoN is " 0 " low level, therefore, described chip secondary power supply is forbidden power supply output, and then can avoid bringing larger rush of current to secondary power supply chip while out-put supply.
Step 2, according to the electric sequence of each chip on pcb board, enable successively each pin, make the power supply being connected with pin to each chip, carry out secondary power supply power supply successively according to aforementioned electric sequence.
In the present invention, on pcb board, the electric sequence of each chip specifically can need to determine according to the application scenarios of electronic equipment reality.Particularly, when having determined according to the application scenarios of electronic equipment reality on pcb board after the electric sequence of the required power supply of different chip load, directly in the logical code of CPLD chip according to pcb board on the electric sequence of each chip set the order that enables of each pin.Like this, CPLD chip, just can be according to the electric sequence of each chip on pcb board after system powers on, successively each pin is enabled, particularly, successively each pin level is set as to " Z " high level, and then makes each chip power supply power supply complete the secondary power supply power supply to each chip.If follow-up, need to adjust the electric sequence of different chips on pcb board, also the logical code that only need to change according to the chip power order after adjusting enable pin order in CPLD chip, need not redesign or change special electric sequence control chip etc. to pcb board.Therefore, compared with existing scheme, the inventive method not only can be adjusted flexibly to electric sequence, and can simplified design and production process, reduces cost of products.
Further, in order realizing, the time interval of each chip power on pcb board to be adjusted, can be realized the time delay to the each pin enable signal output of CPLD chip by the counting of CPLD Chip counter.
Particularly, the principle of the enable signal of CPLD chip generation time delay is the different delayed time that produces the enable signal of each pin by outside OSC crystal oscillator.According to electric sequence, require different delayed signals to distribute to respectively Vo1_EN, Vo2_EN ... VoN_EN signal, thus reach time interval of the electric sequence of programmable logic chip.As adopt the OSC(crystal oscillator of 1KHZ) crystal oscillator, the cycle is 1ms, and Vo1_EN is programmed for direct output high level, and 5 all after dates of Vo2_EN OSC crystal oscillator counting are just exported high level, and Vo3_EN is that OSC crystal oscillator is counted 10 all after dates and just exported high level., after the 1st chip power supply power turn-on, after 5ms, the 2nd chip power supply power supply exported conducting, then the 3rd chip power supply power supply output conducting after 5ms.So, the present invention just can be according to practical application needs, can adjust arbitrarily difference and enable the delay time between control signal, thereby realize the control to different loads chip power time sequencing.
The present invention provides a kind of device of controlling multiple power supplies electric sequence simultaneously, and the electric sequence of the secondary power supply power supply of wherein said application of installation each chip on to electronic equipment pcb board is controlled, and described device is specially CPLD chip, comprising:
Whether the detecting unit that powers on, power on for detection of system, when the system of detecting powers on, and described device acquiescence and the pin inactive that on pcb board, each chip secondary power supply is connected.
Electric sequence control module, for enabling successively each pin according to the electric sequence of each chip power on predefined pcb board.
Power supply enables unit, when receiving electric sequence control module, enables after the signal of each pin, and the chip being connected with this pin is carried out to secondary power supply power supply.
Further, the electric sequence of different chips on described pcb board, specifically realize in the following way:
In the logical code of CPLD chip, according to the electric sequence of different chips on pcb board, set the order that enables each pin;
Described electric sequence control module, according to the order that enables each pin setting in the logical code of CPLD chip, enables each pin successively;
Power supply enables unit and enables after the signal of each pin when receiving electric sequence control module, enables the chip secondary power supply out-put supply being connected with this pin.
Further, the electric sequence of different chips is adjusted on need to be to pcb board, enables the logical code of order by each pin in change CPLD chip.
Further, described electric sequence control module is realized the time delay output to pin enable signal by the counting of counter on CPLD chip, and then realization was adjusted the supply cell time of each chip power on pcb board.
The foregoing is only preferred embodiment of the present invention, in order to limit the present invention, within the spirit and principles in the present invention not all, any modification of making, be equal to replacement, improvement etc., within all should being included in the scope of protection of the invention.
Claims (9)
1. control a method for multiple power supplies electric sequence, described method is used for successively the each chip on pcb board being carried out to secondary power supply power supply according to predefined procedure, it is characterized in that, described method comprises:
When step 1, the system of detecting power on, all enable pins that are connected with the each chip secondary of pcb board power supply of described programmable logic chip acquiescence are invalid;
Step 2, according to the electric sequence of each chip on pcb board, enable successively each pin, make the power supply being connected with pin to each chip, carry out secondary power supply power supply successively according to aforementioned electric sequence.
2. the method for claim 1, is characterized in that, in described step 2, on pcb board, the electric sequence of each chip needs to determine according to the actual application scenarios of each chip power order on electronic equipment.
3. method as claimed in claim 2, it is characterized in that, when having determined according to the application scenarios of electronic equipment reality on pcb board after the electric sequence of each chip, directly in the logical code of CPLD chip according to pcb board on the electric sequence of each chip set the order that enables of each pin.
4. method as claimed in claim 3, is characterized in that, if need to the electric sequence of different chips on pcb board be adjusted, changes the logical code of enable pin order in CPLD chip according to the chip power order after adjusting.
5. the method for claim 1, is characterized in that, described method also comprises:
By the counting of CPLD Chip counter, realize the time delay to the each pin enable signal output of CPLD chip, and then realization was adjusted to the supply cell time of each chip power on pcb board.
6. control a device for multiple power supplies electric sequence, the electric sequence of the secondary power supply power supply of described application of installation each chip on to electronic equipment pcb board is controlled, and wherein said device is specially CPLD chip, it is characterized in that, described device comprises:
Whether the detecting unit that powers on, power on for detection of system, and when the system of detecting powers on, described device acquiescence is all invalid with the enable pin that on pcb board, each chip secondary power supply is connected;
Electric sequence control module, for enabling successively each pin according to the electric sequence of each chip on predefined pcb board;
Power supply enables unit, when receiving electric sequence control module, enables after the signal of each pin, enables the chip secondary power supply out-put supply being connected with this pin.
7. device as claimed in claim 6, is characterized in that, the electric sequence of different chips on described pcb board is specifically realized in the following way:
In the logical code of CPLD chip, according to the electric sequence of different chips on pcb board, set the order that enables each pin;
Described electric sequence control module, according to the order that enables each pin setting in the logical code of CPLD chip, enables each pin successively;
Power supply enables unit and enables after the signal of each pin when receiving electric sequence control module, enables the chip secondary power supply out-put supply being connected with this pin.
8. device as claimed in claim 7, is characterized in that, the electric sequence of different chips is adjusted on need to be to pcb board, enables the logical code of order by each pin in change CPLD chip.
9. device as claimed in claim 6, it is characterized in that, described electric sequence control module is realized the time delay output to pin enable signal by the counting of counter on CPLD chip, and then realization was adjusted the supply cell time of each chip power on pcb board.
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| CN201210383483.9A CN103728896A (en) | 2012-10-10 | 2012-10-10 | Method and device for controlling power-on sequence of multiple channels of power supplies |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
| CN106990727A (en) * | 2017-03-13 | 2017-07-28 | 山东和远智能科技股份有限公司 | The control method and device of i.MX6 series processors electric sequences |
| CN109176523A (en) * | 2018-09-29 | 2019-01-11 | 苏州博众机器人有限公司 | A kind of control circuit, circuit board and robot |
| CN110618742A (en) * | 2019-08-20 | 2019-12-27 | 苏州浪潮智能科技有限公司 | PDB board and working method thereof |
| CN113098254A (en) * | 2021-04-30 | 2021-07-09 | 美芯晟科技（北京）有限公司 | Parallel operation synchronous starting method and system |
| CN113835510A (en) * | 2021-09-27 | 2021-12-24 | 新华三信息安全技术有限公司 | Power supply control method and system |
| CN114720851A (en) * | 2022-04-01 | 2022-07-08 | 珠海妙存科技有限公司 | Chip power supply compatibility verification system and method |
| CN116106725A (en) * | 2023-03-24 | 2023-05-12 | 大唐恩智浦半导体（徐州）有限公司 | Multi-chip power-on test system, method and device and electronic equipment |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105207463A (en) * | 2015-10-28 | 2015-12-30 | 上海斐讯数据通信技术有限公司 | Input power supply control circuit |
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| CN109176523A (en) * | 2018-09-29 | 2019-01-11 | 苏州博众机器人有限公司 | A kind of control circuit, circuit board and robot |
| CN110618742A (en) * | 2019-08-20 | 2019-12-27 | 苏州浪潮智能科技有限公司 | PDB board and working method thereof |
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| CN113098254A (en) * | 2021-04-30 | 2021-07-09 | 美芯晟科技（北京）有限公司 | Parallel operation synchronous starting method and system |
| CN113098254B (en) * | 2021-04-30 | 2022-05-17 | 美芯晟科技(北京)股份有限公司 | Parallel operation synchronous starting method and system |
| CN113835510A (en) * | 2021-09-27 | 2021-12-24 | 新华三信息安全技术有限公司 | Power supply control method and system |
| CN114720851A (en) * | 2022-04-01 | 2022-07-08 | 珠海妙存科技有限公司 | Chip power supply compatibility verification system and method |
| CN116106725A (en) * | 2023-03-24 | 2023-05-12 | 大唐恩智浦半导体（徐州）有限公司 | Multi-chip power-on test system, method and device and electronic equipment |
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