CN106059503B - Voltage buffer amplifier - Google Patents
Voltage buffer amplifier Download PDFInfo
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- CN106059503B CN106059503B CN201610373501.3A CN201610373501A CN106059503B CN 106059503 B CN106059503 B CN 106059503B CN 201610373501 A CN201610373501 A CN 201610373501A CN 106059503 B CN106059503 B CN 106059503B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
- H03F1/0216—Continuous control
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45179—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
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Abstract
The invention discloses a kind of voltage buffer amplifiers, comprising: main body amplifying circuit and adaptive circuit；The operating current size of main body amplifying circuit is determined by the first electric current is heavy；Adaptive circuit, which is that the first electric current is heavy, to be provided image current and automatically adjusts the heavy size of current of the first electric current according to the working condition of main body amplifying circuit；When the voltage of positive inverting input terminal is equal, the first value of electric current that adaptive circuit keeps the first electric current heavy；When the voltage of positive inverting input terminal is unequal, electric current second value that adaptive circuit keeps the first electric current heavy；First value is less than second value, and the power consumption of voltage buffer amplifier is reduced by lesser first value；The output end charge-discharge velocity of the voltage buffer amplifier is improved by biggish second value to improve Slew Rate.The present invention can improve the Slew Rate of voltage buffer amplifier, improve establishing speed, reducing the stabilization time of voltage buffer amplifier for voltage buffer amplifier, while can also reduce power consumption.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit, more particularly to a kind of voltage buffer amplifier.
Background technique
Voltage needed for voltage buffer (voltage buffer) generally provides for circuit operation, to enhance its driving
Ability also avoids load effect to the output voltage of voltage buffer simultaneously.
Common-mode voltage needed for voltage buffer can provide sample phase in gradually-appoximant analog-digital converter is being converted
Stage does not need this common-mode voltage, can close voltage buffer in the conversion stage to save power consumption.
Since voltage buffer foundation and stabilization need the regular hour, this will limit the speed of analog-digital converter.In addition
To make buffer when driving other modules, quickly it can establish and settle out, buffer has to sufficiently large Slew Rate
And bandwidth, this just forces buffer to need very big quiescent current, this causes voltage buffer circuit to occupy entire modulus
The very big power consumption of converter.Therefore a quick response and stable low power consumption voltage buffer are to entire analog-digital converter
Design important in inhibiting.
Summary of the invention
Technical problem to be solved by the invention is to provide a kind of voltage buffer amplifiers, can improve voltage buffer amplifier
Slew Rate, improve stabilization time established speed, reduce voltage buffer amplifier of voltage buffer amplifier, while can also reduce
Power consumption.
In order to solve the above technical problems, voltage buffer amplifier provided by the invention includes: main body amplifying circuit and adaptive
Answer circuit.
The operating current size of the main body amplifying circuit is determined by the first electric current is heavy.
The adaptive circuit, which is that first electric current is heavy, provides image current and according to the work of the main body amplifying circuit
The heavy size of current of first electric current is automatically adjusted as state.
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is equal, the adaptive circuit
The first value of electric current for keeping first electric current heavy.
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is unequal, the adaptive electricity
The electric current second value that road keeps first electric current heavy.
First value is less than the second value, and the function of the voltage buffer amplifier is reduced by lesser first value
Consumption；The output end charge-discharge velocity of the voltage buffer amplifier is improved by the biggish second value to improve pendulum
Rate.
A further improvement is that the adaptive circuit includes the first differential amplifier circuit and the second differential amplifier circuit.
The normal phase input end of first differential amplifier circuit, the normal phase input end of second differential amplifier circuit and institute
The normal phase input end for stating main body amplifying circuit is connected, the inverting input terminal of first differential amplifier circuit, second difference
The inverting input terminal of amplifying circuit is connected with the inverting input terminal of the main body amplifying circuit.
The second of first difference inverted path of first differential amplifier circuit and second differential amplifier circuit is poor
The bottom end of positive phase path is divided to be all connected to the second electric current heavy.
The second of the positive phase path of the first difference of first differential amplifier circuit and second differential amplifier circuit is poor
It is heavy that the bottom end of point inverted path is all connected to third electric current.
It is active that the top of the positive phase path of second difference and the second difference inverted path all connects same first
Load circuit.
The electric current of first active pull-up circuit is mirrored to first electric current by the first mirror image circuit and sinks.
The heavy and described third electric current of second electric current is heavy, and mirror image and size of current are all third value each other.
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is equal, first difference is anti-
The electric current of phase path is N times of the electric current of the positive phase path of the second difference, and the electric current of the positive phase path of the first difference is institute
N times for stating the electric current of the second difference inverted path, N are greater than 1, and the size of current of first active pull-up circuit is the third
For value multiplied by 2/ (N+1), first active pull-up circuit is that the heavy mirror image of first electric current goes out the electric current that size is the first value.
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is unequal, first difference
There are an electric current approach 0, another electric current to approach the third value in positive phase path and the first difference inverted path, it is described
There is electric current approach 0, another electric current approach described the in the positive phase path of second difference and the second difference inverted path
The size of current of three values, first active pull-up circuit approaches the third value, and first active pull-up circuit is described
The heavy mirror image of first electric current goes out the electric current that size is second value.
A further improvement is that the first difference inverted path is made of the first NMOS tube, the first difference positive
Path is made of the second NMOS tube, and the second difference inverted path is made of third NMOS tube, the second difference positive road
Diameter is made of the 4th NMOS tube；First NMOS tube and second NMOS tube it is equal sized, the third NMOS tube and
4th NMOS tube it is equal sized, the breadth length ratio of the channel of first NMOS tube is the channel of the third NMOS tube
N times of breadth length ratio.
The grid of first NMOS tube is the inverting input terminal of first differential amplifier circuit, second NMOS tube
Grid be first differential amplifier circuit normal phase input end, the grid of the third NMOS tube is that second difference is put
The inverting input terminal of big circuit, the grid of the 4th NMOS tube are the normal phase input end of second differential amplifier circuit.
It is made of a further improvement is that second electric current is heavy the 5th NMOS tube, the third electric current is heavy by the 6th
NMOS tube composition.
The source electrode of 5th NMOS tube and the source electrode of the 6th NMOS tube are all grounded.
The drain electrode of 5th NMOS tube connects the source electrode of first NMOS tube and the source electrode of the 4th NMOS tube.
The drain electrode of 6th NMOS tube connects the source electrode of second NMOS tube and the source electrode of the third NMOS tube.
The grid of 5th NMOS tube and the grid of the 6th NMOS tube are all connected to the second mirror image circuit, and described
The heavy and described third electric current of two electric currents is heavy all to be obtained by the second mirror image circuit mirror image.
A further improvement is that second mirror image circuit include the 7th NMOS tube, the grid of the 7th NMOS tube and
Source electrode connects the grid of the 5th NMOS tube and the grid of the 6th NMOS tube, and the source electrode of the 7th NMOS tube is grounded,
First current source is connected to the source electrode of the 7th NMOS tube and provides electric current for second mirror image circuit.
A further improvement is that first current source is connected to the source of the 7th NMOS tube by the 8th NMOS tube
Pole, the drain electrode of the 9th NMOS tube connect the source electrode ground connection of the grid of the 7th NMOS tube, the 9th NMOS tube；Described 8th
The grid of NMOS tube connects first control signal, and the grid of the 9th NMOS tube connects second control signal, first control
Voltage buffer amplifier work when signal processed is high level and the second control signal is low level, first control
The voltage buffer amplifier stops working when signal processed is low level and the second control signal is high level.
A further improvement is that first active pull-up circuit is made of the tenth PMOS tube, the tenth PMOS tube
Source electrode connects supply voltage, and the grid of the tenth PMOS tube and drain electrode all connect the drain electrode of the third NMOS tube.
A further improvement is that first mirror image circuit is made of the 11st PMOS tube and the 12nd NMOS tube, it is described
First electric current is heavy to be made of the 13rd NMOS tube.
The grid of 11st PMOS tube connects the grid of the tenth PMOS tube, the source electrode of the 11st PMOS tube
Connect supply voltage, the drain electrode of the 11st PMOS tube connects the drain and gate and described the of the 12nd NMOS tube
The grid of 13 NMOS tubes, the source electrode of the 12nd NMOS tube and the source electrode of the 13rd NMOS tube are all grounded.
A further improvement is that the source electrode connection supply voltage of the 14th PMOS tube, drain electrode connect the tenth PMOS tube
Grid, the grid of the 14th PMOS tube connects first control signal.
The drain electrode of 15th NMOS tube connects the grid of the 13rd NMOS tube, and the source electrode of the 15th NMOS tube connects
The grid on ground, the 15th NMOS tube connects second control signal.
The voltage buffer is put when the first control signal is high level and the second control signal is low level
Big device work, the voltage buffer is put when the first control signal is low level and the second control signal is high level
Big device stops working.
A further improvement is that first resistor is connected between the drain electrode and supply voltage of first NMOS tube as institute
State the load of the first NMOS tube, second resistance is connected between the drain electrode and supply voltage of second NMOS tube as described the
The load of two NMOS tubes.
A further improvement is that the main body amplifying circuit include by the 16th NMOS tube and the 17th NMOS tube, it is described
It is heavy that the source electrode of 16th NMOS tube and the source electrode of the 17th NMOS tube all connect first electric current.
The drain electrode of 16th NMOS tube is connected to supply voltage by the second active pull-up circuit；Described 17th
The drain electrode of NMOS tube is connected to supply voltage by third active pull-up circuit.
The grid of 16th NMOS tube is normal phase input end, and the grid of the 17th NMOS tube is anti-phase input
End；Output end of the drain electrode of 17th NMOS tube as voltage buffer amplifier.
A further improvement is that second active pull-up circuit is made of the 18th PMOS tube, the third is active negative
Circuit is carried to be made of the 19th PMOS tube.
The source electrode of 18th PMOS tube and the source electrode of the 19th PMOS tube all connect supply voltage.
The grid of 18th PMOS tube and drain electrode connect the grid and the described 16th of the 19th PMOS tube
The drain electrode of NMOS tube.
The drain electrode of 19th PMOS tube connects the drain electrode of the 17th NMOS tube.
A further improvement is that the source electrode connection supply voltage of the 20th PMOS tube, drain electrode connect the 18th PMOS
The grid of the grid of pipe, the 20th PMOS tube connects first control signal.
Voltage buffer amplifier of the present invention by setting adaptive circuit, can automatically according to circuit working condition it is adaptive
The heavy size of first electric current of the control main body amplifying circuit answered and thereby the operating current size for controlling main body amplifying circuit, electricity
Pressure buffer amplifier can not be waited in the voltage of the positive inverting input terminal of the front body amplifying circuit of stabilization, and adaptive circuit can be
First electric current sinks the biggish electric current of mirror image, so as to improve the Slew Rate of voltage buffer amplifier, improve voltage buffer amplifier
The stabilization time established speed, reduce voltage buffer amplifier.After voltage buffer amplifier is stablized, adaptive circuit can
For the first electric current sink the lower electric current of mirror image, so as to reduce circuit power consumption；So this invention removes improve in the prior art
Circuit establishes speed and needs larger current and reduce circuit power consumption and need contradiction between smaller current, mentions so as to realize simultaneously
Height establishes speed and reduces power consumption.
Detailed description of the invention
The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:
Fig. 1 is the circuit diagram of first embodiment of the invention；
Fig. 2 is the current diagram of the first establishment process of circuit shown in Fig. 1；
Fig. 3 is the current diagram of the second establishment process of circuit shown in Fig. 1；
Fig. 4 is the circuit diagram of second embodiment of the invention；
Fig. 5 is the application drawing of second embodiment of the invention.
Specific embodiment
As shown in Figure 1, being the circuit diagram of first embodiment of the invention, first embodiment of the invention voltage buffer amplifier
101 include: main body amplifying circuit 102 and adaptive circuit 103.
The operating current size of the main body amplifying circuit 102 is determined by the first electric current is heavy.
The adaptive circuit 103, which is that first electric current is heavy, provides image current and according to the main body amplifying circuit
102 working condition automatically adjusts the heavy size of current of first electric current.
It is described adaptive when the voltage of the normal phase input end of the main body amplifying circuit 102 and inverting input terminal is equal
The first value of electric current that circuit 103 keeps first electric current heavy.
It is described adaptive when the voltage of the normal phase input end of the main body amplifying circuit 102 and inverting input terminal is unequal
The electric current second value for answering circuit 103 to keep first electric current heavy.
First value is less than the second value, and the function of the voltage buffer amplifier is reduced by lesser first value
Consumption；The output end charge-discharge velocity of the voltage buffer amplifier is improved by the biggish second value to improve pendulum
Rate.
In first embodiment of the invention, the adaptive circuit 103 includes that the first differential amplifier circuit and the second difference are put
Big circuit.
The normal phase input end of first differential amplifier circuit, the normal phase input end of second differential amplifier circuit and institute
The normal phase input end for stating main body amplifying circuit 102 is connected and meets positive phase input signal VIP, first differential amplifier circuit it is anti-
The inverting input terminal phase of phase input terminal, the inverting input terminal of second differential amplifier circuit and the main body amplifying circuit 102
Company and reversed phase input signal VIN.
The second of first difference inverted path of first differential amplifier circuit and second differential amplifier circuit is poor
The bottom end of positive phase path is divided to be all connected to the second electric current heavy.
The second of the positive phase path of the first difference of first differential amplifier circuit and second differential amplifier circuit is poor
It is heavy that the bottom end of point inverted path is all connected to third electric current.
It is active that the top of the positive phase path of second difference and the second difference inverted path all connects same first
Load circuit.
The electric current of first active pull-up circuit is mirrored to first electric current by the first mirror image circuit and sinks.
The heavy and described third electric current of second electric current is heavy, and mirror image and size of current are all third value each other.
When the voltage of the normal phase input end of the main body amplifying circuit 102 and inverting input terminal is equal, described first is poor
Dividing the electric current of inverted path is N times of the electric current of the positive phase path of the second difference, the electric current of the positive phase path of the first difference
It is N times of the electric current of the second difference inverted path, N is greater than 1, and the size of current of first active pull-up circuit is described
For third value multiplied by 2/ (N+1), first active pull-up circuit is that the heavy mirror image of first electric current goes out the electricity that size is the first value
Stream.
When the voltage of the normal phase input end of the main body amplifying circuit 102 and inverting input terminal is unequal, described first
There are electric current approach 0, another electric current to approach the third value in the positive phase path of difference and the first difference inverted path,
There are an electric current approach 0, another electric current approach institute in the positive phase path of second difference and the second difference inverted path
Third value is stated, the size of current of first active pull-up circuit approaches the third value, and first active pull-up circuit is
The heavy mirror image of first electric current goes out the electric current that size is second value.
Preferably, the first difference inverted path is made of the first NMOS tube M1, the positive phase path of the first difference by
Second NMOS tube M2 composition, the second difference inverted path are made of third NMOS tube M3, the positive phase path of the second difference
It is made of the 4th NMOS tube M4；Equal sized, the 3rd NMOS of the first NMOS tube M1 and the second NMOS tube M2
Pipe M3's and the 4th NMOS tube M4 is equal sized, and the breadth length ratio of the channel of the first NMOS tube M1 is the 3rd NMOS
N times of the breadth length ratio of the channel of pipe M3.
The grid of the first NMOS tube M1 is the inverting input terminal of first differential amplifier circuit, the 2nd NMOS
The grid of pipe M2 is the normal phase input end of first differential amplifier circuit, and the grid of the third NMOS tube M3 is described second
The inverting input terminal of differential amplifier circuit, the grid of the 4th NMOS tube M4 are that the positive of second differential amplifier circuit is defeated
Enter end.
Second electric current is heavy to be made of the 5th NMOS tube M5, and the third electric current is heavy to be made of the 6th NMOS tube M6.
The source electrode of the 5th NMOS tube M5 and the source electrode of the 6th NMOS tube M6 are all grounded GND.
The drain electrode of the 5th NMOS tube M5 connects the source electrode and the 4th NMOS tube M4 of the first NMOS tube M1
Source electrode.
The drain electrode of the 6th NMOS tube M6 connects the source electrode and the third NMOS tube M3 of the second NMOS tube M2
Source electrode.
The grid of the 5th NMOS tube M5 and the grid of the 6th NMOS tube M6 are all connected to the second mirror image circuit, institute
State that the heavy and described third electric current of the second electric current is heavy all to be obtained by the second mirror image circuit mirror image.
Second mirror image circuit includes the 7th NMOS tube M7, described in the grid of the 7th NMOS tube M7 is connected with source electrode
The grid of the grid of 5th NMOS tube M5 and the 6th NMOS tube M6, the source electrode of the 7th NMOS tube M7 are grounded GND, and first
Current source IDC is connected to the source electrode of the 7th NMOS tube M7 and provides electric current for second mirror image circuit.
First active pull-up circuit is made of the tenth PMOS tube M10, and the source electrode of the tenth PMOS tube M10 connects electricity
The grid of source voltage VDD, the tenth PMOS tube M10 and drain electrode all connect the drain electrode of the third NMOS tube M3.
The first mirror image circuit is stated to be made of the 11st PMOS tube M11 and the 12nd NMOS tube M12, first electric current it is heavy by
13rd NMOS tube M13 composition.
The grid of the 11st PMOS tube M11 connects the grid of the tenth PMOS tube M10, the 11st PMOS tube
The source electrode of M11 connects supply voltage VDD, and the drain electrode of the 11st PMOS tube M11 connects the leakage of the 12nd NMOS tube M12
The grid of pole and grid and the 13rd NMOS tube M13, the source electrode and the described 13rd of the 12nd NMOS tube M12
The source electrode of NMOS tube M13 is all grounded GND.
First resistor R1 is connected between the drain electrode and supply voltage VDD of the first NMOS tube M1 as described first
The load of NMOS tube M1, second resistance R2 are connected between the drain electrode and supply voltage VDD of the second NMOS tube M2 as institute
State the load of the second NMOS tube M2.
The main body amplifying circuit 102 includes the by the 16th NMOS tube M16 and the 17th NMOS tube M17 the described 16th
The source electrode of the source electrode of NMOS tube M16 and the 17th NMOS tube M17 all connect the heavy i.e. connection the 13rd of first electric current
The drain electrode of NMOS tube M13.
The drain electrode of the 16th NMOS tube M16 is connected to supply voltage VDD by the second active pull-up circuit；Described
The drain electrode of 17 NMOS tube M17 is connected to supply voltage VDD by third active pull-up circuit.
The grid of the 16th NMOS tube M16 is normal phase input end, and the grid of the 17th NMOS tube M17 is reverse phase
Input terminal；Output end of the drain electrode of the 17th NMOS tube M17 as voltage buffer amplifier.
Second active pull-up circuit is made of the 18th PMOS tube M18, and the third active pull-up circuit is by the tenth
Nine PMOS tube M19 composition.
The source electrode of the 18th PMOS tube M18 and the source electrode of the 19th PMOS tube M19 all connect supply voltage
VDD。
The grid of the 18th PMOS tube M18 and drain electrode connect the grid of the 19th PMOS tube M19 and described
The drain electrode of 16th NMOS tube M16.
The drain electrode of the 19th PMOS tube M19 connects the drain electrode of the 17th NMOS tube M17.
As shown in Figure 1 it is found that positive is defeated at this time in the voltage buffer amplifier steady operation of first embodiment of the invention
Enter signal VIP and rp input signal VIN is equal in magnitude, the first difference inverted path, that is, first NMOS tube M1 electricity
Stream is N times of the positive phase path of the second difference, that is, the 4th NMOS tube M4 electric current, and the positive phase path of the first difference is
The electric current of second NMOS tube M2 is N times of the second difference inverted path, that is, third NMOS tube M3 electric current, described the
The one active pull-up circuit i.e. size of current of the tenth NMOS tube M10 for small current value the 4th NMOS tube M4 and institute
The superposition of the electric current of third NMOS tube M3 is stated, is the third value multiplied by 2/ (N+1), first active pull-up circuit is described
The heavy mirror image of first electric current goes out the electric current that size is the first value, so the first electric current is heavy at this time has lesser electric current, the electric current is flat
The 16th NMOS tube M16 and the 17th NMOS tube M17 is separately flowed into afterwards, this can reduce power consumption in circuit stability.
When voltage buffer amplifier is unstable, this can be there are two types of situation:
As shown in Fig. 2, being the current diagram of the first establishment process of circuit shown in Fig. 1；The first situation is that positive is defeated
The value for entering signal VIP is greater than the value of rp input signal VIN, and the second NMOS tube M2 and the 4th NMOS tube M4 has larger electricity at this time
Stream, the electric current of the first NMOS tube M1 and third NMOS tube M3 level off to 0, and the electric current of the 6th NMOS tube M6 is flowed into second substantially
In NMOS tube M2, the electric current of the 5th NMOS tube M5 is flowed into the 4th NMOS tube M4 substantially and is flowed into the tenth PMOS tube in turn
In M10, and being mirrored in the 13rd NMOS tube M13 by the 11st NMOS tube M11 and the 12nd NMOS tube M12；16th
The 16th NMOS tube M16 is connected in NMOS tube M16 and the 17th NMOS tube M17, and the electric current of the 17th NMOS tube M17 is close to 0,
The electric current of 13rd NMOS tube M13 flows through the 16th NMOS tube M16 and the 18th NMOS tube M18 and is mirrored to the 19th NMOS tube
It realizes after M19 and charges to inverting input terminal, thus make the positive phase input signal VIP of rp input signal VINN fast approaching, thus
It can make output signal VOUT fast and stable, improve Slew Rate, reduce settling time.
As shown in figure 3, being the current diagram of the second establishment process of circuit shown in Fig. 1；The first situation is that positive is defeated
The value for entering signal VIP is less than the value of rp input signal VIN, at this time the electric current approach of the second NMOS tube M2 and the 4th NMOS tube M4
There is larger current in 0, first NMOS tube M1 and third NMOS tube M3, and the electric current of the 5th NMOS tube M5 is flowed into first substantially
In NMOS tube M1, the electric current of the 6th NMOS tube M6 is flowed into third NMOS tube M3 substantially and is flowed into the tenth PMOS tube in turn
In M10, and being mirrored in the 13rd NMOS tube M13 by the 11st NMOS tube M11 and the 12nd NMOS tube M12；16th
The electric current of the 16th NMOS tube M16 is close to 0 in NMOS tube M16 and the 17th NMOS tube M17, and the 17th NMOS tube M17 is connected,
The electric current of 13rd NMOS tube M13 is realized after flowing through the 17th NMOS tube M17 to inverting input terminal electric discharge, to make anti-phase input
The positive phase input signal VIP of signal VINN fast approaching improves Slew Rate so as to make output signal VOUT fast and stable, and reduction is built
Between immediately.
As shown in figure 4, being the circuit diagram of second embodiment of the invention voltage buffer amplifier 101a, the present invention second is implemented
Example voltage buffer amplifier 101a is to do further to obtain on the basis of first embodiment voltage buffer amplifier 101, specifically
For second embodiment of the invention further include:
The first current source IDC is connected to the source electrode of the 7th NMOS tube M7 by the 8th NMOS tube M8, and the 9th
The drain electrode of NMOS tube connects the grid of the 7th NMOS tube M7, the source electrode of the 9th NMOS tube M9 is grounded GND；Described 8th
The grid of NMOS tube M8 connects first control signal PU, and the grid of the 9th NMOS tube M9 connects second control signal PD.
The source electrode connection supply voltage VDD of 14th PMOS tube M14, drain electrode connect the grid of the tenth PMOS tube M10,
The grid of the 14th PMOS tube M14 connects first control signal PU.
The drain electrode of 15th NMOS tube M15 connects the grid of the 13rd NMOS tube M13, the 15th NMOS tube
The source electrode of M15 is grounded GND, and the grid of the 15th NMOS tube M15 connects second control signal PD.
The source electrode connection supply voltage VDD of 20th PMOS tube M20, drain electrode connect the grid of the 18th PMOS tube M18
The grid of pole, the 20th PMOS tube M20 connects first control signal PU.
The voltage is slow when the first control signal PU is high level and the second control signal PD is low level
Amplifier operation is rushed, the electricity when first control signal PU is low level and the second control signal PD is high level
Pressure buffer amplifier stops working.
If Fig. 5 is the application drawing of second embodiment of the invention, resistance R3 and R4 is divided to obtain defeated to supply voltage VDD
Enter voltage VCM be input to the normal phase input end of voltage buffer amplifier 101a i.e.+end, the source and drain of PMOS tube M21 is connected to resistance
For controlling the top of resistance R3 and the connection of supply voltage VDD between the top and supply voltage VDD of R3；PMOS tube M22 connects
Connect the bottom end between the bottom end and ground GND of resistance R4 for controlling resistance R4 and the connection of ground GND, the grid of PMOS tube M21
Second control signal PD is connected, the grid of PMOS tube M22 connects the first control signal PU.Voltage buffer amplifier 101a's
Output end be connected to inverting input terminal i.e.-end namely output signal VOUT connection rp input signal VIN.Output signal VOUT connects
It is connected to load circuit 102.Voltage buffer amplifier 101a is connected into unit gain form, when the first control signal PU is high electricity
Flat, when second control signal PD is low level, voltage buffer amplifier 101a starts to work, and output voltage VO UT is made to follow input
Voltage VCM.
When first control signal PU is low level, and second control signal PD is high level, voltage buffer amplifier 101a
It stops working.Load circuit 102 may change the voltage value i.e. value of output voltage VO UT of output end at this time.
The present invention has been described in detail through specific embodiments, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many modification and improvement, these are also answered
It is considered as protection scope of the present invention.
Claims (12)
1. a kind of voltage buffer amplifier characterized by comprising main body amplifying circuit and adaptive circuit；
The operating current size of the main body amplifying circuit is determined by the first electric current is heavy；
The adaptive circuit, which is that first electric current is heavy, provides image current and according to the work shape of the main body amplifying circuit
State automatically adjusts the heavy size of current of first electric current；
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is equal, the adaptive circuit makes institute
Stating the heavy electric current of the first electric current is the first value；
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is unequal, the adaptive circuit makes
The heavy electric current of first electric current is second value；
First value is less than the second value, and the power consumption of the voltage buffer amplifier is reduced by lesser first value；
The output end charge-discharge velocity of the voltage buffer amplifier is improved by the biggish second value to improve Slew Rate；
The adaptive circuit includes the first differential amplifier circuit and the second differential amplifier circuit；
The normal phase input end of first differential amplifier circuit, the normal phase input end of second differential amplifier circuit and the master
The normal phase input end of body amplifying circuit is connected, the inverting input terminal of first differential amplifier circuit, second differential amplification
The inverting input terminal of circuit is connected with the inverting input terminal of the main body amplifying circuit；
First difference inverted path of first differential amplifier circuit and the second difference of second differential amplifier circuit are just
It is heavy that the bottom end of phase path is all connected to the second electric current；
The positive phase path of the first difference of first differential amplifier circuit and the second difference of second differential amplifier circuit are anti-
It is heavy that the bottom end of phase path is all connected to third electric current；
The top of the positive phase path of second difference and the second difference inverted path all connects same first active load
Circuit；
The electric current of first active pull-up circuit is mirrored to first electric current by the first mirror image circuit and sinks；
The heavy and described third electric current of second electric current is heavy, and mirror image and size of current are all third value each other；
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is equal, the first difference reverse phase road
The electric current of diameter is N times of electric current of the positive phase path of the second difference, and the electric current of the positive phase path of the first difference is described the
N times of the electric current of two difference inverted paths, N are greater than 1, and the size of current of first active pull-up circuit is that the third value multiplies
With 2/ (N+1), first active pull-up circuit is that the heavy mirror image of first electric current goes out the electric current that size is the first value；
When the voltage of the normal phase input end of the main body amplifying circuit and inverting input terminal is unequal, the first difference positive
There are electric current approach 0, another electric current to approach the third value in path and the first difference inverted path, described second
There are electric current approach 0, another electric current to approach the third value in the positive phase path of difference and the second difference inverted path,
The size of current of first active pull-up circuit approaches the third value, and first active pull-up circuit is first electricity
It flows heavy mirror image and goes out the electric current that size is second value.
2. voltage buffer amplifier as described in claim 1, it is characterised in that:
The first difference inverted path is made of the first NMOS tube, and the positive phase path of the first difference is by the second NMOS tube group
At the second difference inverted path is made of third NMOS tube, and the positive phase path of the second difference is made of the 4th NMOS tube；
Equal sized, the size of the third NMOS tube and the 4th NMOS tube of first NMOS tube and second NMOS tube
Equal, the breadth length ratio of the channel of first NMOS tube is N times of the breadth length ratio of the channel of the third NMOS tube；
The grid of first NMOS tube is the inverting input terminal of first differential amplifier circuit, the grid of second NMOS tube
The normal phase input end of extremely described first differential amplifier circuit, the grid of the third NMOS tube are the second differential amplification electricity
The inverting input terminal on road, the grid of the 4th NMOS tube are the normal phase input end of second differential amplifier circuit.
3. voltage buffer amplifier as claimed in claim 2, it is characterised in that: second electric current is heavy by the 5th NMOS tube group
At the third electric current is heavy to be made of the 6th NMOS tube；
The source electrode of 5th NMOS tube and the source electrode of the 6th NMOS tube are all grounded；
The drain electrode of 5th NMOS tube connects the source electrode of first NMOS tube and the source electrode of the 4th NMOS tube；
The drain electrode of 6th NMOS tube connects the source electrode of second NMOS tube and the source electrode of the third NMOS tube；
The grid of 5th NMOS tube and the grid of the 6th NMOS tube are all connected to the second mirror image circuit, second electricity
The heavy and described third electric current of stream is heavy all to be obtained by the second mirror image circuit mirror image.
4. voltage buffer amplifier as claimed in claim 3, it is characterised in that: second mirror image circuit includes the 7th NMOS
Pipe, the grid of the 7th NMOS tube connect the grid of the 5th NMOS tube and the grid of the 6th NMOS tube with source electrode,
The source electrode of 7th NMOS tube is grounded, and the first current source is connected to the source electrode of the 7th NMOS tube and is second mirror image
Circuit provides electric current.
5. voltage buffer amplifier as claimed in claim 4, it is characterised in that: first current source is connected by the 8th NMOS tube
It is connected to the source electrode of the 7th NMOS tube, the drain electrode of the 9th NMOS tube connects the grid of the 7th NMOS tube, the described 9th
The source electrode of NMOS tube is grounded；The grid of 8th NMOS tube connects first control signal, and the grid of the 9th NMOS tube connects
Second control signal is connect, the voltage when first control signal is high level and the second control signal is low level
Buffer amplifier work, the voltage when first control signal is low level and the second control signal is high level
Buffer amplifier stops working.
6. voltage buffer amplifier as claimed in claim 2, it is characterised in that: first active pull-up circuit is by the tenth PMOS
Described in pipe composition, the source electrode connection supply voltage of the tenth PMOS tube, the grid of the tenth PMOS tube and drain electrode all connect
The drain electrode of third NMOS tube.
7. voltage buffer amplifier as claimed in claim 6, it is characterised in that: first mirror image circuit is by the 11st PMOS tube
It is formed with the 12nd NMOS tube, first electric current is heavy to be made of the 13rd NMOS tube；
The grid of 11st PMOS tube connects the grid of the tenth PMOS tube, the source electrode connection of the 11st PMOS tube
Supply voltage, the drain electrode of the 11st PMOS tube connect the drain and gate and the described 13rd of the 12nd NMOS tube
The grid of NMOS tube, the source electrode of the 12nd NMOS tube and the source electrode of the 13rd NMOS tube are all grounded.
8. voltage buffer amplifier as claimed in claim 7, it is characterised in that: the source electrode connection power supply electricity of the 14th PMOS tube
Pressure, drain electrode connect the grid of the tenth PMOS tube, and the grid of the 14th PMOS tube connects first control signal；
The drain electrode of 15th NMOS tube connects the grid of the 13rd NMOS tube, and the source electrode of the 15th NMOS tube is grounded,
The grid of 15th NMOS tube connects second control signal；
The voltage buffer amplifier when first control signal is high level and the second control signal is low level
Work, the voltage buffer amplifier when first control signal is low level and the second control signal is high level
It stops working.
9. voltage buffer amplifier as claimed in claim 2, it is characterised in that: first resistor is connected to first NMOS tube
Load between drain electrode and supply voltage as first NMOS tube, second resistance are connected to the drain electrode of second NMOS tube
Load between supply voltage as second NMOS tube.
10. the voltage buffer amplifier as described in any claim in claim 1-9, it is characterised in that: the main body amplification
Circuit includes by the 16th NMOS tube and the 17th NMOS tube, the source electrode of the 16th NMOS tube and the 17th NMOS tube
Source electrode all to connect first electric current heavy；
The drain electrode of 16th NMOS tube is connected to supply voltage by the second active pull-up circuit；17th NMOS tube
Drain electrode supply voltage is connected to by third active pull-up circuit；
The grid of 16th NMOS tube is normal phase input end, and the grid of the 17th NMOS tube is inverting input terminal；Institute
State output end of the drain electrode of the 17th NMOS tube as voltage buffer amplifier.
11. voltage buffer amplifier as claimed in claim 10, it is characterised in that: second active pull-up circuit is by the 18th
PMOS tube composition, the third active pull-up circuit are made of the 19th PMOS tube；
The source electrode of 18th PMOS tube and the source electrode of the 19th PMOS tube all connect supply voltage；
The grid of 18th PMOS tube and drain electrode connect the grid and the 16th NMOS of the 19th PMOS tube
The drain electrode of pipe；
The drain electrode of 19th PMOS tube connects the drain electrode of the 17th NMOS tube.
12. voltage buffer amplifier as claimed in claim 11, it is characterised in that:
The source electrode connection supply voltage of 20th PMOS tube, draining connects the grid of the 18th PMOS tube, and the described 20th
The grid of PMOS tube connects first control signal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610373501.3A CN106059503B (en) | 2016-05-31 | 2016-05-31 | Voltage buffer amplifier |
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| CN201610373501.3A CN106059503B (en) | 2016-05-31 | 2016-05-31 | Voltage buffer amplifier |
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| CN106059503B true CN106059503B (en) | 2019-06-11 |
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| CN109302173A (en) * | 2018-12-10 | 2019-02-01 | 上海艾为电子技术股份有限公司 | Input buffer |
| WO2022134042A1 (en) * | 2020-12-25 | 2022-06-30 | 中国科学院微电子研究所 | Signal driving system with constant slew rate |
| CN112737564A (en) * | 2020-12-25 | 2021-04-30 | 中国科学院微电子研究所 | Constant slew rate signal driving system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645658A (en) * | 2009-05-27 | 2010-02-10 | 北京中星微电子有限公司 | Flyback power converter and loop control method thereof |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN103259492A (en) * | 2013-05-28 | 2013-08-21 | 上海贝岭股份有限公司 | Video driver output amplifier circuit |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101645658A (en) * | 2009-05-27 | 2010-02-10 | 北京中星微电子有限公司 | Flyback power converter and loop control method thereof |
| CN102789257A (en) * | 2012-08-31 | 2012-11-21 | 电子科技大学 | Low dropout regulator |
| CN103259492A (en) * | 2013-05-28 | 2013-08-21 | 上海贝岭股份有限公司 | Video driver output amplifier circuit |
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